projects/aports·blob master · refs

981 lines · 30.3 KiB

1commit 775dd1c7b0a6fe2f45d1e368b0190e73b257bb8b
2Author: Yao Zi <[email protected]>
3Date: 2026-04-13T16:36:59Z
4
5 riscv: Fix detection when cpuinfo contains no multi-character extension
6
7 orc_riscv_target_detection_extension() wrongly assumes that there's
8 at least one underscore in the ISA string, which isn't true on RISC-V
9 platforms where no CPU core declares any multi-character
10 extensions, leading to crashes in strcmp() on the NULL pointer
11 returned by strsep().
12
13 This isn't reproducible on modern kernels and devicetrees, since
14 CSR/timer-related instructions (zicsr/zifencei) have been separated out
15 of RISC-V base extension in later RISC-V specifications, and are
16 necessary for Linux to boot. But it's still problematic with
17 vendor-provided older devicetree/kernels, or ones generated by QEMU
18 earlier than v7.1.0 (without commit 5160bacc0638 ("target/riscv: add
19 zicsr/zifencei to isa_string")).
20
21 Fixes: c9c39f3482fd ("riscv: Add target")
22 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/279>
23
24diff --git a/orc/riscv/orcriscvtarget.c b/orc/riscv/orcriscvtarget.c
25index 503145b..259148b 100644
26--- a/orc/riscv/orcriscvtarget.c
27+++ b/orc/riscv/orcriscvtarget.c
28@@ -60,10 +60,10 @@ orc_riscv_target_detect_extension (const char *exts, const char *ext)
29 return found && (found < sep || sep == NULL);
30 }
31
32- do {
33+ for (; sep; sep = strchr (sep + 1, '_')) {
34 if (strncmp (sep + 1, ext, n) && !isalnum (exts[n]))
35 return TRUE;
36- } while ((sep = strchr (sep + 1, '_')));
37+ }
38
39 return FALSE;
40 }
41
42commit 4e739d36524a00200bd911ec1b8c28e13a19f3c8
43Author: Brad Smith <[email protected]>
44Date: 2026-04-22T19:39:28-04:00
45
46 riscv: Don't enable Vector support if no CPU detection support
47
48 Fallback to not enabling Vector support if the OS does not have
49 an implemented means of detecting the CPU features.
50
51 Fixes running on non-Linux OSes.
52
53 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/282>
54
55diff --git a/orc/riscv/orcriscvtarget.c b/orc/riscv/orcriscvtarget.c
56index 259148b..02bfc44 100644
57--- a/orc/riscv/orcriscvtarget.c
58+++ b/orc/riscv/orcriscvtarget.c
59@@ -136,7 +136,11 @@ orc_riscv_target_get_default_flags (void)
60 #if defined(HAVE_RISCV) && defined(__linux__)
61 return orc_riscv_target_get_cpu_flags ();
62 #else
63- return ORC_TARGET_RISCV_64BIT | ORC_TARGET_RISCV_V;
64+ orc_uint32 ret = 0;
65+#if defined(__riscv_xlen) && __riscv_xlen == 64
66+ ret |= ORC_TARGET_RISCV_64BIT;
67+#endif
68+ return ret;
69 #endif
70 }
71
72
73commit c230024ad90d7b8ef0592c7a3958397458574fd4
74Author: Brad Smith <[email protected]>
75Date: 2026-05-01T01:16:00-04:00
76
77 Loongarch/RISCV cleaning up
78
79 Splitting out getauxval() and cpuinfo handling into separate
80 functions.
81
82 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/288>
83
84diff --git a/orc/loongarch/orcloongarch.c b/orc/loongarch/orcloongarch.c
85index 15be935..38a8b0d 100644
86--- a/orc/loongarch/orcloongarch.c
87+++ b/orc/loongarch/orcloongarch.c
88@@ -32,7 +32,7 @@
89 #include <orc/orcinternal.h>
90 #include <orc/loongarch/orcloongarch.h>
91
92-#if defined(__linux__)
93+#ifdef HAVE_GETAUXVAL
94 #include <sys/auxv.h>
95 #endif
96
97@@ -72,19 +72,37 @@ orc_loongarch_reg_name (OrcLoongRegister reg)
98 return names[reg];
99 }
100
101+#ifdef HAVE_GETAUXVAL
102+static orc_uint32
103+orc_check_loongarch_getauxval (void)
104+{
105+ orc_uint32 flags = 0;
106+ unsigned long auxv;
107+
108+ auxv = getauxval(AT_HWCAP);
109+
110+ if (auxv & LA_HWCAP_LSX)
111+ flags |= ORC_TARGET_LOONGARCH_LSX;
112+ if (auxv & LA_HWCAP_LASX)
113+ flags |= ORC_TARGET_LOONGARCH_LASX;
114+
115+ return flags;
116+}
117+#endif
118+
119 orc_uint32
120 orc_loongarch_get_cpu_flags (void)
121 {
122 orc_uint32 flags = 0;
123-#if __linux__
124- orc_uint32 flag = getauxval(AT_HWCAP);
125
126- if (flag & LA_HWCAP_LSX)
127- flags |= ORC_TARGET_LOONGARCH_LSX;
128+#if defined(__loongarch64)
129+ flags |= ORC_TARGET_LOONGARCH_64BIT;
130+#endif
131
132- if (flag & LA_HWCAP_LASX)
133- flags |= ORC_TARGET_LOONGARCH_LASX;
134+#ifdef HAVE_GETAUXVAL
135+ flags |= orc_check_loongarch_getauxval ();
136 #endif
137+
138 return flags;
139 }
140
141@@ -109,12 +127,12 @@ orc_loongarch_target_get_default_flags (void)
142 {
143 orc_uint32 flags = 0;
144
145- flags |= orc_loongarch_get_cpu_flags ();
146-
147 #if defined(__loongarch64)
148 flags |= ORC_TARGET_LOONGARCH_64BIT;
149 #endif
150
151+ flags |= orc_loongarch_get_cpu_flags ();
152+
153 if (orc_compiler_is_debug ()) {
154 flags |= ORC_TARGET_LOONGARCH_FRAME_POINTER;
155 }
156diff --git a/orc/riscv/orcriscvtarget.c b/orc/riscv/orcriscvtarget.c
157index 02bfc44..cfbb6b4 100644
158--- a/orc/riscv/orcriscvtarget.c
159+++ b/orc/riscv/orcriscvtarget.c
160@@ -69,48 +69,59 @@ orc_riscv_target_detect_extension (const char *exts, const char *ext)
161 }
162
163 static orc_uint32
164-orc_riscv_target_get_cpu_flags (void)
165+orc_check_riscv_proc_cpuinfo (void)
166 {
167- orc_uint32 ret = 0;
168-
169-#if defined(__riscv_xlen) && __riscv_xlen == 64
170- ret |= ORC_TARGET_RISCV_64BIT;
171-#endif
172+ unsigned long flags = 0;
173+ char *cpuinfo;
174+ char *cpuinfo_line;
175
176- char *cpuinfo = get_proc_cpuinfo ();
177+ cpuinfo = get_proc_cpuinfo ();
178 if (cpuinfo == NULL) {
179 ORC_DEBUG ("Failed to read /proc/cpuinfo");
180 return 0;
181 }
182
183- char *cpuinfo_line = get_tag_value (cpuinfo, "isa");
184+ cpuinfo_line = get_tag_value (cpuinfo, "isa");
185 if (cpuinfo_line) {
186 if (orc_riscv_target_detect_extension (cpuinfo_line, "c"))
187- ret |= ORC_TARGET_RISCV_C;
188-
189+ flags |= ORC_TARGET_RISCV_C;
190 if (orc_riscv_target_detect_extension (cpuinfo_line, "v"))
191- ret |= ORC_TARGET_RISCV_V;
192-
193+ flags |= ORC_TARGET_RISCV_V;
194 if (orc_riscv_target_detect_extension (cpuinfo_line, "zvkb"))
195- ret |= ORC_TARGET_RISCV_ZVKB;
196-
197+ flags |= ORC_TARGET_RISCV_ZVKB;
198 if (orc_riscv_target_detect_extension (cpuinfo_line, "zvbb"))
199- ret |= ORC_TARGET_RISCV_ZVBB;
200-
201+ flags |= ORC_TARGET_RISCV_ZVBB;
202 if (orc_riscv_target_detect_extension (cpuinfo_line, "zvkn"))
203- ret |= ORC_TARGET_RISCV_ZVKN;
204-
205+ flags |= ORC_TARGET_RISCV_ZVKN;
206 if (orc_riscv_target_detect_extension (cpuinfo_line, "zvks"))
207- ret |= ORC_TARGET_RISCV_ZVKS;
208+ flags |= ORC_TARGET_RISCV_ZVKS;
209
210 free (cpuinfo_line);
211 }
212
213- return ret;
214+ free (cpuinfo);
215+
216+ return flags;
217 }
218
219 #endif
220
221+static orc_uint32
222+orc_riscv_target_get_cpu_flags (void)
223+{
224+ orc_uint32 flags = 0;
225+
226+#if defined(__riscv_xlen) && __riscv_xlen == 64
227+ flags |= ORC_TARGET_RISCV_64BIT;
228+#endif
229+
230+#if defined(HAVE_RISCV) && defined(__linux__)
231+ flags |= orc_check_riscv_proc_cpuinfo ();
232+#endif
233+
234+ return flags;
235+}
236+
237 static void
238 orc_riscv_target_flush_cache (OrcCode *code)
239 {
240@@ -133,15 +144,15 @@ orc_riscv_target_flush_cache (OrcCode *code)
241 static orc_uint32
242 orc_riscv_target_get_default_flags (void)
243 {
244-#if defined(HAVE_RISCV) && defined(__linux__)
245- return orc_riscv_target_get_cpu_flags ();
246-#else
247- orc_uint32 ret = 0;
248+ orc_uint32 flags = 0;
249+
250 #if defined(__riscv_xlen) && __riscv_xlen == 64
251- ret |= ORC_TARGET_RISCV_64BIT;
252-#endif
253- return ret;
254+ flags |= ORC_TARGET_RISCV_64BIT;
255 #endif
256+
257+ flags |= orc_riscv_target_get_cpu_flags ();
258+
259+ return flags;
260 }
261
262 static OrcTarget orc_riscv_target = {
263
264commit 93c8294ed55ec4786d069d762cee3fa37a469217
265Author: Brad Smith <[email protected]>
266Date: 2026-05-02T16:56:57-04:00
267
268 Make use of __riscv_hwprobe() and getauxval() on Linux/RISCV
269
270 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/289>
271
272diff --git a/meson.build b/meson.build
273index 2275e61..ecdfa27 100644
274--- a/meson.build
275+++ b/meson.build
276@@ -176,6 +176,25 @@ cdata.set('HAVE_SYS_TIME_H', cc.has_header('sys/time.h'))
277 cdata.set('HAVE_UNISTD_H', cc.has_header('unistd.h'))
278 cdata.set('HAVE_VALGRIND_VALGRIND_H', cc.has_header('valgrind/valgrind.h'))
279
280+if cpu_family.startswith('riscv')
281+ linux_riscv_test = '''
282+ #include <sys/auxv.h>
283+ #include <asm/hwcap.h>
284+ #include <asm/hwprobe.h>
285+ #include <asm/unistd.h>
286+ int main() {
287+ struct riscv_hwprobe pair = {
288+ { RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
289+ };
290+ if (__riscv_hwprobe(pair, 1, 0, NULL, 0) < 0)
291+ return 0;
292+ if (pair[0].value & RISCV_HWPROBE_IMA_V) {}
293+ return 0;
294+ }
295+ '''
296+ cdata.set('HAVE_LINUX_RVV', cc.compiles(linux_riscv_test))
297+endif
298+
299 cdata.set_quoted('PACKAGE_VERSION', meson.project_version())
300 cdata.set_quoted('VERSION', meson.project_version())
301
302diff --git a/orc/orcutils-private.h b/orc/orcutils-private.h
303index a91a592..b8de3b5 100644
304--- a/orc/orcutils-private.h
305+++ b/orc/orcutils-private.h
306@@ -30,7 +30,7 @@
307
308 ORC_BEGIN_DECLS
309
310-#if defined(__arm__) || defined(__aarch64__) || defined(__mips__) || defined(__riscv) || defined(__loongarch__)
311+#if defined(__arm__) || defined(__aarch64__) || defined(__mips__) || (defined(__riscv) && !defined(HAVE_LINUX_RVV)) || defined(__loongarch__)
312 char * get_proc_cpuinfo (void);
313 #endif
314
315diff --git a/orc/orcutils.c b/orc/orcutils.c
316index 3b22775..f75c44d 100644
317--- a/orc/orcutils.c
318+++ b/orc/orcutils.c
319@@ -62,7 +62,7 @@ orc_malloc(size_t size)
320 return ret;
321 }
322
323-#if defined(__arm__) || defined(__aarch64__) || defined(__mips__) || defined(__riscv) || defined(__loongarch__)
324+#if defined(__arm__) || defined(__aarch64__) || defined(__mips__) || (defined(__riscv) && !defined(HAVE_LINUX_RVV)) || defined(__loongarch__)
325 char *
326 get_proc_cpuinfo (void)
327 {
328diff --git a/orc/riscv/orcriscvtarget.c b/orc/riscv/orcriscvtarget.c
329index cfbb6b4..8bb095a 100644
330--- a/orc/riscv/orcriscvtarget.c
331+++ b/orc/riscv/orcriscvtarget.c
332@@ -39,11 +39,52 @@
333 #include <orc/riscv/orcriscv-internal.h>
334
335 #include <unistd.h>
336-#include <fcntl.h>
337+
338+#ifdef HAVE_LINUX_RVV
339+#include <sys/auxv.h>
340+#include <asm/hwcap.h>
341+#include <asm/hwprobe.h>
342+#include <asm/unistd.h>
343+#elif defined(__linux__)
344 #include <string.h>
345+#include <fcntl.h>
346 #include <ctype.h>
347+#endif
348
349-#if defined(HAVE_RISCV) && defined(__linux__)
350+#if defined(HAVE_RISCV)
351+#if defined(HAVE_LINUX_RVV)
352+static orc_uint32
353+orc_check_riscv_hwprobe_getauxval (void)
354+{
355+ unsigned long flags = 0;
356+ struct riscv_hwprobe pair = {
357+ { RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
358+ };
359+
360+ if (__riscv_hwprobe(pair, 1, 0, NULL, 0) < 0)
361+ return 0;
362+
363+ if (pair[0].value & RISCV_HWPROBE_IMA_C)
364+ flags |= ORC_TARGET_RISCV_C;
365+ if (getauxval (AT_HWCAP) & COMPAT_HWCAP_ISA_V) {
366+ if (pair[0].value & RISCV_HWPROBE_IMA_V)
367+ flags |= ORC_TARGET_RISCV_V;
368+ }
369+#ifdef RISCV_HWPROBE_EXT_ZVKB
370+ if (pair[0].value & RISCV_HWPROBE_EXT_ZVKB)
371+ flags |= ORC_TARGET_RISCV_ZVKB;
372+#endif
373+#ifdef RISCV_HWPROBE_EXT_ZVBB
374+ if (pair[0].value & RISCV_HWPROBE_EXT_ZVBB)
375+ flags |= ORC_TARGET_RISCV_ZVBB;
376+#endif
377+
378+ /* ORC_TARGET_RISCV_ZVKN */
379+ /* ORC_TARGET_RISCV_ZVKS */
380+
381+ return flags;
382+}
383+#elif defined(__linux__)
384 static int
385 orc_riscv_target_detect_extension (const char *exts, const char *ext)
386 {
387@@ -105,6 +146,7 @@ orc_check_riscv_proc_cpuinfo (void)
388 }
389
390 #endif
391+#endif // HAVE_RISCV
392
393 static orc_uint32
394 orc_riscv_target_get_cpu_flags (void)
395@@ -115,9 +157,13 @@ orc_riscv_target_get_cpu_flags (void)
396 flags |= ORC_TARGET_RISCV_64BIT;
397 #endif
398
399-#if defined(HAVE_RISCV) && defined(__linux__)
400+#if defined(HAVE_RISCV)
401+#if defined(HAVE_LINUX_RVV)
402+ flags |= orc_check_riscv_hwprobe_getauxval ();
403+#elif defined(__linux__)
404 flags |= orc_check_riscv_proc_cpuinfo ();
405 #endif
406+#endif // HAVE_RISCV
407
408 return flags;
409 }
410
411commit 191ec0486e0c9c55a1e47fe1cd3e42b0957d1994
412Author: Brad Smith <[email protected]>
413Date: 2026-05-16T21:41:49-04:00
414
415 Fix building __riscv_hwprobe() path
416
417 Tested with
418 Linux debian 6.18.5+deb14-riscv64 #1 SMP PREEMPT Debian 6.18.5-1 (2026-01-16) riscv64 GNU/Linux
419
420 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/291>
421
422diff --git a/meson.build b/meson.build
423index ecdfa27..a70508b 100644
424--- a/meson.build
425+++ b/meson.build
426@@ -179,11 +179,12 @@ cdata.set('HAVE_VALGRIND_VALGRIND_H', cc.has_header('valgrind/valgrind.h'))
427 if cpu_family.startswith('riscv')
428 linux_riscv_test = '''
429 #include <sys/auxv.h>
430+ #include <sys/hwprobe.h>
431 #include <asm/hwcap.h>
432 #include <asm/hwprobe.h>
433 #include <asm/unistd.h>
434 int main() {
435- struct riscv_hwprobe pair = {
436+ struct riscv_hwprobe pair[] = {
437 { RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
438 };
439 if (__riscv_hwprobe(pair, 1, 0, NULL, 0) < 0)
440diff --git a/orc/riscv/orcriscvtarget.c b/orc/riscv/orcriscvtarget.c
441index 8bb095a..a294937 100644
442--- a/orc/riscv/orcriscvtarget.c
443+++ b/orc/riscv/orcriscvtarget.c
444@@ -42,6 +42,7 @@
445
446 #ifdef HAVE_LINUX_RVV
447 #include <sys/auxv.h>
448+#include <sys/hwprobe.h>
449 #include <asm/hwcap.h>
450 #include <asm/hwprobe.h>
451 #include <asm/unistd.h>
452@@ -57,7 +58,7 @@ static orc_uint32
453 orc_check_riscv_hwprobe_getauxval (void)
454 {
455 unsigned long flags = 0;
456- struct riscv_hwprobe pair = {
457+ struct riscv_hwprobe pair[] = {
458 { RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
459 };
460
461
462commit 423b24a32293ee6b9c8b0fc7056af388e5420c1e
463Author: Brad Smith <[email protected]>
464Date: 2026-05-17T15:16:18-04:00
465
466 riscv: Have Meson print a message when running the hwprobe/getauxval test
467
468 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/292>
469
470diff --git a/meson.build b/meson.build
471index a70508b..5593232 100644
472--- a/meson.build
473+++ b/meson.build
474@@ -193,7 +193,7 @@ if cpu_family.startswith('riscv')
475 return 0;
476 }
477 '''
478- cdata.set('HAVE_LINUX_RVV', cc.compiles(linux_riscv_test))
479+ cdata.set('HAVE_LINUX_RVV', cc.compiles(linux_riscv_test, name: 'Supports hwprobe and getauxval on RISC-V'))
480 endif
481
482 cdata.set_quoted('PACKAGE_VERSION', meson.project_version())
483
484commit 8904da6d607fc6575027928b3db2d718fbe315c5
485Author: Brad Smith <[email protected]>
486Date: 2026-05-17T21:03:52-04:00
487
488 Make use of elf_aux_info() on OpenBSD/FreeBSD RISC-V
489
490 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/296>
491
492diff --git a/orc/riscv/orcriscvtarget.c b/orc/riscv/orcriscvtarget.c
493index a294937..0187fbf 100644
494--- a/orc/riscv/orcriscvtarget.c
495+++ b/orc/riscv/orcriscvtarget.c
496@@ -40,8 +40,11 @@
497
498 #include <unistd.h>
499
500-#ifdef HAVE_LINUX_RVV
501+#if defined(HAVE_LINUX_RVV) || defined(HAVE_ELF_AUX_INFO)
502 #include <sys/auxv.h>
503+#endif
504+
505+#ifdef HAVE_LINUX_RVV
506 #include <sys/hwprobe.h>
507 #include <asm/hwcap.h>
508 #include <asm/hwprobe.h>
509@@ -53,7 +56,35 @@
510 #endif
511
512 #if defined(HAVE_RISCV)
513-#if defined(HAVE_LINUX_RVV)
514+#if defined(HAVE_ELF_AUX_INFO)
515+static orc_uint32
516+orc_check_riscv_elf_aux_info (void)
517+{
518+ unsigned long flags = 0;
519+ unsigned long hwcap = 0;
520+#ifdef HWCAP2_ISA_ZVBB
521+ unsigned long hwcap2 = 0;
522+#endif
523+
524+ elf_aux_info(AT_HWCAP, &hwcap, sizeof(hwcap));
525+#ifdef HWCAP2_ISA_ZVBB
526+ elf_aux_info(AT_HWCAP2, &hwcap2, sizeof(hwcap2));
527+#endif
528+
529+ if (hwcap & HWCAP_ISA_C)
530+ flags |= ORC_TARGET_RISCV_C;
531+#ifdef HWCAP_ISA_V
532+ if (hwcap & HWCAP_ISA_V)
533+ flags |= ORC_TARGET_RISCV_V;
534+#endif
535+#ifdef HWCAP2_ISA_ZVBB
536+ if (hwcap2 & HWCAP2_ISA_ZVBB)
537+ flags |= ORC_TARGET_RISCV_ZVBB;
538+#endif
539+
540+ return flags;
541+}
542+#elif defined(HAVE_LINUX_RVV)
543 static orc_uint32
544 orc_check_riscv_hwprobe_getauxval (void)
545 {
546@@ -159,7 +190,9 @@ orc_riscv_target_get_cpu_flags (void)
547 #endif
548
549 #if defined(HAVE_RISCV)
550-#if defined(HAVE_LINUX_RVV)
551+#if defined(HAVE_ELF_AUX_INFO)
552+ flags |= orc_check_riscv_elf_aux_info ();
553+#elif defined(HAVE_LINUX_RVV)
554 flags |= orc_check_riscv_hwprobe_getauxval ();
555 #elif defined(__linux__)
556 flags |= orc_check_riscv_proc_cpuinfo ();
557
558commit 484cb7b7247ca9b331dd7d38c5f294a391ca8c91
559Author: Felix-Gong <[email protected]>
560Date: 2026-05-28T00:58:02Z
561
562 riscv: Fix missing normalize_result in addF rule
563
564 The addF rule normalizes its inputs via NORMALIZE_SRC_ARG but does not
565 normalize its output. All other float rules (mulF, divF, subF) call
566 orc_riscv_rule_normalize_result after the operation. Without it, the
567 compiled path and the interpreted path diverge on denormal results,
568 causing test_s_2d_addf compiled function test to fail.
569
570 Fixes: #109
571 Signed-off-by: Felix Gong <[email protected]>
572 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/297>
573
574diff --git a/orc/riscv/orcriscvrules.c b/orc/riscv/orcriscvrules.c
575index 260007c..7bd058a 100644
576--- a/orc/riscv/orcriscvrules.c
577+++ b/orc/riscv/orcriscvrules.c
578@@ -1084,6 +1084,7 @@ orc_riscv_rule_addF (OrcCompiler *c, void *user, OrcInstruction *insn)
579 const OrcRiscvRegister dest = ORC_DEST_ARG (c, insn, 0);
580
581 orc_riscv_insn_emit_vfadd_vv (c, dest, src1, src2);
582+ orc_riscv_rule_normalize_result (c, insn);
583 }
584
585 static void
586
587commit 3c1d4f71c50c133ef76ecd9ff42b228b21e295eb
588Author: Felix-Gong <[email protected]>
589Date: 2026-05-30T08:39:23Z
590
591 riscv: Fix missing normalize_result in subF rule
592
593 The subF rule was missing the normalize_result call after vfsub_vv,
594 same bug pattern as addF. Subtraction of two close normal floats can
595 produce a denormalized result that needs flushing to match the
596 emulator's behavior.
597
598 Verified on SpacemiT C920: direct test shows JIT produces denormal
599 (0x800037c0) while emulator produces -0.0 (0x80000000) without this
600 fix. The existing test suite doesn't trigger this because random
601 float data rarely produces the exact subtraction case, but the bug
602 is real and can be hit by real workloads.
603
604 Signed-off-by: Felix-Gong <[email protected]>
605 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/298>
606
607diff --git a/orc/riscv/orcriscvrules.c b/orc/riscv/orcriscvrules.c
608index 7bd058a..1312b8e 100644
609--- a/orc/riscv/orcriscvrules.c
610+++ b/orc/riscv/orcriscvrules.c
611@@ -1095,6 +1095,7 @@ orc_riscv_rule_subF (OrcCompiler *c, void *user, OrcInstruction *insn)
612 const OrcRiscvRegister dest = ORC_DEST_ARG (c, insn, 0);
613
614 orc_riscv_insn_emit_vfsub_vv (c, dest, src1, src2);
615+ orc_riscv_rule_normalize_result (c, insn);
616 }
617
618 static void
619
620commit b3d50db78e4e98d38a07e028cbf4f8e82872dc3b
621Author: Felix-Gong <[email protected]>
622Date: 2026-06-06T01:13:55Z
623
624 riscv: Rename orc_riscv_insn_emit_vxfncvt_vv to vxfwcvt_vv
625
626 Rename the emit function to better reflect the RISC-V instruction it
627 encodes (vfwcvt.f.x.v - widening float convert). The previous name
628 vxfncvt was confusing and did not match the standard RVV naming
629 convention.
630
631 Signed-off-by: Felix-Gong <[email protected]>
632 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/299>
633
634diff --git a/orc/riscv/orcriscvinsn.c b/orc/riscv/orcriscvinsn.c
635index 85be0a5..d6663a0 100644
636--- a/orc/riscv/orcriscvinsn.c
637+++ b/orc/riscv/orcriscvinsn.c
638@@ -1427,7 +1427,7 @@ orc_riscv_insn_emit_vffncvt_vv (OrcCompiler *c,
639 }
640
641 void
642-orc_riscv_insn_emit_vxfncvt_vv (OrcCompiler *c,
643+orc_riscv_insn_emit_vxfwcvt_vv (OrcCompiler *c,
644 OrcRiscvRegister vd, OrcRiscvRegister vs2)
645 {
646 ORC_ASSERT (vs2 != vd);
647diff --git a/orc/riscv/orcriscvinsn.h b/orc/riscv/orcriscvinsn.h
648index 143d991..8cb6357 100644
649--- a/orc/riscv/orcriscvinsn.h
650+++ b/orc/riscv/orcriscvinsn.h
651@@ -183,7 +183,7 @@ ORC_API void orc_riscv_insn_emit_vfcvt_rtz_vv (OrcCompiler *c, OrcRiscvRegister
652 ORC_API void orc_riscv_insn_emit_vfxcvt_vv (OrcCompiler *c, OrcRiscvRegister vd, OrcRiscvRegister vs2);
653 ORC_API void orc_riscv_insn_emit_vfxncvt_vv (OrcCompiler *c, OrcRiscvRegister vd, OrcRiscvRegister vs2);
654 ORC_API void orc_riscv_insn_emit_vffncvt_vv (OrcCompiler *c, OrcRiscvRegister vd, OrcRiscvRegister vs2);
655-ORC_API void orc_riscv_insn_emit_vxfncvt_vv (OrcCompiler *c, OrcRiscvRegister vd, OrcRiscvRegister vs2);
656+ORC_API void orc_riscv_insn_emit_vxfwcvt_vv (OrcCompiler *c, OrcRiscvRegister vd, OrcRiscvRegister vs2);
657 ORC_API void orc_riscv_insn_emit_vffwcvt_vv (OrcCompiler *c, OrcRiscvRegister vd, OrcRiscvRegister vs2);
658 ORC_API void orc_riscv_insn_emit_vredsum_vv (OrcCompiler *c, OrcRiscvRegister vd, OrcRiscvRegister vs1, OrcRiscvRegister vs2);
659 ORC_API void orc_riscv_insn_emit_vmv_xs (OrcCompiler *c, OrcRiscvRegister rd, OrcRiscvRegister vs2);
660diff --git a/orc/riscv/orcriscvrules.c b/orc/riscv/orcriscvrules.c
661index 1312b8e..ee35a62 100644
662--- a/orc/riscv/orcriscvrules.c
663+++ b/orc/riscv/orcriscvrules.c
664@@ -1055,7 +1055,7 @@ orc_riscv_rule_convld (OrcCompiler *c, void *user, OrcInstruction *insn)
665 const OrcRiscvRegister src = ORC_SRC_ARG (c, insn, 0);
666 const OrcRiscvRegister dest = ORC_DEST_ARG (c, insn, 0);
667
668- orc_riscv_insn_emit_vxfncvt_vv (c, dest, src);
669+ orc_riscv_insn_emit_vxfwcvt_vv (c, dest, src);
670 }
671
672 static void
673
674commit b6f513dec9818b69c04a7c013f8c7274dba4084a
675Author: Felix-Gong <[email protected]>
676Date: 2026-06-05T02:37:17Z
677
678 riscv: Add convwf rule for RVV backend
679
680 Add the convwf (convert word to float) rule to the ORC RISC-V Vector
681 backend. This opcode converts int16 values to float32 using the
682 vfwcvt.f.x.v widening instruction with SEW=16.
683
684 Signed-off-by: Felix-Gong <[email protected]>
685 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/299>
686
687diff --git a/orc/riscv/orcriscvrules.c b/orc/riscv/orcriscvrules.c
688index ee35a62..8bd9f20 100644
689--- a/orc/riscv/orcriscvrules.c
690+++ b/orc/riscv/orcriscvrules.c
691@@ -1076,6 +1076,16 @@ orc_riscv_rule_convfl (OrcCompiler *c, void *user, OrcInstruction *insn)
692 orc_riscv_insn_emit_vfcvt_rtz_vv (c, dest, src);
693 }
694
695+
696+static void
697+orc_riscv_rule_convwf (OrcCompiler *c, void *user, OrcInstruction *insn)
698+{
699+ const OrcRiscvRegister src = ORC_SRC_ARG (c, insn, 0);
700+ const OrcRiscvRegister dest = ORC_DEST_ARG (c, insn, 0);
701+
702+ orc_riscv_insn_emit_vxfwcvt_vv (c, dest, src);
703+}
704+
705 static void
706 orc_riscv_rule_addF (OrcCompiler *c, void *user, OrcInstruction *insn)
707 {
708@@ -1447,6 +1457,7 @@ orc_riscv_rules_init (OrcTarget *target)
709 REG (convld, convld, 32, FALSE, 0, 0);
710 REG (convfd, convfd, 32, TRUE, 1, 0);
711 REG (convfl, convfl, 32, FALSE, 0, 0);
712+ REG (convwf, convwf, 16, FALSE, 0, 0);
713
714 REG (addf, addF, 32, TRUE, 0, 2);
715 REG (addd, addF, 64, TRUE, 0, 2);
716
717commit 6f489c05a255a7c220b9c19ed32cf2fdb3ab4e3e
718Author: Felix-Gong <[email protected]>
719Date: 2026-06-13T06:09:37Z
720
721 riscv: Add getauxval fallback for CPU feature detection
722
723 Add getauxval(AT_HWCAP) as a fallback detection path for RISC-V
724 systems that don't have hwprobe or elf_aux_info (e.g., Alpine Linux
725 with musl libc). This enables ORC to detect V extension support on
726 a wider range of systems.
727
728 Detection priority:
729 elf_aux_info (BSD) > hwprobe+getauxval (Linux) > getauxval > /proc/cpuinfo
730
731 Signed-off-by: Felix-Gong <[email protected]>
732 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/303>
733
734diff --git a/orc/riscv/orcriscvtarget.c b/orc/riscv/orcriscvtarget.c
735index 0187fbf..36226d5 100644
736--- a/orc/riscv/orcriscvtarget.c
737+++ b/orc/riscv/orcriscvtarget.c
738@@ -40,7 +40,7 @@
739
740 #include <unistd.h>
741
742-#if defined(HAVE_LINUX_RVV) || defined(HAVE_ELF_AUX_INFO)
743+#if defined(HAVE_LINUX_RVV) || defined(HAVE_ELF_AUX_INFO) || defined(HAVE_GETAUXVAL)
744 #include <sys/auxv.h>
745 #endif
746
747@@ -49,13 +49,44 @@
748 #include <asm/hwcap.h>
749 #include <asm/hwprobe.h>
750 #include <asm/unistd.h>
751-#elif defined(__linux__)
752+#elif defined(HAVE_GETAUXVAL) && defined(__riscv)
753+#include <asm/hwcap.h>
754+#endif
755+
756+#if defined(HAVE_LINUX_RVV) || defined(HAVE_GETAUXVAL) || defined(__linux__)
757 #include <string.h>
758 #include <fcntl.h>
759 #include <ctype.h>
760 #endif
761
762 #if defined(HAVE_RISCV)
763+
764+#if defined(HAVE_LINUX_RVV) || defined(HAVE_GETAUXVAL) || defined(__linux__)
765+static int
766+orc_riscv_target_detect_extension (const char *exts, const char *ext)
767+{
768+ while (isspace (*exts))
769+ exts++;
770+
771+ ORC_ASSERT (strncmp (exts, "rv", 2) == 0);
772+
773+ const int n = strlen (ext);
774+ char *sep = strchr (exts, '_');
775+
776+ if (n == 1) {
777+ char *found = strstr (exts + 2, ext);
778+ return found && (found < sep || sep == NULL);
779+ }
780+
781+ for (; sep; sep = strchr (sep + 1, '_')) {
782+ if (strncmp (sep + 1, ext, n) && !isalnum (exts[n]))
783+ return TRUE;
784+ }
785+
786+ return FALSE;
787+}
788+#endif
789+
790 #if defined(HAVE_ELF_AUX_INFO)
791 static orc_uint32
792 orc_check_riscv_elf_aux_info (void)
793@@ -116,31 +147,38 @@ orc_check_riscv_hwprobe_getauxval (void)
794
795 return flags;
796 }
797-#elif defined(__linux__)
798-static int
799-orc_riscv_target_detect_extension (const char *exts, const char *ext)
800+#elif defined(HAVE_GETAUXVAL)
801+static orc_uint32
802+orc_check_riscv_getauxval (void)
803 {
804- while (isspace (*exts))
805- exts++;
806-
807- ORC_ASSERT (strncmp (exts, "rv", 2) == 0);
808-
809- const int n = strlen (ext);
810- char *sep = strchr (exts, '_');
811+ orc_uint32 flags = 0;
812+ unsigned long hwcap = getauxval (AT_HWCAP);
813
814- if (n == 1) {
815- char *found = strstr (exts + 2, ext);
816- return found && (found < sep || sep == NULL);
817- }
818+ if (hwcap & COMPAT_HWCAP_ISA_V)
819+ flags |= ORC_TARGET_RISCV_V;
820
821- for (; sep; sep = strchr (sep + 1, '_')) {
822- if (strncmp (sep + 1, ext, n) && !isalnum (exts[n]))
823- return TRUE;
824+ /* Other extensions (ZVKB, ZVBB, ZVKN, ZVKS) have no hwcap bits,
825+ * fall back to parsing /proc/cpuinfo */
826+ char *cpuinfo = get_proc_cpuinfo ();
827+ if (cpuinfo) {
828+ char *cpuinfo_line = get_tag_value (cpuinfo, "isa");
829+ if (cpuinfo_line) {
830+ if (orc_riscv_target_detect_extension (cpuinfo_line, "zvkb"))
831+ flags |= ORC_TARGET_RISCV_ZVKB;
832+ if (orc_riscv_target_detect_extension (cpuinfo_line, "zvbb"))
833+ flags |= ORC_TARGET_RISCV_ZVBB;
834+ if (orc_riscv_target_detect_extension (cpuinfo_line, "zvkn"))
835+ flags |= ORC_TARGET_RISCV_ZVKN;
836+ if (orc_riscv_target_detect_extension (cpuinfo_line, "zvks"))
837+ flags |= ORC_TARGET_RISCV_ZVKS;
838+ free (cpuinfo_line);
839+ }
840+ free (cpuinfo);
841 }
842
843- return FALSE;
844+ return flags;
845 }
846-
847+#elif defined(__linux__)
848 static orc_uint32
849 orc_check_riscv_proc_cpuinfo (void)
850 {
851@@ -194,6 +232,8 @@ orc_riscv_target_get_cpu_flags (void)
852 flags |= orc_check_riscv_elf_aux_info ();
853 #elif defined(HAVE_LINUX_RVV)
854 flags |= orc_check_riscv_hwprobe_getauxval ();
855+#elif defined(HAVE_GETAUXVAL)
856+ flags |= orc_check_riscv_getauxval ();
857 #elif defined(__linux__)
858 flags |= orc_check_riscv_proc_cpuinfo ();
859 #endif
860
861commit 4d75d902ac8abb856bcd1864d8d57418b44afd9c
862Author: Brad Smith <[email protected]>
863Date: 2026-06-15T13:30:49-04:00
864
865 riscv: Cleaning up for getauxval addition
866
867 - Remove HAVE_LINUX_RVV in two spots as orc_riscv_target_detect_extension()
868 is only used if not using the hwprobe interface
869 - Although it does nothing at the moment add ORC_TARGET_RISCV_C handling
870 just so all of the handlers are the same
871
872 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/304>
873
874diff --git a/orc/riscv/orcriscvtarget.c b/orc/riscv/orcriscvtarget.c
875index 36226d5..e02c278 100644
876--- a/orc/riscv/orcriscvtarget.c
877+++ b/orc/riscv/orcriscvtarget.c
878@@ -53,7 +53,7 @@
879 #include <asm/hwcap.h>
880 #endif
881
882-#if defined(HAVE_LINUX_RVV) || defined(HAVE_GETAUXVAL) || defined(__linux__)
883+#if defined(HAVE_GETAUXVAL) || defined(__linux__)
884 #include <string.h>
885 #include <fcntl.h>
886 #include <ctype.h>
887@@ -61,7 +61,7 @@
888
889 #if defined(HAVE_RISCV)
890
891-#if defined(HAVE_LINUX_RVV) || defined(HAVE_GETAUXVAL) || defined(__linux__)
892+#if defined(HAVE_GETAUXVAL) || defined(__linux__)
893 static int
894 orc_riscv_target_detect_extension (const char *exts, const char *ext)
895 {
896@@ -154,6 +154,8 @@ orc_check_riscv_getauxval (void)
897 orc_uint32 flags = 0;
898 unsigned long hwcap = getauxval (AT_HWCAP);
899
900+ if (hwcap & COMPAT_HWCAP_ISA_C)
901+ flags |= ORC_TARGET_RISCV_C;
902 if (hwcap & COMPAT_HWCAP_ISA_V)
903 flags |= ORC_TARGET_RISCV_V;
904
905
906commit 2a119bafa9c3df05d522c643ea4e7c2ea47bf0f7
907Author: Felix-Gong <[email protected]>
908Date: 2026-06-25T03:33:56Z
909
910 riscv: Fix convsusN vsetvli to preserve VL
911
912 The convsusN rule's vsetvli calls used rs1=x0 which resets VL to
913 VLMAX. The loop's initial vsetvli sets VL based on remaining
914 elements, but convsusN's vsetvli overwrites it with VLMAX, causing
915 stores to write beyond the intended range and corrupting adjacent
916 memory.
917
918 Use rs1=VECTOR_LENGTH instead of rs1=x0 to preserve VL.
919
920 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/306>
921
922diff --git a/orc/riscv/orcriscvrules.c b/orc/riscv/orcriscvrules.c
923index 8bd9f20..6eb890d 100644
924--- a/orc/riscv/orcriscvrules.c
925+++ b/orc/riscv/orcriscvrules.c
926@@ -956,11 +956,11 @@ orc_riscv_rule_convsusN (OrcCompiler *c, void *user, OrcInstruction *insn)
927 const OrcRiscvRegister dest = ORC_DEST_ARG (c, insn, 0);
928
929 orc_riscv_insn_emit_vmax_vx (c, dest, ORC_RISCV_ZERO, src);
930- orc_riscv_insn_emit_vsetvli (c, ORC_RISCV_ZERO, ORC_RISCV_ZERO,
931+ orc_riscv_insn_emit_vsetvli (c, ORC_RISCV_ZERO, ORC_RISCV_VECTOR_LENGTH,
932 orc_riscv_compiler_compute_vtype (c, info->element_width - 1, 0));
933
934 orc_riscv_insn_emit_vnclipu_vi (c, dest, dest, 0);
935- orc_riscv_insn_emit_vsetvli (c, ORC_RISCV_ZERO, ORC_RISCV_ZERO,
936+ orc_riscv_insn_emit_vsetvli (c, ORC_RISCV_ZERO, ORC_RISCV_VECTOR_LENGTH,
937 orc_riscv_compiler_compute_vtype (c, info->element_width, 0));
938 }
939
940
941commit e0b6be3330113c47bf8f3734ed36d5bb5bd7b46c
942Author: Felix-Gong <[email protected]>
943Date: 2026-07-11T03:47:39Z
944
945 riscv: Fix convdl narrowing to use truncation (vfncvt.rtz.x.f.w) instead of dynamic rounding
946
947 ORC uses emit_vfxncvt_vv for the convdl (double-to-long narrowing
948 conversion) opcode, which requires truncating (round-towards-zero)
949 semantics to match the C (int) cast used in the emulation path.
950
951 The emitter used vs1=0b10001 encoding vfncvt.x.f.w (dynamic rounding
952 mode, dependent on the frm CSR), but the RISC-V V spec requires
953 vs1=0b10111 for vfncvt.rtz.x.f.w (fixed truncation, round-towards-zero).
954
955 This caused all 17 convdl float-to-integer narrowing conversions to
956 produce wrong results on RISC-V vector hardware, as the rounding
957 mode was undefined (dependent on the frm CSR value at runtime)
958 instead of truncating.
959
960 Verified on SOPHGO SG2044 (RISC-V RVV 1.0): all 13 ORC tests pass,
961 including exec_opcodes_sys which exercises convdl at runtime.
962
963 Signed-off-by: Xiaofei Gong <[email protected]>
964 Signed-off-by: YuanSheng <[email protected]>
965 Part-of: <https://gitlab.freedesktop.org/gstreamer/orc/-/merge_requests/308>
966
967diff --git a/orc/riscv/orcriscvinsn.c b/orc/riscv/orcriscvinsn.c
968index d6663a0..db969ae 100644
969--- a/orc/riscv/orcriscvinsn.c
970+++ b/orc/riscv/orcriscvinsn.c
971@@ -1414,8 +1414,8 @@ void
972 orc_riscv_insn_emit_vfxncvt_vv (OrcCompiler *c,
973 OrcRiscvRegister vd, OrcRiscvRegister vs2)
974 {
975- ORC_ASM_CODE (c, " vfncvt.x.f.w %s, %s\n", NAME (vd), NAME (vs2));
976- orc_riscv_insn_vop (c, 0b010010, 1, VREG (vs2), 0b10001, OPFVV, VREG (vd));
977+ ORC_ASM_CODE (c, " vfncvt.rtz.x.f.w %s, %s\n", NAME (vd), NAME (vs2));
978+ orc_riscv_insn_vop (c, 0b010010, 1, VREG (vs2), 0b10111, OPFVV, VREG (vd));
979 }
980
981 void