projects/guix·blob python-team · refs

325 lines · 12.4 KiB

1;;; GNU Guix --- Functional package management for GNU
2;;; Copyright © 2026 Cayetano Santos <[email protected]>
3;;;
4;;; This file is part of GNU Guix.
5;;;
6;;; GNU Guix is free software; you can redistribute it and/or modify it
7;;; under the terms of the GNU General Public License as published by
8;;; the Free Software Foundation; either version 3 of the License, or (at
9;;; your option) any later version.
10;;;
11;;; GNU Guix is distributed in the hope that it will be useful, but
12;;; WITHOUT ANY WARRANTY; without even the implied warranty of
13;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14;;; GNU General Public License for more details.
15;;;
16;;; You should have received a copy of the GNU General Public License
17;;; along with GNU Guix. If not, see <http://www.gnu.org/licenses/>.
18
19(define-module (gnu packages hdl)
20 #:use-module ((guix licenses) #:prefix license:)
21 #:use-module (guix build-system copy)
22 #:use-module (guix gexp)
23 #:use-module (guix git-download)
24 #:use-module (guix packages)
25 #:use-module (gnu packages electronics)
26 #:use-module (gnu packages python)
27 #:use-module (gnu packages python-science)
28 #:use-module (gnu packages python-xyz))
29
30(define-public colibri
31 (package
32 (name "colibri")
33 (version "2026.07")
34 (source
35 (origin
36 (method git-fetch)
37 (uri (git-reference
38 (url "https://gitlab.com/colibri-cern/colibri")
39 (commit version)
40 ;; UVVM, not in Guix.
41 (recursive? #t)))
42 (file-name (git-file-name name version))
43 (sha256
44 (base32
45 "0vh4ynm0gfw3274xbj5yhkz0lgqwwh99fndjyb5ddc1l12639spn"))))
46 (outputs
47 '("out" "colibri"))
48 (properties
49 `((output-synopsis "out" "Instance this design library as work")
50 (output-synopsis "colibri" "Instance this design library as colibri")))
51 (build-system copy-build-system)
52 (arguments
53 (list
54 #:phases
55 #~(modify-phases %standard-phases
56 (add-after 'install 'runpy
57 (lambda* (#:key tests? #:allow-other-keys)
58 (when tests?
59 ;; This test gives "pass 14 of 30; fail 16 of 30"
60 (delete-file "sim/fileio/run.py")
61 (delete-file "sim/misc/run.py") ;requires peakrdl
62 (for-each
63 (lambda (file)
64 (substitute* file
65 ;; This is required to comply with current VUnit, see:
66 ;; https://github.com/VUnit/vunit/issues/777
67 (("compile_builtins=False") ""))
68 (invoke "python3" file "-v"
69 "-p" (number->string (parallel-job-count))))
70 (find-files "sim" "\\.py$"))))))
71 #:install-plan
72 #~'(;; Library work.
73 ("vhdl_ls.toml" "share/colibri/work/vhdl_ls.toml")
74 ("src" "share/colibri/work/src"
75 #:include ("vhdl" "md"))
76 ("sim" "share/colibri/work/sim"
77 #:include ("vhdl" "py"))
78 ;; Library colibri.
79 ("vhdl_ls.toml" "share/colibri/colibri/vhdl_ls.toml")
80 ("src" "share/colibri/colibri/src"
81 #:include ("vhdl" "md") #:output "colibri")
82 ("sim" "share/colibri/colibri/sim"
83 #:include ("vhdl" "py") #:output "colibri"))))
84 (native-inputs
85 (list nvc python-minimal python-vunit))
86 (native-search-paths
87 (list (search-path-specification
88 (variable "FW_COLIBRI")
89 (separator #f)
90 (files (list "share/colibri")))))
91 (home-page "https://gitlab.com/colibri-cern/colibri")
92 (synopsis "Vendor independent VHDL common library")
93 (description "This library is a collection of common VHDL components,
94functions, and procedures used in CERN gateware projects, including:
95
96@itemize
97 @item common - Common Functions
98 @item comms - Utilities for Communications (PRBS, CRC, ...)
99 @item endec - Encoders and Decoders (RLE, 8b10b, ...)
100 @item fileio - File Operations
101 @item interfaces - Bus and Stream Protocols Components (AXI, Avalon, ...)
102 @item io - Input Output protocols (UART, I2C, SPI, ...)
103 @item memory - Memory Entities (FIFOs, RAMs)
104 @item misc - Miscellaneous
105 @item pipes - Pipes entities (Arbiter, Router, ...)
106 @item packet - Manipulation of Packeted streams
107 @item proto - Protocols (Aurora 64b66b, ...)
108@end itemize
109
110It is written following the VHDL 2008 standard.")
111 (license (list license:asl2.0
112 license:ohl2-w
113 license:cc-by-sa4.0))))
114
115(define-public ieee-p1076
116 (package
117 (name "ieee-p1076")
118 (version "2019")
119 (source
120 (origin
121 (method git-fetch)
122 (uri (git-reference
123 (url "https://opensource.ieee.org/vasg/Packages/")
124 (commit (string-append "1076-" version))))
125 (file-name (git-file-name name version))
126 (sha256
127 (base32 "1va626i5ww2ziw3dghw0d2mq7mrj5dwcn0h019h77866yw2pq9xn"))))
128 (build-system copy-build-system)
129 (native-inputs (list python-minimal-wrapper nvc python-vunit))
130 (arguments
131 (list
132 ;; Not all 2019 features are supported by nvc compiler.
133 ;; pass 1055 of 1648
134 #:tests? #f
135 #:install-plan
136 #~'(("ieee" "share/ieee-p1076/ieee" #:include ("vhdl"))
137 ("std" "share/ieee-p1076/std" #:include ("vhdl")))))
138 (native-search-paths
139 (list (search-path-specification
140 (variable "FW_IEEE_p1076")
141 (separator #f)
142 (files (list "share/ieee-p1076")))))
143 (home-page "https://IEEE-P1076.gitlab.io")
144 (synopsis "VHDL libraries corresponding to the IEEE 1076 standard")
145 (description
146 "Open source materials intended for reference by the IEEE standard 1076,
147as approved and published by the @acronym{VHDL, Very High Speed Hardware
148Description Language} Analysis and Standardization Group.")
149 (license license:asl2.0)))
150
151(define-public json-for-vhdl
152 ;; No tagged releases.
153 (let ((commit "2ab1ebc2c788ececce152a49ffda706f84570e95")
154 (revision "1"))
155 (package
156 (name "json-for-vhdl")
157 (version (git-version "20260713" revision commit)) ;last revision
158 (source
159 (origin
160 (method git-fetch)
161 (uri (git-reference
162 (url "https://github.com/Paebbels/JSON-for-VHDL/")
163 (commit commit)))
164 (file-name (git-file-name name version))
165 (sha256
166 (base32 "1gkj9hc92w7ibz3w3n6aa4hijril5r77vba299xl81nlzjdlb4mx"))))
167 (build-system copy-build-system)
168 (arguments
169 (list
170 #:install-plan
171 #~'(("src" "share/json-for-vhdl/work/src"
172 #:include ("vhdl")))
173 #:phases
174 #~(modify-phases %standard-phases
175 ;; The examples/Encodings_VUnit test requires vhdl builtins.
176 (add-after 'unpack 'fix-check
177 (lambda _
178 (substitute* "tests/VUnit/run.py"
179 (("from_argv\\(\\)")
180 "from_argv()\nvu.add_vhdl_builtins()")))))))
181 (native-search-paths
182 (list (search-path-specification
183 (variable "FW_JSON_VHDL")
184 (separator #f)
185 (files (list "share/json-for-vhdl")))))
186 (home-page "https://github.com/Paebbels/JSON-for-VHDL/")
187 (synopsis "Parse and query JSON data structures in VHDL")
188 (description
189 "The JSON-for-VHDL library provides a parser to query JSON data
190structures from external files on disk. It provides a context to be
191used in the declarative section of design units.")
192 (license license:asl2.0))))
193
194(define-public neorv32
195 (package
196 (name "neorv32")
197 (version "1.12.7")
198 (source
199 (origin
200 (method git-fetch)
201 (uri (git-reference
202 (url "https://github.com/stnolting/neorv32")
203 (commit (string-append "v" version))))
204 (file-name (git-file-name name version))
205 (sha256
206 (base32
207 "030djnf5ww4b2w6lhb9lpprq2iawf8v93rmmgfgnbr56k4blyyk6"))))
208 (outputs
209 '("out" "neorv32"))
210 (build-system copy-build-system)
211 (arguments
212 (list
213 #:tests? #f ;FIXME: nvc checksum errors inside the build env
214 #:phases
215 #~(modify-phases %standard-phases
216 (add-after 'install 'check
217 (lambda* (#:key tests? #:allow-other-keys)
218 (when tests?
219 (substitute* '("rtl/file_list_cpu.f" "rtl/file_list_soc.f")
220 (("NEORV32_RTL_PATH_PLACEHOLDER") "rtl"))
221 (for-each
222 (lambda (f)
223 (invoke
224 "sh" "-c"
225 (format #f "cat rtl/~a.f | xargs nvc --work=neorv32 -a" f)))
226 '("file_list_soc" "file_list_cpu"))
227 (for-each
228 (lambda (f)
229 (invoke "nvc" "--work=neorv32" "-a" f))
230 `("sim/sim_uart_rx.vhd"
231 ,@(find-files "sim" "x.*\\.vhd$")
232 "sim/neorv32_tb.vhd"))
233 (invoke "nvc" "--work=neorv32" "-e" "neorv32_tb")
234 (invoke "nvc" "--work=neorv32" "-r" "--stop-time=10ms"
235 "neorv32_tb")))))
236 #:install-plan
237 #~'(("rtl" "share/neorv32/work/rtl"
238 #:exclude-regexp (".*\\.f$" ".*\\.sh$"))
239 ("rtl" "share/neorv32/neorv32/rtl"
240 #:exclude-regexp (".*\\.f$" ".*\\.sh$")
241 #:output "neorv32"))))
242 (native-inputs (list nvc))
243 (native-search-paths
244 (list (search-path-specification
245 (variable "FW_NEORV32")
246 (separator #f)
247 (files (list "share/neorv32")))))
248 (home-page "https://stnolting.github.io/neorv32/")
249 (synopsis "RISC-V soft core CPU in VHDL")
250 (description
251 "Neorv32 is a small, customizable 32 bits microcontroller-like system on
252chip written in platform-independent VHDL.")
253 (properties
254 `((output-synopsis "out" "Instance this design library as work")
255 (output-synopsis "neorv32" "Instance this design library as neorv32")))
256 (license license:bsd-3)))
257
258(define-public open-logic
259 (package
260 (name "open-logic")
261 (version "4.7.0")
262 (source
263 (origin
264 (method git-fetch)
265 (uri (git-reference
266 (url "https://github.com/open-logic/open-logic/")
267 (commit version)
268 ;; Required by the en_cl_fix submodule.
269 (recursive? #t)))
270 (file-name (git-file-name name version))
271 (sha256
272 (base32
273 "1q8f09yqjpa2638zns7pgjpzdj8ddjd2fvqvsclwpks022q2y79l"))))
274 (outputs
275 '("out" "olo"))
276 (properties
277 `((output-synopsis "out" "Instance this design library as work")
278 (output-synopsis "olo" "Instance this design library as olo")))
279 (build-system copy-build-system)
280 (arguments
281 (list
282 #:phases
283 #~(modify-phases %standard-phases
284 (add-after 'install 'check
285 (lambda* (#:key tests? inputs #:allow-other-keys)
286 (when tests?
287 (setenv "HOME" "/tmp")
288 (with-directory-excursion "3rdParty/en_cl_fix/sim"
289 (invoke "python3" "run.py" "--simulator" "nvc"
290 "-p" (number->string (parallel-job-count))
291 "--simulator-path"
292 (dirname (search-input-file inputs "bin/nvc"))))
293 (with-directory-excursion "sim"
294 (invoke "python3" "run.py" "--nvc" "-v"
295 "-p" (number->string (parallel-job-count))))))))
296 #:install-plan
297 #~'(;; Library work.
298 ("src" "share/open-logic/work/src"
299 #:include ("vhd"))
300 ("3rdParty" "share/open-logic/work/3rdParty"
301 #:include ("vhd"))
302 ;; Library olo.
303 ("src" "share/open-logic/olo/src"
304 #:include ("vhd") #:output "olo")
305 ("3rdParty" "share/open-logic/olo/3rdParty"
306 #:include ("vhd") #:output "olo"))))
307 (native-inputs
308 (list nvc
309 python-jinja2
310 python-matplotlib
311 python-minimal
312 python-scipy
313 python-vunit))
314 (native-search-paths
315 (list (search-path-specification
316 (variable "FW_OPEN_LOGIC")
317 (separator #f)
318 (files (list "share/open-logic")))))
319 (home-page "https://github.com/open-logic/open-logic/")
320 (synopsis "Open library of VHDL standard components")
321 (description "Open Logic implements commonly used design units in a
322reusable and vendor/tool-independent way. It is written following the VHDL
3232008 standard, but can also be used from System Verilog.")
324 (license (list license:lgpl2.1
325 license:expat)))) ;en_cl_fix uses Expat license