| 1 | https://pagure.io/libaio/pull-request/23
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| 2 |
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| 3 | From f68c69b6cbc1260a6034997d5f146e3d0a197ed8 Mon Sep 17 00:00:00 2001
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| 4 | From: Xiongchuan Tan <[email protected]>
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| 5 | Date: Jun 28 2022 15:53:38 +0000
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| 6 | Subject: As of June 28th, 2022, the RISC-V spec[1] reserves the PTE permission bit
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| 7 |
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| 8 | combination of "write+!read", and the kernel would have incoherent behavior in
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| 9 | the last test case of "harness/cases/5.t". Since it leads to undefined behavior,
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| 10 | until further spec update, this test case should be disabled for RISC-V.
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| 11 |
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| 12 | A patch to disallow such permission in mmap() can be found here[2].
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| 13 |
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| 14 | [1]: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
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| 15 | [2]: https://www.spinics.net/lists/kernel/msg4412421.html
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| 16 |
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| 17 | ---
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| 18 |
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| 19 | diff --git a/harness/cases/5.t b/harness/cases/5.t
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| 20 | index b0a7c56..8d6c959 100644
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| 21 | |
| 22 | |
| 23 | @@ -37,6 +37,14 @@ int test_main(void)
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| 24 | status |= attempt_rw(rwfd, buf, SIZE, 0, READ, -EFAULT);
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| 25 |
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| 26 | res = munmap(buf, page_size); assert(res == 0);
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| 27 | +
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| 28 | + /* As of June 28th, 2022, the RISC-V spec Volume 2 Section 4.3
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| 29 | + * version "20211203 Privileged Architecture v1.12, Ratified"
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| 30 | + * reserves the usage of the PTE permission bit combination of
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| 31 | + * "write+!read", so the next test leads to undefined behavior
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| 32 | + * and should be disabled. */
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| 33 | +#ifndef __riscv
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| 34 | +
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| 35 | buf = mmap(0, page_size, PROT_WRITE, MAP_SHARED, rwfd, 0);
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| 36 | assert(buf != (char *)-1);
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| 37 |
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| 38 | @@ -48,6 +56,8 @@ int test_main(void)
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| 39 | status |= attempt_rw(rwfd, buf, SIZE, 0, READ, SIZE);
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| 40 | status |= attempt_rw(rwfd, buf, SIZE, 0, WRITE, res);
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| 41 |
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| 42 | +#endif
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| 43 | +
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| 44 | return status;
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| 45 | }
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| 46 |
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| 47 |
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