| 1 | |
| 2 | %YAML 1.2
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| 3 | ---
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| 4 | $id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml#
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| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml#
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| 6 |
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| 7 | title: Marvell ODMI controller
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| 8 |
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| 9 | maintainers:
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| 10 | - Thomas Petazzoni <[email protected]>
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| 11 |
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| 12 | description:
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| 13 | Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can
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| 14 | be used by on-board peripherals for MSI interrupts.
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| 15 |
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| 16 | properties:
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| 17 | compatible:
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| 18 | const: marvell,odmi-controller
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| 19 |
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| 20 | reg:
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| 21 | description: List of register definitions, one for each ODMI frame.
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| 22 |
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| 23 | msi-controller: true
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| 24 |
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| 25 | marvell,odmi-frames:
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| 26 | description: Number of ODMI frames available. Each frame provides a number of events.
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| 27 | $ref: /schemas/types.yaml#/definitions/uint32
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| 28 |
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| 29 | marvell,spi-base:
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| 30 | description: >
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| 31 | List of GIC base SPI interrupts, one for each ODMI frame. Those SPI
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| 32 | interrupts are 0-based, i.e. marvell,spi-base = <128> will use SPI #96.
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| 33 | See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
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| 34 | for details.
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| 35 | $ref: /schemas/types.yaml#/definitions/uint32-array
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| 36 |
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| 37 | required:
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| 38 | - compatible
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| 39 | - reg
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| 40 | - msi-controller
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| 41 | - marvell,odmi-frames
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| 42 | - marvell,spi-base
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| 43 |
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| 44 | additionalProperties: false
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| 45 |
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| 46 | examples:
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| 47 | - |
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| 48 | msi-controller@300000 {
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| 49 | compatible = "marvell,odmi-controller";
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| 50 | msi-controller;
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| 51 | marvell,odmi-frames = <4>;
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| 52 | reg = <0x300000 0x4000>, <0x304000 0x4000>, <0x308000 0x4000>, <0x30C000 0x4000>;
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| 53 | marvell,spi-base = <128>, <136>, <144>, <152>;
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| 54 | };
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