| 1 | |
| 2 | %YAML 1.2
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| 3 | ---
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| 4 | $id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
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| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml#
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| 6 |
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| 7 | title: MIPS CPU Interrupt Controller
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| 8 |
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| 9 | description: >
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| 10 | On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
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| 11 | IRQs from a devicetree file and create a irq_domain for IRQ controller.
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| 12 |
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| 13 | With the irq_domain in place we can describe how the 8 IRQs are wired to the
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| 14 | platforms internal interrupt controller cascade.
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| 15 |
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| 16 | maintainers:
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| 17 | - Thomas Bogendoerfer <[email protected]>
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| 18 |
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| 19 | properties:
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| 20 | compatible:
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| 21 | const: mti,cpu-interrupt-controller
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| 22 |
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| 23 | '#interrupt-cells':
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| 24 | const: 1
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| 25 |
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| 26 | '#address-cells':
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| 27 | const: 0
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| 28 |
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| 29 | interrupt-controller: true
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| 30 |
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| 31 | additionalProperties: false
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| 32 |
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| 33 | required:
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| 34 | - compatible
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| 35 | - '#interrupt-cells'
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| 36 | - '#address-cells'
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| 37 | - interrupt-controller
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| 38 |
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| 39 | examples:
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| 40 | - |
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| 41 | interrupt-controller {
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| 42 | compatible = "mti,cpu-interrupt-controller";
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| 43 | #address-cells = <0>;
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| 44 | #interrupt-cells = <1>;
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| 45 | interrupt-controller;
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| 46 | };
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