| 1 | ==============================================
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| 2 | Ordering I/O writes to memory-mapped addresses
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| 3 | ==============================================
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| 4 |
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| 5 | On some platforms, so-called memory-mapped I/O is weakly ordered. On such
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| 6 | platforms, driver writers are responsible for ensuring that I/O writes to
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| 7 | memory-mapped addresses on their device arrive in the order intended. This is
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| 8 | typically done by reading a 'safe' device or bridge register, causing the I/O
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| 9 | chipset to flush pending writes to the device before any reads are posted. A
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| 10 | driver would usually use this technique immediately prior to the exit of a
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| 11 | critical section of code protected by spinlocks. This would ensure that
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| 12 | subsequent writes to I/O space arrived only after all prior writes (much like a
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| 13 | memory barrier op, mb(), only with respect to I/O).
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| 14 |
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| 15 | A more concrete example from a hypothetical device driver::
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| 16 |
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| 17 | ...
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| 18 | CPU A: spin_lock_irqsave(&dev_lock, flags)
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| 19 | CPU A: val = readl(my_status);
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| 20 | CPU A: ...
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| 21 | CPU A: writel(newval, ring_ptr);
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| 22 | CPU A: spin_unlock_irqrestore(&dev_lock, flags)
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| 23 | ...
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| 24 | CPU B: spin_lock_irqsave(&dev_lock, flags)
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| 25 | CPU B: val = readl(my_status);
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| 26 | CPU B: ...
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| 27 | CPU B: writel(newval2, ring_ptr);
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| 28 | CPU B: spin_unlock_irqrestore(&dev_lock, flags)
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| 29 | ...
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| 30 |
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| 31 | In the case above, the device may receive newval2 before it receives newval,
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| 32 | which could cause problems. Fixing it is easy enough though::
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| 33 |
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| 34 | ...
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| 35 | CPU A: spin_lock_irqsave(&dev_lock, flags)
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| 36 | CPU A: val = readl(my_status);
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| 37 | CPU A: ...
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| 38 | CPU A: writel(newval, ring_ptr);
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| 39 | CPU A: (void)readl(safe_register); /* maybe a config register? */
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| 40 | CPU A: spin_unlock_irqrestore(&dev_lock, flags)
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| 41 | ...
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| 42 | CPU B: spin_lock_irqsave(&dev_lock, flags)
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| 43 | CPU B: val = readl(my_status);
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| 44 | CPU B: ...
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| 45 | CPU B: writel(newval2, ring_ptr);
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| 46 | CPU B: (void)readl(safe_register); /* maybe a config register? */
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| 47 | CPU B: spin_unlock_irqrestore(&dev_lock, flags)
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| 48 |
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| 49 | Here, the reads from safe_register will cause the I/O chipset to flush any
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| 50 | pending writes before actually posting the read to the chipset, preventing
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| 51 | possible data corruption.
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