| 1 | ===============
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| 2 | AMDGPU Glossary
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| 3 | ===============
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| 4 |
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| 5 | Here you can find some generic acronyms used in the amdgpu driver. Notice that
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| 6 | we have a dedicated glossary for Display Core at
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| 7 | 'Documentation/gpu/amdgpu/display/dc-glossary.rst'.
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| 8 |
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| 9 | .. glossary::
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| 10 |
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| 11 | active_cu_number
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| 12 | The number of CUs that are active on the system. The number of active
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| 13 | CUs may be less than SE * SH * CU depending on the board configuration.
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| 14 |
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| 15 | BACO
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| 16 | Bus Alive, Chip Off
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| 17 |
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| 18 | BOCO
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| 19 | Bus Off, Chip Off
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| 20 |
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| 21 | CE
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| 22 | Constant Engine
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| 23 |
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| 24 | CIK
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| 25 | Sea Islands
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| 26 |
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| 27 | CB
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| 28 | Color Buffer
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| 29 |
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| 30 | CP
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| 31 | Command Processor
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| 32 |
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| 33 | CPC
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| 34 | Command Processor Compute
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| 35 |
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| 36 | CPF
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| 37 | Command Processor Fetch
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| 38 |
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| 39 | CPG
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| 40 | Command Processor Graphics
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| 41 |
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| 42 | CPLIB
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| 43 | Content Protection Library
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| 44 |
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| 45 | CS
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| 46 | Command Submission
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| 47 |
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| 48 | CSB
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| 49 | Clear State Indirect Buffer
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| 50 |
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| 51 | CU
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| 52 | Compute Unit
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| 53 |
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| 54 | DB
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| 55 | Depth Buffer
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| 56 |
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| 57 | DFS
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| 58 | Digital Frequency Synthesizer
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| 59 |
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| 60 | ECP
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| 61 | Enhanced Content Protection
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| 62 |
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| 63 | EOP
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| 64 | End Of Pipe/Pipeline
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| 65 |
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| 66 | FLR
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| 67 | Function Level Reset
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| 68 |
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| 69 | GART
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| 70 | Graphics Address Remapping Table. This is the name we use for the GPUVM
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| 71 | page table used by the GPU kernel driver. It remaps system resources
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| 72 | (memory or MMIO space) into the GPU's address space so the GPU can access
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| 73 | them. The name GART harkens back to the days of AGP when the platform
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| 74 | provided an MMU that the GPU could use to get a contiguous view of
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| 75 | scattered pages for DMA. The MMU has since moved on to the GPU, but the
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| 76 | name stuck.
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| 77 |
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| 78 | GC
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| 79 | Graphics and Compute
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| 80 |
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| 81 | GDS
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| 82 | Global Data Share
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| 83 |
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| 84 | GE
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| 85 | Geometry Engine
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| 86 |
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| 87 | GMC
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| 88 | Graphic Memory Controller
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| 89 |
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| 90 | GPR
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| 91 | General Purpose Register
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| 92 |
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| 93 | GPUVM
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| 94 | GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple
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| 95 | virtual address spaces that can be in flight at any given time. These
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| 96 | allow the GPU to remap VRAM and system resources into GPU virtual address
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| 97 | spaces for use by the GPU kernel driver and applications using the GPU.
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| 98 | These provide memory protection for different applications using the GPU.
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| 99 |
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| 100 | GTT
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| 101 | Graphics Translation Tables. This is a memory pool managed through TTM
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| 102 | which provides access to system resources (memory or MMIO space) for
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| 103 | use by the GPU. These addresses can be mapped into the "GART" GPUVM page
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| 104 | table for use by the kernel driver or into per process GPUVM page tables
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| 105 | for application usage.
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| 106 |
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| 107 | GWS
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| 108 | Global Wave Sync
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| 109 |
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| 110 | IH
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| 111 | Interrupt Handler
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| 112 |
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| 113 | IV
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| 114 | Interrupt Vector
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| 115 |
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| 116 | HQD
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| 117 | Hardware Queue Descriptor
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| 118 |
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| 119 | IB
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| 120 | Indirect Buffer
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| 121 |
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| 122 | IMU
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| 123 | Integrated Management Unit (Power Management support)
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| 124 |
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| 125 | IP
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| 126 | Intellectual Property blocks
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| 127 |
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| 128 | KCQ
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| 129 | Kernel Compute Queue
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| 130 |
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| 131 | KFD
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| 132 | Kernel Fusion Driver
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| 133 |
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| 134 | KGQ
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| 135 | Kernel Graphics Queue
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| 136 |
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| 137 | KIQ
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| 138 | Kernel Interface Queue
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| 139 |
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| 140 | MC
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| 141 | Memory Controller
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| 142 |
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| 143 | MCBP
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| 144 | Mid Command Buffer Preemption
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| 145 |
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| 146 | ME
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| 147 | MicroEngine (Graphics)
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| 148 |
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| 149 | MEC
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| 150 | MicroEngine Compute
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| 151 |
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| 152 | MES
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| 153 | MicroEngine Scheduler
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| 154 |
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| 155 | MMHUB
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| 156 | Multi-Media HUB
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| 157 |
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| 158 | MQD
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| 159 | Memory Queue Descriptor
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| 160 |
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| 161 | PA
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| 162 | Primitive Assembler / Physical Address
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| 163 |
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| 164 | PDE
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| 165 | Page Directory Entry
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| 166 |
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| 167 | PFP
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| 168 | Pre-Fetch Parser (Graphics)
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| 169 |
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| 170 | PPLib
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| 171 | PowerPlay Library - PowerPlay is the power management component.
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| 172 |
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| 173 | PRT
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| 174 | Partially Resident Texture (also known as sparse residency)
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| 175 |
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| 176 | PSP
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| 177 | Platform Security Processor
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| 178 |
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| 179 | PTE
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| 180 | Page Table Entry
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| 181 |
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| 182 | RB
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| 183 | Render Backends. Some people called it ROPs.
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| 184 |
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| 185 | RLC
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| 186 | RunList Controller. This name is a remnant of past ages and doesn't have
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| 187 | much meaning today. It's a group of general-purpose helper engines for
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| 188 | the GFX block. It's involved in GFX power management and SR-IOV, among
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| 189 | other things.
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| 190 |
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| 191 | SC
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| 192 | Scan Converter
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| 193 |
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| 194 | SDMA
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| 195 | System DMA
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| 196 |
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| 197 | SE
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| 198 | Shader Engine
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| 199 |
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| 200 | SGPR
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| 201 | Scalar General-Purpose Registers
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| 202 |
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| 203 | SH
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| 204 | SHader array
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| 205 |
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| 206 | SI
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| 207 | Southern Islands
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| 208 |
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| 209 | SMU/SMC
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| 210 | System Management Unit / System Management Controller
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| 211 |
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| 212 | SPI (AMDGPU)
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| 213 | Shader Processor Input
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| 214 |
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| 215 | SRLC
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| 216 | Save/Restore List Control
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| 217 |
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| 218 | SRLG
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| 219 | Save/Restore List GPM_MEM
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| 220 |
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| 221 | SRLS
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| 222 | Save/Restore List SRM_MEM
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| 223 |
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| 224 | SS
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| 225 | Spread Spectrum
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| 226 |
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| 227 | SX
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| 228 | Shader Export
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| 229 |
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| 230 | TA
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| 231 | Trusted Application
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| 232 |
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| 233 | TC
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| 234 | Texture Cache
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| 235 |
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| 236 | TCC
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| 237 | Texture Cache per Channel - L2 cache attached to the memory channels.
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| 238 | May be used when shader cores are accessing memory.
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| 239 | Despite "Texture" in the name, this is used by any kind of memory access.
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| 240 | TCCs may be mapped to TCPs, depending on the architecture.
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| 241 |
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| 242 | TCP (AMDGPU)
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| 243 | Texture Cache per Pipe - L1 cache attached to each CU.
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| 244 | Even though the name "Texture" is part of this
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| 245 | acronym, the TCP represents the path to memory shaders; i.e., it is not
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| 246 | related to texture. The name is a leftover from older designs where shader
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| 247 | stages had different cache designs; it refers to the L1 cache in older
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| 248 | architectures.
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| 249 |
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| 250 | TMR
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| 251 | Trusted Memory Region
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| 252 |
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| 253 | TMZ
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| 254 | Trusted Memory Zone
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| 255 |
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| 256 | TOC
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| 257 | Table of Contents
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| 258 |
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| 259 | UMC
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| 260 | Unified Memory Controller
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| 261 |
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| 262 | UMSCH
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| 263 | User Mode Scheduler
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| 264 |
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| 265 | UTC (AMDGPU)
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| 266 | Unified Translation Cache. UTC is equivalent to TLB. You might see a
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| 267 | variation of this acronym with L at the end, i.e., UTCL followed by a
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| 268 | number; L means the cache level (e.g., UTCL1 and UTCL2).
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| 269 |
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| 270 | UVD
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| 271 | Unified Video Decoder
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| 272 |
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| 273 | VCE
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| 274 | Video Compression Engine
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| 275 |
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| 276 | VCN
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| 277 | Video Codec Next
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| 278 |
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| 279 | VGPR
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| 280 | Vector General-Purpose Registers
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| 281 |
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| 282 | VMID
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| 283 | Virtual Memory ID
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| 284 |
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| 285 | VPE
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| 286 | Video Processing Engine
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| 287 |
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| 288 | XCC
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| 289 | Accelerator Core Complex
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| 290 |
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| 291 | XCP
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| 292 | Accelerator Core Partition
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