| 1 |
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| 2 | #ifndef __ASM_ALPHA_AUXVEC_H
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| 3 | #define __ASM_ALPHA_AUXVEC_H
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| 4 |
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| 5 |
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| 6 | #if 0 |
| 7 | #define AT_SYSINFO 32
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| 8 | #define AT_SYSINFO_EHDR 33
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| 9 | #endif
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| 10 |
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| 11 | |
| 12 | value is -1, then the cache doesn't exist. Otherwise:
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| 13 |
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| 14 | bit 0-3: Cache set-associativity; 0 means fully associative.
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| 15 | bit 4-7: Log2 of cacheline size.
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| 16 | bit 8-31: Size of the entire cache >> 8.
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| 17 | bit 32-63: Reserved.
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| 18 |
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| 19 |
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| 20 | #define AT_L1I_CACHESHAPE 34
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| 21 | #define AT_L1D_CACHESHAPE 35
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| 22 | #define AT_L2_CACHESHAPE 36
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| 23 | #define AT_L3_CACHESHAPE 37
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| 24 |
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| 25 | #define AT_VECTOR_SIZE_ARCH 4
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| 26 |
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| 27 | #endif
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