| 1 | |
| 2 | |
| 3 | * linux/arch/alpha/kernel/sys_mikasa.c
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| 4 | *
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| 5 | * Copyright (C) 1995 David A Rusling
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| 6 | * Copyright (C) 1996 Jay A Estabrook
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| 7 | * Copyright (C) 1998, 1999 Richard Henderson
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| 8 | *
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| 9 | * Code supporting the MIKASA (AlphaServer 1000).
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| 10 |
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| 11 |
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| 12 | #include <linux/kernel.h>
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| 13 | #include <linux/types.h>
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| 14 | #include <linux/mm.h>
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| 15 | #include <linux/sched.h>
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| 16 | #include <linux/pci.h>
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| 17 | #include <linux/init.h>
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| 18 | #include <linux/bitops.h>
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| 19 |
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| 20 | #include <asm/ptrace.h>
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| 21 | #include <asm/mce.h>
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| 22 | #include <asm/dma.h>
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| 23 | #include <asm/irq.h>
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| 24 | #include <asm/mmu_context.h>
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| 25 | #include <asm/io.h>
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| 26 | #include <asm/core_cia.h>
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| 27 | #include <asm/tlbflush.h>
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| 28 |
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| 29 | #include "proto.h"
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| 30 | #include "irq_impl.h"
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| 31 | #include "pci_impl.h"
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| 32 | #include "machvec_impl.h"
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| 33 |
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| 34 |
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| 35 |
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| 36 | static int cached_irq_mask;
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| 37 |
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| 38 | static inline void
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| 39 | mikasa_update_irq_hw(int mask)
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| 40 | {
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| 41 | outw(mask, 0x536);
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| 42 | }
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| 43 |
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| 44 | static inline void
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| 45 | mikasa_enable_irq(struct irq_data *d)
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| 46 | {
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| 47 | mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16));
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| 48 | }
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| 49 |
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| 50 | static void
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| 51 | mikasa_disable_irq(struct irq_data *d)
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| 52 | {
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| 53 | mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16)));
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| 54 | }
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| 55 |
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| 56 | static struct irq_chip mikasa_irq_type = {
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| 57 | .name = "MIKASA",
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| 58 | .irq_unmask = mikasa_enable_irq,
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| 59 | .irq_mask = mikasa_disable_irq,
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| 60 | .irq_mask_ack = mikasa_disable_irq,
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| 61 | };
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| 62 |
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| 63 | static void
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| 64 | mikasa_device_interrupt(unsigned long vector)
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| 65 | {
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| 66 | unsigned long pld;
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| 67 | unsigned int i;
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| 68 |
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| 69 |
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| 70 | pld = (((~inw(0x534) & 0x0000ffffUL) << 16)
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| 71 | | (((unsigned long) inb(0xa0)) << 8)
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| 72 | | inb(0x20));
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| 73 |
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| 74 | |
| 75 | * Now for every possible bit set, work through them and call
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| 76 | * the appropriate interrupt handler.
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| 77 |
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| 78 | while (pld) {
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| 79 | i = ffz(~pld);
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| 80 | pld &= pld - 1;
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| 81 | if (i < 16) {
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| 82 | isa_device_interrupt(vector);
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| 83 | } else {
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| 84 | handle_irq(i);
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| 85 | }
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| 86 | }
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| 87 | }
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| 88 |
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| 89 | static void __init
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| 90 | mikasa_init_irq(void)
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| 91 | {
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| 92 | long i;
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| 93 |
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| 94 | if (alpha_using_srm)
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| 95 | alpha_mv.device_interrupt = srm_device_interrupt;
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| 96 |
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| 97 | mikasa_update_irq_hw(0);
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| 98 |
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| 99 | for (i = 16; i < 32; ++i) {
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| 100 | irq_set_chip_and_handler(i, &mikasa_irq_type,
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| 101 | handle_level_irq);
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| 102 | irq_set_status_flags(i, IRQ_LEVEL);
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| 103 | }
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| 104 |
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| 105 | init_i8259a_irqs();
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| 106 | common_init_isa_dma();
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| 107 | }
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| 108 |
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| 109 |
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| 110 | |
| 111 | * PCI Fixup configuration.
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| 112 | *
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| 113 | * Summary @ 0x536:
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| 114 | * Bit Meaning
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| 115 | * 0 Interrupt Line A from slot 0
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| 116 | * 1 Interrupt Line B from slot 0
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| 117 | * 2 Interrupt Line C from slot 0
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| 118 | * 3 Interrupt Line D from slot 0
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| 119 | * 4 Interrupt Line A from slot 1
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| 120 | * 5 Interrupt line B from slot 1
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| 121 | * 6 Interrupt Line C from slot 1
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| 122 | * 7 Interrupt Line D from slot 1
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| 123 | * 8 Interrupt Line A from slot 2
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| 124 | * 9 Interrupt Line B from slot 2
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| 125 | *10 Interrupt Line C from slot 2
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| 126 | *11 Interrupt Line D from slot 2
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| 127 | *12 NCR 810 SCSI
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| 128 | *13 Power Supply Fail
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| 129 | *14 Temperature Warn
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| 130 | *15 Reserved
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| 131 | *
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| 132 | * The device to slot mapping looks like:
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| 133 | *
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| 134 | * Slot Device
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| 135 | * 6 NCR SCSI controller
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| 136 | * 7 Intel PCI-EISA bridge chip
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| 137 | * 11 PCI on board slot 0
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| 138 | * 12 PCI on board slot 1
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| 139 | * 13 PCI on board slot 2
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| 140 | *
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| 141 | *
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| 142 | * This two layered interrupt approach means that we allocate IRQ 16 and
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| 143 | * above for PCI interrupts. The IRQ relates to which bit the interrupt
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| 144 | * comes in on. This makes interrupt processing much easier.
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| 145 |
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| 146 |
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| 147 | static int
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| 148 | mikasa_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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| 149 | {
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| 150 | static char irq_tab[8][5] = {
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| 151 |
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| 152 | {16+12, 16+12, 16+12, 16+12, 16+12},
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| 153 | { -1, -1, -1, -1, -1},
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| 154 | { -1, -1, -1, -1, -1},
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| 155 | { -1, -1, -1, -1, -1},
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| 156 | { -1, -1, -1, -1, -1},
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| 157 | { 16+0, 16+0, 16+1, 16+2, 16+3},
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| 158 | { 16+4, 16+4, 16+5, 16+6, 16+7},
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| 159 | { 16+8, 16+8, 16+9, 16+10, 16+11},
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| 160 | };
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| 161 | const long min_idsel = 6, max_idsel = 13, irqs_per_slot = 5;
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| 162 | return COMMON_TABLE_LOOKUP;
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| 163 | }
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| 164 |
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| 165 |
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| 166 | |
| 167 | * The System Vector
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| 168 |
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| 169 | struct alpha_machine_vector mikasa_primo_mv __initmv = {
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| 170 | .vector_name = "Mikasa-Primo",
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| 171 | DO_EV5_MMU,
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| 172 | DO_DEFAULT_RTC,
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| 173 | DO_CIA_IO,
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| 174 | .machine_check = cia_machine_check,
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| 175 | .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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| 176 | .min_io_address = DEFAULT_IO_BASE,
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| 177 | .min_mem_address = CIA_DEFAULT_MEM_BASE,
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| 178 |
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| 179 | .nr_irqs = 32,
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| 180 | .device_interrupt = mikasa_device_interrupt,
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| 181 |
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| 182 | .init_arch = cia_init_arch,
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| 183 | .init_irq = mikasa_init_irq,
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| 184 | .init_rtc = common_init_rtc,
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| 185 | .init_pci = cia_init_pci,
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| 186 | .kill_arch = cia_kill_arch,
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| 187 | .pci_map_irq = mikasa_map_irq,
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| 188 | .pci_swizzle = common_swizzle,
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| 189 | };
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| 190 | ALIAS_MV(mikasa_primo)
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