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1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/module.h>
3#include <linux/types.h>
4#include <linux/kernel.h>
5#include <linux/sched.h>
6#include <asm/ptrace.h>
7#include <asm/fpu.h>
8
9#include <linux/uaccess.h>
10
11#include "sfp-util.h"
12#include <math-emu/soft-fp.h>
13#include <math-emu/single.h>
14#include <math-emu/double.h>
15
16#define OPC_PAL 0x00
17#define OPC_INTA 0x10
18#define OPC_INTL 0x11
19#define OPC_INTS 0x12
20#define OPC_INTM 0x13
21#define OPC_FLTC 0x14
22#define OPC_FLTV 0x15
23#define OPC_FLTI 0x16
24#define OPC_FLTL 0x17
25#define OPC_MISC 0x18
26#define OPC_JSR 0x1a
27
28#define FOP_SRC_S 0
29#define FOP_SRC_T 2
30#define FOP_SRC_Q 3
31
32#define FOP_FNC_ADDx 0
33#define FOP_FNC_CVTQL 0
34#define FOP_FNC_SUBx 1
35#define FOP_FNC_MULx 2
36#define FOP_FNC_DIVx 3
37#define FOP_FNC_CMPxUN 4
38#define FOP_FNC_CMPxEQ 5
39#define FOP_FNC_CMPxLT 6
40#define FOP_FNC_CMPxLE 7
41#define FOP_FNC_SQRTx 11
42#define FOP_FNC_CVTxS 12
43#define FOP_FNC_CVTxT 14
44#define FOP_FNC_CVTxQ 15
45
46#define MISC_TRAPB 0x0000
47#define MISC_EXCB 0x0400
48
49#ifdef MODULE
50
51MODULE_DESCRIPTION("FP Software completion module");
52MODULE_LICENSE("GPL v2");
53
54extern long (*alpha_fp_emul_imprecise)(struct pt_regs *, unsigned long);
55extern long (*alpha_fp_emul) (unsigned long pc, unsigned long summary);
56
57static long (*save_emul_imprecise)(struct pt_regs *, unsigned long);
58static long (*save_emul) (unsigned long pc, unsigned long summary);
59
60long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long);
61long do_alpha_fp_emul(unsigned long, unsigned long);
62
63static int alpha_fp_emul_init_module(void)
64{
65 save_emul_imprecise = alpha_fp_emul_imprecise;
66 save_emul = alpha_fp_emul;
67 alpha_fp_emul_imprecise = do_alpha_fp_emul_imprecise;
68 alpha_fp_emul = do_alpha_fp_emul;
69 return 0;
70}
71module_init(alpha_fp_emul_init_module);
72
73static void alpha_fp_emul_cleanup_module(void)
74{
75 alpha_fp_emul_imprecise = save_emul_imprecise;
76 alpha_fp_emul = save_emul;
77}
78module_exit(alpha_fp_emul_cleanup_module);
79
80#undef alpha_fp_emul_imprecise
81#define alpha_fp_emul_imprecise do_alpha_fp_emul_imprecise
82#undef alpha_fp_emul
83#define alpha_fp_emul do_alpha_fp_emul
84
85#endif /* MODULE */
86
87
88/*
89 * Exception bits of the exception summary register (EXC_SUM). Bit 0 is the
90 * software completion bit; bits 1 through 5 report the exceptions the
91 * hardware attributed to the trapping instruction, and lie at the same
92 * positions as the corresponding IEEE_TRAP_ENABLE_* bits.
93 */
94#define EXC_SUM_INV (1UL << 1)
95#define EXC_SUM_DZE (1UL << 2)
96#define EXC_SUM_OVF (1UL << 3)
97#define EXC_SUM_UNF (1UL << 4)
98#define EXC_SUM_INE (1UL << 5)
99#define EXC_SUM_MASK (EXC_SUM_INV | EXC_SUM_DZE | EXC_SUM_OVF \
100 | EXC_SUM_UNF | EXC_SUM_INE)
101
102/*
103 * Emulate the floating point instruction at address PC. SUMMARY is the
104 * exception summary register the trap was delivered with. Returns -1 if the
105 * instruction to be emulated is illegal (such as with the opDEC trap), else
106 * the SI_CODE for a SIGFPE signal, else 0 if everything's ok.
107 *
108 * Notice that the kernel does not and cannot use FP regs. This is good
109 * because it means that instead of saving/restoring all fp regs, we simply
110 * stick the result of the operation into the appropriate register.
111 */
112long
113alpha_fp_emul (unsigned long pc, unsigned long summary)
114{
115 FP_DECL_EX;
116 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
117 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
118
119 unsigned long fa, fb, fc, func, mode, src;
120 unsigned long res, va, vb, vc, swcr, fpcr;
121 __u32 insn;
122 long si_code;
123
124 get_user(insn, (__u32 __user *)pc);
125 fc = (insn >> 0) & 0x1f; /* destination register */
126 fb = (insn >> 16) & 0x1f;
127 fa = (insn >> 21) & 0x1f;
128 func = (insn >> 5) & 0xf;
129 src = (insn >> 9) & 0x3;
130 mode = (insn >> 11) & 0x3;
131
132 fpcr = rdfpcr();
133 swcr = swcr_update_status(current_thread_info()->ieee_state, fpcr);
134
135 if (mode == 3) {
136 /* Dynamic -- get rounding mode from fpcr. */
137 mode = (fpcr >> FPCR_DYN_SHIFT) & 3;
138 }
139
140 switch (src) {
141 case FOP_SRC_S:
142 va = alpha_read_fp_reg_s(fa);
143 vb = alpha_read_fp_reg_s(fb);
144
145 FP_UNPACK_SP(SA, &va);
146 FP_UNPACK_SP(SB, &vb);
147
148 switch (func) {
149 case FOP_FNC_SUBx:
150 FP_SUB_S(SR, SA, SB);
151 goto pack_s;
152
153 case FOP_FNC_ADDx:
154 FP_ADD_S(SR, SA, SB);
155 goto pack_s;
156
157 case FOP_FNC_MULx:
158 FP_MUL_S(SR, SA, SB);
159 goto pack_s;
160
161 case FOP_FNC_DIVx:
162 FP_DIV_S(SR, SA, SB);
163 goto pack_s;
164
165 case FOP_FNC_SQRTx:
166 FP_SQRT_S(SR, SB);
167 goto pack_s;
168 }
169 goto bad_insn;
170
171 case FOP_SRC_T:
172 va = alpha_read_fp_reg(fa);
173 vb = alpha_read_fp_reg(fb);
174
175 if ((func & ~3) == FOP_FNC_CMPxUN) {
176 FP_UNPACK_RAW_DP(DA, &va);
177 FP_UNPACK_RAW_DP(DB, &vb);
178 if (!DA_e && !_FP_FRAC_ZEROP_1(DA)) {
179 FP_SET_EXCEPTION(FP_EX_DENORM);
180 if (FP_DENORM_ZERO)
181 _FP_FRAC_SET_1(DA, _FP_ZEROFRAC_1);
182 }
183 if (!DB_e && !_FP_FRAC_ZEROP_1(DB)) {
184 FP_SET_EXCEPTION(FP_EX_DENORM);
185 if (FP_DENORM_ZERO)
186 _FP_FRAC_SET_1(DB, _FP_ZEROFRAC_1);
187 }
188 FP_CMP_D(res, DA, DB, 3);
189 vc = 0x4000000000000000UL;
190 /* CMPTEQ, CMPTUN don't trap on QNaN,
191 while CMPTLT and CMPTLE do */
192 if (res == 3
193 && ((func & 3) >= 2
194 || FP_ISSIGNAN_D(DA)
195 || FP_ISSIGNAN_D(DB))) {
196 FP_SET_EXCEPTION(FP_EX_INVALID);
197 }
198 switch (func) {
199 case FOP_FNC_CMPxUN: if (res != 3) vc = 0; break;
200 case FOP_FNC_CMPxEQ: if (res) vc = 0; break;
201 case FOP_FNC_CMPxLT: if (res != -1) vc = 0; break;
202 case FOP_FNC_CMPxLE: if ((long)res > 0) vc = 0; break;
203 }
204 goto done_d;
205 }
206
207 FP_UNPACK_DP(DA, &va);
208 FP_UNPACK_DP(DB, &vb);
209
210 switch (func) {
211 case FOP_FNC_SUBx:
212 FP_SUB_D(DR, DA, DB);
213 goto pack_d;
214
215 case FOP_FNC_ADDx:
216 FP_ADD_D(DR, DA, DB);
217 goto pack_d;
218
219 case FOP_FNC_MULx:
220 FP_MUL_D(DR, DA, DB);
221 goto pack_d;
222
223 case FOP_FNC_DIVx:
224 FP_DIV_D(DR, DA, DB);
225 goto pack_d;
226
227 case FOP_FNC_SQRTx:
228 FP_SQRT_D(DR, DB);
229 goto pack_d;
230
231 case FOP_FNC_CVTxS:
232 /* It is irritating that DEC encoded CVTST with
233 SRC == T_floating. It is also interesting that
234 the bit used to tell the two apart is /U... */
235 if (insn & 0x2000) {
236 FP_CONV(S,D,1,1,SR,DB);
237 goto pack_s;
238 } else {
239 vb = alpha_read_fp_reg_s(fb);
240 FP_UNPACK_SP(SB, &vb);
241 DR_c = DB_c;
242 DR_s = DB_s;
243 DR_e = DB_e + (1024 - 128);
244 DR_f = SB_f << (52 - 23);
245 goto pack_d;
246 }
247
248 case FOP_FNC_CVTxQ:
249 if (DB_c == FP_CLS_NAN
250 && (_FP_FRAC_HIGH_RAW_D(DB) & _FP_QNANBIT_D)) {
251 /* AAHB Table B-2 says QNaN should not trigger INV */
252 vc = 0;
253 } else
254 FP_TO_INT_ROUND_D(vc, DB, 64, 2);
255 goto done_d;
256 }
257 goto bad_insn;
258
259 case FOP_SRC_Q:
260 vb = alpha_read_fp_reg(fb);
261
262 switch (func) {
263 case FOP_FNC_CVTQL:
264 /* Notice: We can get here only due to an integer
265 overflow. Such overflows are reported as invalid
266 ops. We return the result the hw would have
267 computed. */
268 vc = ((vb & 0xc0000000) << 32 | /* sign and msb */
269 (vb & 0x3fffffff) << 29); /* rest of the int */
270 FP_SET_EXCEPTION (FP_EX_INVALID);
271 goto done_d;
272
273 case FOP_FNC_CVTxS:
274 FP_FROM_INT_S(SR, ((long)vb), 64, long);
275 goto pack_s;
276
277 case FOP_FNC_CVTxT:
278 FP_FROM_INT_D(DR, ((long)vb), 64, long);
279 goto pack_d;
280 }
281 goto bad_insn;
282 }
283 goto bad_insn;
284
285pack_s:
286 FP_PACK_SP(&vc, SR);
287 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
288 vc = 0;
289 alpha_write_fp_reg_s(fc, vc);
290 goto done;
291
292pack_d:
293 FP_PACK_DP(&vc, DR);
294 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
295 vc = 0;
296done_d:
297 alpha_write_fp_reg(fc, vc);
298 goto done;
299
300 /*
301 * Take the appropriate action for each possible
302 * floating-point result:
303 *
304 * - Set the appropriate bits in the FPCR
305 * - If the specified exception is enabled in the FPCR,
306 * return. The caller (entArith) will dispatch
307 * the appropriate signal to the translated program.
308 *
309 * In addition, properly track the exception state in software
310 * as described in the Alpha Architecture Handbook section 4.7.7.3.
311 */
312done:
313 if (_fex) {
314 /* Record exceptions in software control word. */
315 swcr |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
316 current_thread_info()->ieee_state
317 |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
318 }
319
320 /*
321 * EV6 records exception status bits in the FPCR before delivering the
322 * software completion trap, and swcr_update_status() above merged them
323 * into SWCR. Some can be wrong for the instruction we just emulated:
324 * a CVTTS of a value exactly representable as a subnormal sets FPCR_UNF
325 * even though the result is exact. Clear the exceptions the trap
326 * reported but that soft-fp did not raise.
327 */
328 if (implver() == IMPLVER_EV6) {
329 unsigned long spurious = summary & EXC_SUM_MASK;
330
331 if (spurious & (EXC_SUM_UNF | EXC_SUM_OVF)) {
332 /*
333 * EXC_SUM reports only the underflow or overflow,
334 * but the hardware sets INE alongside it in the FPCR.
335 */
336 spurious |= EXC_SUM_INE;
337 } else if (!spurious) {
338 /*
339 * No exception reported, so this was a denormal
340 * operand trap, for which INE and UNF can be
341 * fabricated as well.
342 */
343 spurious = EXC_SUM_INE | EXC_SUM_UNF;
344 }
345
346 /*
347 * Never clear an exception software has confirmed. Every
348 * instruction that genuinely raises one traps for software
349 * completion and is recorded in ieee_state above, so a bit
350 * found there -- including one just set from _fex -- belongs
351 * to this or an earlier instruction and must survive.
352 */
353 spurious &= ~(current_thread_info()->ieee_state
354 >> IEEE_STATUS_TO_EXCSUM_SHIFT);
355
356 swcr &= ~(spurious << IEEE_STATUS_TO_EXCSUM_SHIFT);
357 }
358
359 /*
360 * Update hardware control register. This has to happen even when
361 * soft-fp raised nothing, to clear any fabricated bits.
362 */
363 fpcr &= (~FPCR_MASK | FPCR_DYN_MASK);
364 fpcr |= ieee_swcr_to_fpcr(swcr);
365 wrfpcr(fpcr);
366
367 if (_fex) {
368 /* Do we generate a signal? */
369 _fex = _fex & swcr & IEEE_TRAP_ENABLE_MASK;
370 si_code = 0;
371 if (_fex) {
372 if (_fex & IEEE_TRAP_ENABLE_DNO) si_code = FPE_FLTUND;
373 if (_fex & IEEE_TRAP_ENABLE_INE) si_code = FPE_FLTRES;
374 if (_fex & IEEE_TRAP_ENABLE_UNF) si_code = FPE_FLTUND;
375 if (_fex & IEEE_TRAP_ENABLE_OVF) si_code = FPE_FLTOVF;
376 if (_fex & IEEE_TRAP_ENABLE_DZE) si_code = FPE_FLTDIV;
377 if (_fex & IEEE_TRAP_ENABLE_INV) si_code = FPE_FLTINV;
378 }
379
380 return si_code;
381 }
382
383 /* We used to write the destination register here, but DEC FORTRAN
384 requires that the result *always* be written... so we do the write
385 immediately after the operations above. */
386
387 return 0;
388
389bad_insn:
390 printk(KERN_ERR "alpha_fp_emul: Invalid FP insn %#x at %#lx\n",
391 insn, pc);
392 return -1;
393}
394
395long
396alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask)
397{
398 unsigned long trigger_pc = regs->pc - 4;
399 unsigned long insn, opcode, rc, si_code = 0;
400
401 /*
402 * Turn off the bits corresponding to registers that are the
403 * target of instructions that set bits in the exception
404 * summary register. We have some slack doing this because a
405 * register that is the target of a trapping instruction can
406 * be written at most once in the trap shadow.
407 *
408 * Branches, jumps, TRAPBs, EXCBs and calls to PALcode all
409 * bound the trap shadow, so we need not look any further than
410 * up to the first occurrence of such an instruction.
411 */
412 while (write_mask) {
413 get_user(insn, (__u32 __user *)(trigger_pc));
414 opcode = insn >> 26;
415 rc = insn & 0x1f;
416
417 switch (opcode) {
418 case OPC_PAL:
419 case OPC_JSR:
420 case 0x30 ... 0x3f: /* branches */
421 goto egress;
422
423 case OPC_MISC:
424 switch (insn & 0xffff) {
425 case MISC_TRAPB:
426 case MISC_EXCB:
427 goto egress;
428
429 default:
430 break;
431 }
432 break;
433
434 case OPC_INTA:
435 case OPC_INTL:
436 case OPC_INTS:
437 case OPC_INTM:
438 write_mask &= ~(1UL << rc);
439 break;
440
441 case OPC_FLTC:
442 case OPC_FLTV:
443 case OPC_FLTI:
444 case OPC_FLTL:
445 write_mask &= ~(1UL << (rc + 32));
446 break;
447 }
448 if (!write_mask) {
449 /*
450 * Re-execute insns in the trap-shadow. Pass no
451 * exception summary: it describes the trap, which
452 * was taken anywhere in the shadow, and so is not
453 * attribution for this instruction. Nothing is
454 * lost, since only EV6 -- which traps precisely and
455 * never comes this way -- needs it.
456 */
457 regs->pc = trigger_pc + 4;
458 si_code = alpha_fp_emul(trigger_pc, 0);
459 goto egress;
460 }
461 trigger_pc -= 4;
462 }
463
464egress:
465 return si_code;
466}