| 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | # |
| 3 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
| 4 | # |
| 5 | |
| 6 | config ARC |
| 7 | def_bool y |
| 8 | select ARC_TIMERS |
| 9 | select ARCH_HAS_CPU_CACHE_ALIASING |
| 10 | select ARCH_HAS_CACHE_LINE_SIZE |
| 11 | select ARCH_HAS_DEBUG_VM_PGTABLE |
| 12 | select ARCH_HAS_DMA_PREP_COHERENT |
| 13 | select ARCH_HAS_PTE_SPECIAL |
| 14 | select ARCH_HAS_SETUP_DMA_OPS |
| 15 | select ARCH_HAS_SYNC_DMA_FOR_CPU |
| 16 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
| 17 | select ARCH_NEED_CMPXCHG_1_EMU |
| 18 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
| 19 | select ARCH_32BIT_OFF_T |
| 20 | select BUILDTIME_TABLE_SORT |
| 21 | select GENERIC_BUILTIN_DTB |
| 22 | select CLONE_BACKWARDS |
| 23 | select COMMON_CLK |
| 24 | select DMA_DIRECT_REMAP |
| 25 | select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) |
| 26 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP |
| 27 | select GENERIC_IRQ_SHOW |
| 28 | select GENERIC_PCI_IOMAP |
| 29 | select GENERIC_SCHED_CLOCK |
| 30 | select GENERIC_SMP_IDLE_THREAD |
| 31 | select GENERIC_IOREMAP |
| 32 | select GENERIC_STRNCPY_FROM_USER if MMU |
| 33 | select GENERIC_STRNLEN_USER if MMU |
| 34 | select HAVE_ARCH_KGDB |
| 35 | select HAVE_ARCH_TRACEHOOK |
| 36 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4 |
| 37 | select HAVE_DEBUG_STACKOVERFLOW |
| 38 | select HAVE_DEBUG_KMEMLEAK |
| 39 | select HAVE_IOREMAP_PROT |
| 40 | select HAVE_KERNEL_GZIP |
| 41 | select HAVE_KERNEL_LZMA |
| 42 | select HAVE_KPROBES |
| 43 | select HAVE_KRETPROBES |
| 44 | select HAVE_REGS_AND_STACK_ACCESS_API |
| 45 | select HAVE_MOD_ARCH_SPECIFIC |
| 46 | select HAVE_PERF_EVENTS |
| 47 | select HAVE_SYSCALL_TRACEPOINTS |
| 48 | select IRQ_DOMAIN |
| 49 | select LOCK_MM_AND_FIND_VMA |
| 50 | select MODULES_USE_ELF_RELA |
| 51 | select OF |
| 52 | select OF_EARLY_FLATTREE |
| 53 | select PCI_SYSCALL if PCI |
| 54 | select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 |
| 55 | select TRACE_IRQFLAGS_SUPPORT |
| 56 | select HAVE_EBPF_JIT if ISA_ARCV2 |
| 57 | |
| 58 | config LOCKDEP_SUPPORT |
| 59 | def_bool y |
| 60 | |
| 61 | config SCHED_OMIT_FRAME_POINTER |
| 62 | def_bool y |
| 63 | |
| 64 | config GENERIC_CSUM |
| 65 | def_bool y |
| 66 | |
| 67 | config ARCH_FLATMEM_ENABLE |
| 68 | def_bool y |
| 69 | |
| 70 | config MMU |
| 71 | def_bool y |
| 72 | |
| 73 | config NO_IOPORT_MAP |
| 74 | def_bool y |
| 75 | |
| 76 | config GENERIC_CALIBRATE_DELAY |
| 77 | def_bool y |
| 78 | |
| 79 | config GENERIC_HWEIGHT |
| 80 | def_bool y |
| 81 | |
| 82 | config STACKTRACE_SUPPORT |
| 83 | def_bool y |
| 84 | select STACKTRACE |
| 85 | |
| 86 | menu "ARC Architecture Configuration" |
| 87 | |
| 88 | menu "ARC Platform/SoC/Board" |
| 89 | |
| 90 | source "arch/arc/plat-tb10x/Kconfig" |
| 91 | source "arch/arc/plat-axs10x/Kconfig" |
| 92 | source "arch/arc/plat-hsdk/Kconfig" |
| 93 | |
| 94 | endmenu |
| 95 | |
| 96 | choice |
| 97 | prompt "ARC Instruction Set" |
| 98 | default ISA_ARCV2 |
| 99 | |
| 100 | config ISA_ARCOMPACT |
| 101 | bool "ARCompact ISA" |
| 102 | select CPU_NO_EFFICIENT_FFS |
| 103 | help |
| 104 | The original ARC ISA of ARC600/700 cores |
| 105 | |
| 106 | config ISA_ARCV2 |
| 107 | bool "ARC ISA v2" |
| 108 | select ARC_TIMERS_64BIT |
| 109 | help |
| 110 | ISA for the Next Generation ARC-HS cores |
| 111 | |
| 112 | endchoice |
| 113 | |
| 114 | menu "ARC CPU Configuration" |
| 115 | |
| 116 | choice |
| 117 | prompt "ARC Core" |
| 118 | default ARC_CPU_770 if ISA_ARCOMPACT |
| 119 | default ARC_CPU_HS if ISA_ARCV2 |
| 120 | |
| 121 | config ARC_CPU_770 |
| 122 | bool "ARC770" |
| 123 | depends on ISA_ARCOMPACT |
| 124 | help |
| 125 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) |
| 126 | This core has a bunch of cool new features: |
| 127 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) |
| 128 | Shared Address Spaces (for sharing TLB entries in MMU) |
| 129 | -Caches: New Prog Model, Region Flush |
| 130 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr |
| 131 | |
| 132 | config ARC_CPU_HS |
| 133 | bool "ARC-HS" |
| 134 | depends on ISA_ARCV2 |
| 135 | help |
| 136 | Support for ARC HS38x Cores based on ARCv2 ISA |
| 137 | The notable features are: |
| 138 | - SMP configurations of up to 4 cores with coherency |
| 139 | - Optional L2 Cache and IO-Coherency |
| 140 | - Revised Interrupt Architecture (multiple priorites, reg banks, |
| 141 | auto stack switch, auto regfile save/restore) |
| 142 | - MMUv4 (PIPT dcache, Huge Pages) |
| 143 | - Instructions for |
| 144 | * 64bit load/store: LDD, STD |
| 145 | * Hardware assisted divide/remainder: DIV, REM |
| 146 | * Function prologue/epilogue: ENTER_S, LEAVE_S |
| 147 | * IRQ enable/disable: CLRI, SETI |
| 148 | * pop count: FFS, FLS |
| 149 | * SETcc, BMSKN, XBFU... |
| 150 | |
| 151 | endchoice |
| 152 | |
| 153 | config ARC_TUNE_MCPU |
| 154 | string "Override default -mcpu compiler flag" |
| 155 | default "" |
| 156 | help |
| 157 | Override default -mcpu=xxx compiler flag (which is set depending on |
| 158 | the ISA version) with the specified value. |
| 159 | NOTE: If specified flag isn't supported by current compiler the |
| 160 | ISA default value will be used as a fallback. |
| 161 | |
| 162 | config CPU_BIG_ENDIAN |
| 163 | bool "Enable Big Endian Mode" |
| 164 | help |
| 165 | Build kernel for Big Endian Mode of ARC CPU |
| 166 | |
| 167 | config SMP |
| 168 | bool "Symmetric Multi-Processing" |
| 169 | select ARC_MCIP if ISA_ARCV2 |
| 170 | help |
| 171 | This enables support for systems with more than one CPU. |
| 172 | |
| 173 | if SMP |
| 174 | |
| 175 | config NR_CPUS |
| 176 | int "Maximum number of CPUs (2-4096)" |
| 177 | range 2 4096 |
| 178 | default "4" |
| 179 | |
| 180 | config ARC_SMP_HALT_ON_RESET |
| 181 | bool "Enable Halt-on-reset boot mode" |
| 182 | help |
| 183 | In SMP configuration cores can be configured as Halt-on-reset |
| 184 | or they could all start at same time. For Halt-on-reset, non |
| 185 | masters are parked until Master kicks them so they can start off |
| 186 | at designated entry point. For other case, all jump to common |
| 187 | entry point and spin wait for Master's signal. |
| 188 | |
| 189 | endif #SMP |
| 190 | |
| 191 | config ARC_MCIP |
| 192 | bool "ARConnect Multicore IP (MCIP) Support " |
| 193 | depends on ISA_ARCV2 |
| 194 | default y if SMP |
| 195 | help |
| 196 | This IP block enables SMP in ARC-HS38 cores. |
| 197 | It provides for cross-core interrupts, multi-core debug |
| 198 | hardware semaphores, shared memory,.... |
| 199 | |
| 200 | menuconfig ARC_CACHE |
| 201 | bool "Enable Cache Support" |
| 202 | default y |
| 203 | |
| 204 | if ARC_CACHE |
| 205 | |
| 206 | config ARC_CACHE_LINE_SHIFT |
| 207 | int "Cache Line Length (as power of 2)" |
| 208 | range 5 7 |
| 209 | default "6" |
| 210 | help |
| 211 | Starting with ARC700 4.9, Cache line length is configurable, |
| 212 | This option specifies "N", with Line-len = 2 power N |
| 213 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively |
| 214 | Linux only supports same line lengths for I and D caches. |
| 215 | |
| 216 | config ARC_HAS_ICACHE |
| 217 | bool "Use Instruction Cache" |
| 218 | default y |
| 219 | |
| 220 | config ARC_HAS_DCACHE |
| 221 | bool "Use Data Cache" |
| 222 | default y |
| 223 | |
| 224 | config ARC_CACHE_PAGES |
| 225 | bool "Per Page Cache Control" |
| 226 | default y |
| 227 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE |
| 228 | help |
| 229 | This can be used to over-ride the global I/D Cache Enable on a |
| 230 | per-page basis (but only for pages accessed via MMU such as |
| 231 | Kernel Virtual address or User Virtual Address) |
| 232 | TLB entries have a per-page Cache Enable Bit. |
| 233 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary |
| 234 | Global DISABLE + Per Page ENABLE won't work |
| 235 | |
| 236 | endif #ARC_CACHE |
| 237 | |
| 238 | config ARC_HAS_ICCM |
| 239 | bool "Use ICCM" |
| 240 | help |
| 241 | Single Cycle RAMS to store Fast Path Code |
| 242 | |
| 243 | config ARC_ICCM_SZ |
| 244 | int "ICCM Size in KB" |
| 245 | default "64" |
| 246 | depends on ARC_HAS_ICCM |
| 247 | |
| 248 | config ARC_HAS_DCCM |
| 249 | bool "Use DCCM" |
| 250 | help |
| 251 | Single Cycle RAMS to store Fast Path Data |
| 252 | |
| 253 | config ARC_DCCM_SZ |
| 254 | int "DCCM Size in KB" |
| 255 | default "64" |
| 256 | depends on ARC_HAS_DCCM |
| 257 | |
| 258 | config ARC_DCCM_BASE |
| 259 | hex "DCCM map address" |
| 260 | default "0xA0000000" |
| 261 | depends on ARC_HAS_DCCM |
| 262 | |
| 263 | choice |
| 264 | prompt "MMU Version" |
| 265 | default ARC_MMU_V3 if ISA_ARCOMPACT |
| 266 | default ARC_MMU_V4 if ISA_ARCV2 |
| 267 | |
| 268 | config ARC_MMU_V3 |
| 269 | bool "MMU v3" |
| 270 | depends on ISA_ARCOMPACT |
| 271 | help |
| 272 | Introduced with ARC700 4.10: New Features |
| 273 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) |
| 274 | Shared Address Spaces (SASID) |
| 275 | |
| 276 | config ARC_MMU_V4 |
| 277 | bool "MMU v4" |
| 278 | depends on ISA_ARCV2 |
| 279 | |
| 280 | endchoice |
| 281 | |
| 282 | |
| 283 | choice |
| 284 | prompt "MMU Page Size" |
| 285 | default ARC_PAGE_SIZE_8K |
| 286 | |
| 287 | config ARC_PAGE_SIZE_8K |
| 288 | bool "8KB" |
| 289 | select HAVE_PAGE_SIZE_8KB |
| 290 | help |
| 291 | Choose between 8k vs 16k |
| 292 | |
| 293 | config ARC_PAGE_SIZE_16K |
| 294 | select HAVE_PAGE_SIZE_16KB |
| 295 | bool "16KB" |
| 296 | |
| 297 | config ARC_PAGE_SIZE_4K |
| 298 | bool "4KB" |
| 299 | select HAVE_PAGE_SIZE_4KB |
| 300 | |
| 301 | endchoice |
| 302 | |
| 303 | choice |
| 304 | prompt "MMU Super Page Size" |
| 305 | depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE |
| 306 | default ARC_HUGEPAGE_2M |
| 307 | |
| 308 | config ARC_HUGEPAGE_2M |
| 309 | bool "2MB" |
| 310 | |
| 311 | config ARC_HUGEPAGE_16M |
| 312 | bool "16MB" |
| 313 | |
| 314 | endchoice |
| 315 | |
| 316 | config PGTABLE_LEVELS |
| 317 | int "Number of Page table levels" |
| 318 | default 2 |
| 319 | |
| 320 | config ARC_COMPACT_IRQ_LEVELS |
| 321 | depends on ISA_ARCOMPACT |
| 322 | bool "Setup Timer IRQ as high Priority" |
| 323 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
| 324 | depends on !SMP |
| 325 | |
| 326 | config ARC_FPU_SAVE_RESTORE |
| 327 | bool "Enable FPU state persistence across context switch" |
| 328 | help |
| 329 | ARCompact FPU has internal registers to assist with Double precision |
| 330 | Floating Point operations. There are control and stauts registers |
| 331 | for floating point exceptions and rounding modes. These are |
| 332 | preserved across task context switch when enabled. |
| 333 | |
| 334 | config ARC_HAS_LLSC |
| 335 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" |
| 336 | default y |
| 337 | |
| 338 | if ISA_ARCV2 |
| 339 | |
| 340 | config ARC_USE_UNALIGNED_MEM_ACCESS |
| 341 | bool "Enable unaligned access in HW" |
| 342 | default y |
| 343 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
| 344 | help |
| 345 | The ARC HS architecture supports unaligned memory access |
| 346 | which is disabled by default. Enable unaligned access in |
| 347 | hardware and use software to use it |
| 348 | |
| 349 | config ARC_HAS_LL64 |
| 350 | bool "Insn: 64bit LDD/STD" |
| 351 | help |
| 352 | Enable gcc to generate 64-bit load/store instructions |
| 353 | ISA mandates even/odd registers to allow encoding of two |
| 354 | dest operands with 2 possible source operands. |
| 355 | default y |
| 356 | |
| 357 | config ARC_HAS_DIV_REM |
| 358 | bool "Insn: div, divu, rem, remu" |
| 359 | default y |
| 360 | |
| 361 | config ARC_HAS_ACCL_REGS |
| 362 | bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" |
| 363 | default y |
| 364 | help |
| 365 | Depending on the configuration, CPU can contain accumulator reg-pair |
| 366 | (also referred to as r58:r59). These can also be used by gcc as GPR so |
| 367 | kernel needs to save/restore per process |
| 368 | |
| 369 | config ARC_DSP_HANDLED |
| 370 | def_bool n |
| 371 | |
| 372 | config ARC_DSP_SAVE_RESTORE_REGS |
| 373 | def_bool n |
| 374 | |
| 375 | choice |
| 376 | prompt "DSP support" |
| 377 | default ARC_DSP_NONE |
| 378 | help |
| 379 | Depending on the configuration, CPU can contain DSP registers |
| 380 | (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL). |
| 381 | Below are options describing how to handle these registers in |
| 382 | interrupt entry / exit and in context switch. |
| 383 | |
| 384 | config ARC_DSP_NONE |
| 385 | bool "No DSP extension presence in HW" |
| 386 | help |
| 387 | No DSP extension presence in HW |
| 388 | |
| 389 | config ARC_DSP_KERNEL |
| 390 | bool "DSP extension in HW, no support for userspace" |
| 391 | select ARC_HAS_ACCL_REGS |
| 392 | select ARC_DSP_HANDLED |
| 393 | help |
| 394 | DSP extension presence in HW, no support for DSP-enabled userspace |
| 395 | applications. We don't save / restore DSP registers and only do |
| 396 | some minimal preparations so userspace won't be able to break kernel |
| 397 | |
| 398 | config ARC_DSP_USERSPACE |
| 399 | bool "Support DSP for userspace apps" |
| 400 | select ARC_HAS_ACCL_REGS |
| 401 | select ARC_DSP_HANDLED |
| 402 | select ARC_DSP_SAVE_RESTORE_REGS |
| 403 | help |
| 404 | DSP extension presence in HW, support save / restore DSP registers to |
| 405 | run DSP-enabled userspace applications |
| 406 | |
| 407 | config ARC_DSP_AGU_USERSPACE |
| 408 | bool "Support DSP with AGU for userspace apps" |
| 409 | select ARC_HAS_ACCL_REGS |
| 410 | select ARC_DSP_HANDLED |
| 411 | select ARC_DSP_SAVE_RESTORE_REGS |
| 412 | help |
| 413 | DSP and AGU extensions presence in HW, support save / restore DSP |
| 414 | and AGU registers to run DSP-enabled userspace applications |
| 415 | endchoice |
| 416 | |
| 417 | config ARC_IRQ_NO_AUTOSAVE |
| 418 | bool "Disable hardware autosave regfile on interrupts" |
| 419 | default n |
| 420 | help |
| 421 | On HS cores, taken interrupt auto saves the regfile on stack. |
| 422 | This is programmable and can be optionally disabled in which case |
| 423 | software INTERRUPT_PROLOGUE/EPILGUE do the needed work |
| 424 | |
| 425 | config ARC_LPB_DISABLE |
| 426 | bool "Disable loop buffer (LPB)" |
| 427 | help |
| 428 | On HS cores, loop buffer (LPB) is programmable in runtime and can |
| 429 | be optionally disabled. |
| 430 | |
| 431 | endif # ISA_ARCV2 |
| 432 | |
| 433 | endmenu # "ARC CPU Configuration" |
| 434 | |
| 435 | config LINUX_LINK_BASE |
| 436 | hex "Kernel link address" |
| 437 | default "0x80000000" |
| 438 | help |
| 439 | ARC700 divides the 32 bit phy address space into two equal halves |
| 440 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU |
| 441 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel |
| 442 | Typically Linux kernel is linked at the start of untransalted addr, |
| 443 | hence the default value of 0x8zs. |
| 444 | However some customers have peripherals mapped at this addr, so |
| 445 | Linux needs to be scooted a bit. |
| 446 | If you don't know what the above means, leave this setting alone. |
| 447 | This needs to match memory start address specified in Device Tree |
| 448 | |
| 449 | config LINUX_RAM_BASE |
| 450 | hex "RAM base address" |
| 451 | default LINUX_LINK_BASE |
| 452 | help |
| 453 | By default Linux is linked at base of RAM. However in some special |
| 454 | cases (such as HSDK), Linux can't be linked at start of DDR, hence |
| 455 | this option. |
| 456 | |
| 457 | config HIGHMEM |
| 458 | bool "High Memory Support" |
| 459 | select HAVE_ARCH_PFN_VALID |
| 460 | select KMAP_LOCAL |
| 461 | help |
| 462 | With ARC 2G:2G address split, only upper 2G is directly addressable by |
| 463 | kernel. Enable this to potentially allow access to rest of 2G and PAE |
| 464 | in future |
| 465 | |
| 466 | config ARC_HAS_PAE40 |
| 467 | bool "Support for the 40-bit Physical Address Extension" |
| 468 | depends on ARC_MMU_V4 |
| 469 | depends on !ARC_PAGE_SIZE_4K |
| 470 | select HIGHMEM |
| 471 | select PHYS_ADDR_T_64BIT |
| 472 | help |
| 473 | Enable access to physical memory beyond 4G, only supported on |
| 474 | ARC cores with 40 bit Physical Addressing support |
| 475 | |
| 476 | config ARC_KVADDR_SIZE |
| 477 | int "Kernel Virtual Address Space size (MB)" |
| 478 | range 0 512 |
| 479 | default "256" |
| 480 | help |
| 481 | The kernel address space is carved out of 256MB of translated address |
| 482 | space for catering to vmalloc, modules, pkmap, fixmap. This however may |
| 483 | not suffice vmalloc requirements of a 4K CPU EZChip system. So allow |
| 484 | this to be stretched to 512 MB (by extending into the reserved |
| 485 | kernel-user gutter) |
| 486 | |
| 487 | config ARC_CURR_IN_REG |
| 488 | bool "cache current task pointer in gp" |
| 489 | default y |
| 490 | help |
| 491 | This reserves gp register to point to Current Task in |
| 492 | kernel mode eliding memory access for each access |
| 493 | |
| 494 | |
| 495 | config ARC_EMUL_UNALIGNED |
| 496 | bool "Emulate unaligned memory access (userspace only)" |
| 497 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
| 498 | select SYSCTL_ARCH_UNALIGN_ALLOW |
| 499 | depends on ISA_ARCOMPACT |
| 500 | help |
| 501 | This enables misaligned 16 & 32 bit memory access from user space. |
| 502 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide |
| 503 | potential bugs in code |
| 504 | |
| 505 | config HZ |
| 506 | int "Timer Frequency" |
| 507 | default 100 |
| 508 | |
| 509 | config ARC_METAWARE_HLINK |
| 510 | bool "Support for Metaware debugger assisted Host access" |
| 511 | help |
| 512 | This options allows a Linux userland apps to directly access |
| 513 | host file system (open/creat/read/write etc) with help from |
| 514 | Metaware Debugger. This can come in handy for Linux-host communication |
| 515 | when there is no real usable peripheral such as EMAC. |
| 516 | |
| 517 | menuconfig ARC_DBG |
| 518 | bool "ARC debugging" |
| 519 | default y |
| 520 | |
| 521 | if ARC_DBG |
| 522 | |
| 523 | config ARC_DW2_UNWIND |
| 524 | bool "Enable DWARF specific kernel stack unwind" |
| 525 | default y |
| 526 | select KALLSYMS |
| 527 | help |
| 528 | Compiles the kernel with DWARF unwind information and can be used |
| 529 | to get stack backtraces. |
| 530 | |
| 531 | If you say Y here the resulting kernel image will be slightly larger |
| 532 | but not slower, and it will give very useful debugging information. |
| 533 | If you don't debug the kernel, you can say N, but we may not be able |
| 534 | to solve problems without frame unwind information |
| 535 | |
| 536 | config ARC_DBG_JUMP_LABEL |
| 537 | bool "Paranoid checks in Static Keys (jump labels) code" |
| 538 | depends on JUMP_LABEL |
| 539 | default y if STATIC_KEYS_SELFTEST |
| 540 | help |
| 541 | Enable paranoid checks and self-test of both ARC-specific and generic |
| 542 | part of static keys (jump labels) related code. |
| 543 | endif |
| 544 | |
| 545 | config BUILTIN_DTB_NAME |
| 546 | string "Built in DTB" |
| 547 | default "nsim_700" |
| 548 | help |
| 549 | Set the name of the DTB to embed in the vmlinux binary. |
| 550 | |
| 551 | endmenu # "ARC Architecture Configuration" |
| 552 | |
| 553 | config ARCH_FORCE_MAX_ORDER |
| 554 | int "Maximum zone order" |
| 555 | default "11" if ARC_HUGEPAGE_16M |
| 556 | default "10" |
| 557 | |
| 558 | source "kernel/power/Kconfig" |