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| 2 |
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| 3 | #ifndef _ASM_ARC_ATOMIC_SPLOCK_H
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| 4 | #define _ASM_ARC_ATOMIC_SPLOCK_H
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| 5 |
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| 6 | |
| 7 | * Non hardware assisted Atomic-R-M-W
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| 8 | * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
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| 9 |
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| 10 |
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| 11 | static inline void arch_atomic_set(atomic_t *v, int i)
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| 12 | {
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| 13 | |
| 14 | * Independent of hardware support, all of the atomic_xxx() APIs need
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| 15 | * to follow the same locking rules to make sure that a "hardware"
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| 16 | * atomic insn (e.g. LD) doesn't clobber an "emulated" atomic insn
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| 17 | * sequence
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| 18 | *
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| 19 | * Thus atomic_set() despite being 1 insn (and seemingly atomic)
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| 20 | * requires the locking.
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| 21 |
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| 22 | unsigned long flags;
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| 23 |
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| 24 | atomic_ops_lock(flags);
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| 25 | WRITE_ONCE(v->counter, i);
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| 26 | atomic_ops_unlock(flags);
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| 27 | }
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| 28 |
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| 29 | #define arch_atomic_set_release(v, i) arch_atomic_set((v), (i))
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| 30 |
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| 31 | #define ATOMIC_OP(op, c_op, asm_op) \
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| 32 | static inline void arch_atomic_##op(int i, atomic_t *v) \
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| 33 | { \
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| 34 | unsigned long flags; \
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| 35 | \
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| 36 | atomic_ops_lock(flags); \
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| 37 | v->counter c_op i; \
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| 38 | atomic_ops_unlock(flags); \
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| 39 | }
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| 40 |
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| 41 | #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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| 42 | static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
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| 43 | { \
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| 44 | unsigned long flags; \
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| 45 | unsigned int temp; \
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| 46 | \
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| 47 | |
| 48 | * spin lock/unlock provides the needed smp_mb() before/after \
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| 49 | \
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| 50 | atomic_ops_lock(flags); \
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| 51 | temp = v->counter; \
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| 52 | temp c_op i; \
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| 53 | v->counter = temp; \
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| 54 | atomic_ops_unlock(flags); \
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| 55 | \
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| 56 | return temp; \
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| 57 | }
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| 58 |
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| 59 | #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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| 60 | static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
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| 61 | { \
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| 62 | unsigned long flags; \
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| 63 | unsigned int orig; \
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| 64 | \
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| 65 | |
| 66 | * spin lock/unlock provides the needed smp_mb() before/after \
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| 67 | \
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| 68 | atomic_ops_lock(flags); \
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| 69 | orig = v->counter; \
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| 70 | v->counter c_op i; \
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| 71 | atomic_ops_unlock(flags); \
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| 72 | \
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| 73 | return orig; \
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| 74 | }
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| 75 |
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| 76 | #define ATOMIC_OPS(op, c_op, asm_op) \
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| 77 | ATOMIC_OP(op, c_op, asm_op) \
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| 78 | ATOMIC_OP_RETURN(op, c_op, asm_op) \
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| 79 | ATOMIC_FETCH_OP(op, c_op, asm_op)
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| 80 |
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| 81 | ATOMIC_OPS(add, +=, add)
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| 82 | ATOMIC_OPS(sub, -=, sub)
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| 83 |
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| 84 | #define arch_atomic_fetch_add arch_atomic_fetch_add
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| 85 | #define arch_atomic_fetch_sub arch_atomic_fetch_sub
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| 86 | #define arch_atomic_add_return arch_atomic_add_return
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| 87 | #define arch_atomic_sub_return arch_atomic_sub_return
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| 88 |
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| 89 | #undef ATOMIC_OPS
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| 90 | #define ATOMIC_OPS(op, c_op, asm_op) \
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| 91 | ATOMIC_OP(op, c_op, asm_op) \
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| 92 | ATOMIC_FETCH_OP(op, c_op, asm_op)
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| 93 |
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| 94 | ATOMIC_OPS(and, &=, and)
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| 95 | ATOMIC_OPS(andnot, &= ~, bic)
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| 96 | ATOMIC_OPS(or, |=, or)
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| 97 | ATOMIC_OPS(xor, ^=, xor)
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| 98 |
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| 99 | #define arch_atomic_andnot arch_atomic_andnot
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| 100 |
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| 101 | #define arch_atomic_fetch_and arch_atomic_fetch_and
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| 102 | #define arch_atomic_fetch_andnot arch_atomic_fetch_andnot
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| 103 | #define arch_atomic_fetch_or arch_atomic_fetch_or
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| 104 | #define arch_atomic_fetch_xor arch_atomic_fetch_xor
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| 105 |
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| 106 | #undef ATOMIC_OPS
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| 107 | #undef ATOMIC_FETCH_OP
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| 108 | #undef ATOMIC_OP_RETURN
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| 109 | #undef ATOMIC_OP
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| 110 |
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| 111 | #endif
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