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1# SPDX-License-Identifier: GPL-2.0
2config ARM
3 bool
4 default y
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CACHE_LINE_SIZE if OF
9 select ARCH_HAS_CC_CAN_LINK
10 select ARCH_HAS_CPU_CACHE_ALIASING
11 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
12 select ARCH_HAS_CURRENT_STACK_POINTER
13 select ARCH_HAS_DEBUG_VIRTUAL if MMU
14 select ARCH_HAS_DELAY_TIMER
15 select ARCH_HAS_DMA_ALLOC if MMU
16 select ARCH_HAS_DMA_OPS
17 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
18 select ARCH_HAS_ELF_RANDOMIZE
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_KEEPINITRD
21 select ARCH_HAS_KCOV
22 select ARCH_HAS_MEMBARRIER_SYNC_CORE
23 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
24 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
25 select ARCH_HAS_SETUP_DMA_OPS
26 select ARCH_HAS_SET_MEMORY
27 select ARCH_STACKWALK
28 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
29 select ARCH_HAS_STRICT_MODULE_RWX if MMU
30 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
31 select ARCH_HAS_SYNC_DMA_FOR_CPU
32 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
33 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
34 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
35 select ARCH_HAS_GCOV_PROFILE_ALL
36 select ARCH_KEEP_MEMBLOCK
37 select ARCH_HAS_UBSAN
38 select ARCH_MIGHT_HAVE_PC_PARPORT
39 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
40 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
41 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6
42 select ARCH_SUPPORTS_ATOMIC_RMW
43 select ARCH_SUPPORTS_CFI
44 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
45 select ARCH_SUPPORTS_PER_VMA_LOCK
46 select ARCH_SUPPORTS_RT
47 select ARCH_USE_BUILTIN_BSWAP
48 select ARCH_USE_CMPXCHG_LOCKREF
49 select ARCH_USE_MEMTEST
50 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de
51 select ARCH_USES_CFI_GENERIC_LLVM_PASS if CLANG_VERSION < 220000
52 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
53 select ARCH_WANT_GENERAL_HUGETLB
54 select ARCH_WANT_IPC_PARSE_VERSION
55 select ARCH_WANT_LD_ORPHAN_WARN
56 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
57 select BUILDTIME_TABLE_SORT if MMU
58 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
59 select CLONE_BACKWARDS
60 select CPU_PM if SUSPEND || CPU_IDLE
61 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
62 select DMA_DECLARE_COHERENT
63 select DMA_GLOBAL_POOL if !MMU
64 select DMA_NONCOHERENT_MMAP if MMU
65 select EDAC_SUPPORT
66 select EDAC_ATOMIC_SCRUB
67 select GENERIC_ALLOCATOR
68 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
69 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
70 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
71 select GENERIC_IRQ_IPI if SMP
72 select GENERIC_CPU_AUTOPROBE
73 select GENERIC_CPU_DEVICES
74 select GENERIC_EARLY_IOREMAP
75 select GENERIC_IDLE_POLL_SETUP
76 select GENERIC_IRQ_MULTI_HANDLER
77 select GENERIC_IRQ_PROBE
78 select GENERIC_IRQ_SHOW
79 select GENERIC_IRQ_SHOW_LEVEL
80 select GENERIC_LIB_DEVMEM_IS_ALLOWED
81 select GENERIC_PCI_IOMAP
82 select GENERIC_SCHED_CLOCK
83 select GENERIC_SMP_IDLE_THREAD
84 select HARDIRQS_SW_RESEND
85 select HAS_IOPORT
86 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
87 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 && BITREVERSE
88 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU && (!PREEMPT_RT || !SMP)
89 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
90 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
91 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
92 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
93 select HAVE_ARCH_KSTACK_ERASE
94 select HAVE_ARCH_MMAP_RND_BITS if MMU
95 select HAVE_ARCH_PFN_VALID
96 select HAVE_ARCH_SECCOMP
97 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
98 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
99 select HAVE_ARCH_TRACEHOOK
100 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
101 select HAVE_ARM_SMCCC if CPU_V7
102 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 && !CPU_32v3
103 select HAVE_CONTEXT_TRACKING_USER
104 select HAVE_C_RECORDMCOUNT
105 select HAVE_BUILDTIME_MCOUNT_SORT
106 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
107 select HAVE_DMA_CONTIGUOUS if MMU
108 select HAVE_EXTRA_IPI_TRACEPOINTS
109 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
110 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
111 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
112 select HAVE_EXIT_THREAD
113 select HAVE_GUP_FAST if ARM_LPAE
114 select HAVE_FUNCTION_ERROR_INJECTION
115 select HAVE_FUNCTION_GRAPH_TRACER
116 select HAVE_FUNCTION_GRAPH_FREGS
117 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
118 select HAVE_GCC_PLUGINS
119 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
120 select HAVE_IRQ_TIME_ACCOUNTING
121 select HAVE_KERNEL_GZIP
122 select HAVE_KERNEL_LZ4
123 select HAVE_KERNEL_LZMA
124 select HAVE_KERNEL_LZO
125 select HAVE_KERNEL_XZ
126 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
127 select HAVE_KRETPROBES if HAVE_KPROBES
128 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) && LD_CAN_USE_KEEP_IN_OVERLAY
129 select HAVE_MOD_ARCH_SPECIFIC
130 select HAVE_NMI
131 select HAVE_OPTPROBES if !THUMB2_KERNEL
132 select HAVE_PAGE_SIZE_4KB
133 select HAVE_PCI if MMU
134 select HAVE_PERF_EVENTS
135 select HAVE_PERF_REGS
136 select HAVE_PERF_USER_STACK_DUMP
137 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
138 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
139 select HAVE_REGS_AND_STACK_ACCESS_API
140 select HAVE_RSEQ
141 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 && !KASAN
142 select HAVE_STACKPROTECTOR
143 select HAVE_SYSCALL_TRACEPOINTS
144 select HAVE_UID16
145 select HAVE_VIRT_CPU_ACCOUNTING_GEN
146 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
147 select IRQ_FORCED_THREADING
148 select LOCK_MM_AND_FIND_VMA
149 select MODULES_USE_ELF_REL
150 select NEED_DMA_MAP_STATE
151 select OF_EARLY_FLATTREE if OF
152 select OLD_SIGACTION
153 select OLD_SIGSUSPEND3
154 select PCI_DOMAINS_GENERIC if PCI
155 select PCI_SYSCALL if PCI
156 select PERF_USE_VMALLOC
157 select RTC_LIB
158 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
159 select SYS_SUPPORTS_APM_EMULATION
160 select THREAD_INFO_IN_TASK
161 select TIMER_OF if OF
162 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
163 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
164 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
165 # Above selects are sorted alphabetically; please add new ones
166 # according to that. Thanks.
167 help
168 The ARM series is a line of low-power-consumption RISC chip designs
169 licensed by ARM Ltd and targeted at embedded applications and
170 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
171 manufactured, but legacy ARM-based PC hardware remains popular in
172 Europe. There is an ARM Linux project with a web page at
173 <http://www.arm.linux.org.uk/>.
174
175config ARM_HAS_GROUP_RELOCS
176 def_bool !COMPILE_TEST
177 help
178 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
179 relocations. The combined range is -/+ 256 MiB, which is usually
180 sufficient, but not for allyesconfig, so we disable this feature
181 when doing compile testing.
182
183config ARM_DMA_USE_IOMMU
184 bool
185 select NEED_SG_DMA_LENGTH
186
187if ARM_DMA_USE_IOMMU
188
189config ARM_DMA_IOMMU_ALIGNMENT
190 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
191 range 4 9
192 default 8
193 help
194 DMA mapping framework by default aligns all buffers to the smallest
195 PAGE_SIZE order which is greater than or equal to the requested buffer
196 size. This works well for buffers up to a few hundreds kilobytes, but
197 for larger buffers it just a waste of address space. Drivers which has
198 relatively small addressing window (like 64Mib) might run out of
199 virtual space with just a few allocations.
200
201 With this parameter you can specify the maximum PAGE_SIZE order for
202 DMA IOMMU buffers. Larger buffers will be aligned only to this
203 specified order. The order is expressed as a power of two multiplied
204 by the PAGE_SIZE.
205
206endif
207
208config SYS_SUPPORTS_APM_EMULATION
209 bool
210
211config HAVE_TCM
212 bool
213 select GENERIC_ALLOCATOR
214
215config HAVE_PROC_CPU
216 bool
217
218config NO_IOPORT_MAP
219 bool
220
221config SBUS
222 bool
223
224config STACKTRACE_SUPPORT
225 bool
226 default y
227
228config LOCKDEP_SUPPORT
229 bool
230 default y
231
232config ARCH_HAS_ILOG2_U32
233 bool
234
235config ARCH_HAS_ILOG2_U64
236 bool
237
238config ARCH_HAS_BANDGAP
239 bool
240
241config FIX_EARLYCON_MEM
242 def_bool y if MMU
243
244config GENERIC_HWEIGHT
245 bool
246 default y
247
248config GENERIC_CALIBRATE_DELAY
249 bool
250 default y
251
252config ARCH_MAY_HAVE_PC_FDC
253 bool
254
255config ARCH_SUPPORTS_UPROBES
256 def_bool y
257
258config GENERIC_ISA_DMA
259 bool
260
261config FIQ
262 bool
263
264config ARCH_MTD_XIP
265 bool
266
267config ARM_PATCH_PHYS_VIRT
268 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM
269 default y
270 depends on MMU
271 help
272 Patch phys-to-virt and virt-to-phys translation functions at
273 boot and module load time according to the position of the
274 kernel in system memory.
275
276 This can only be used with non-XIP MMU kernels where the base
277 of physical memory is at a 2 MiB boundary.
278
279 Only disable this option if you know that you do not require
280 this feature (eg, building a kernel for a single machine) and
281 you need to shrink the kernel to the minimal size.
282
283config NEED_MACH_IO_H
284 bool
285 help
286 Select this when mach/io.h is required to provide special
287 definitions for this platform. The need for mach/io.h should
288 be avoided when possible.
289
290config NEED_MACH_MEMORY_H
291 bool
292 help
293 Select this when mach/memory.h is required to provide special
294 definitions for this platform. The need for mach/memory.h should
295 be avoided when possible.
296
297config PHYS_OFFSET
298 hex "Physical address of main memory" if MMU
299 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
300 default DRAM_BASE if !MMU
301 default 0x00000000 if ARCH_FOOTBRIDGE
302 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
303 default 0xa0000000 if ARCH_PXA
304 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
305 default 0
306 help
307 Please provide the physical address corresponding to the
308 location of main memory in your system.
309
310config GENERIC_BUG
311 def_bool y
312 depends on BUG
313
314config PGTABLE_LEVELS
315 int
316 default 3 if ARM_LPAE
317 default 2
318
319menu "System Type"
320
321config MMU
322 bool "MMU-based Paged Memory Management Support"
323 default y
324 help
325 Select if you want MMU-based virtualised addressing space
326 support by paged memory management. If unsure, say 'Y'.
327
328config ARM_SINGLE_ARMV7M
329 def_bool !MMU
330 select ARM_NVIC
331 select CPU_V7M
332 select NO_IOPORT_MAP
333
334config ARCH_MMAP_RND_BITS_MIN
335 default 8
336
337config ARCH_MMAP_RND_BITS_MAX
338 default 14 if PAGE_OFFSET=0x40000000
339 default 15 if PAGE_OFFSET=0x80000000
340 default 16
341
342config ARCH_MULTIPLATFORM
343 bool "Require kernel to be portable to multiple machines" if EXPERT
344 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
345 default y
346 help
347 In general, all Arm machines can be supported in a single
348 kernel image, covering either Armv4/v5 or Armv6/v7.
349
350 However, some configuration options require hardcoding machine
351 specific physical addresses or enable errata workarounds that may
352 break other machines.
353
354 Selecting N here allows using those options, including
355 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
356
357source "arch/arm/Kconfig.platforms"
358
359#
360# This is sorted alphabetically by mach-* pathname. However, plat-*
361# Kconfigs may be included either alphabetically (according to the
362# plat- suffix) or along side the corresponding mach-* source.
363#
364source "arch/arm/mach-actions/Kconfig"
365
366source "arch/arm/mach-alpine/Kconfig"
367
368source "arch/arm/mach-artpec/Kconfig"
369
370source "arch/arm/mach-aspeed/Kconfig"
371
372source "arch/arm/mach-at91/Kconfig"
373
374source "arch/arm/mach-axxia/Kconfig"
375
376source "arch/arm/mach-bcm/Kconfig"
377
378source "arch/arm/mach-berlin/Kconfig"
379
380source "arch/arm/mach-clps711x/Kconfig"
381
382source "arch/arm/mach-davinci/Kconfig"
383
384source "arch/arm/mach-digicolor/Kconfig"
385
386source "arch/arm/mach-dove/Kconfig"
387
388source "arch/arm/mach-ep93xx/Kconfig"
389
390source "arch/arm/mach-exynos/Kconfig"
391
392source "arch/arm/mach-footbridge/Kconfig"
393
394source "arch/arm/mach-gemini/Kconfig"
395
396source "arch/arm/mach-highbank/Kconfig"
397
398source "arch/arm/mach-hisi/Kconfig"
399
400source "arch/arm/mach-imx/Kconfig"
401
402source "arch/arm/mach-ixp4xx/Kconfig"
403
404source "arch/arm/mach-keystone/Kconfig"
405
406source "arch/arm/mach-lpc32xx/Kconfig"
407
408source "arch/arm/mach-mediatek/Kconfig"
409
410source "arch/arm/mach-meson/Kconfig"
411
412source "arch/arm/mach-milbeaut/Kconfig"
413
414source "arch/arm/mach-mmp/Kconfig"
415
416source "arch/arm/mach-mstar/Kconfig"
417
418source "arch/arm/mach-mv78xx0/Kconfig"
419
420source "arch/arm/mach-mvebu/Kconfig"
421
422source "arch/arm/mach-mxs/Kconfig"
423
424source "arch/arm/mach-nomadik/Kconfig"
425
426source "arch/arm/mach-npcm/Kconfig"
427
428source "arch/arm/mach-omap1/Kconfig"
429
430source "arch/arm/mach-omap2/Kconfig"
431
432source "arch/arm/mach-orion5x/Kconfig"
433
434source "arch/arm/mach-pxa/Kconfig"
435
436source "arch/arm/mach-qcom/Kconfig"
437
438source "arch/arm/mach-realtek/Kconfig"
439
440source "arch/arm/mach-rpc/Kconfig"
441
442source "arch/arm/mach-rockchip/Kconfig"
443
444source "arch/arm/mach-s3c/Kconfig"
445
446source "arch/arm/mach-s5pv210/Kconfig"
447
448source "arch/arm/mach-sa1100/Kconfig"
449
450source "arch/arm/mach-shmobile/Kconfig"
451
452source "arch/arm/mach-socfpga/Kconfig"
453
454source "arch/arm/mach-spear/Kconfig"
455
456source "arch/arm/mach-sti/Kconfig"
457
458source "arch/arm/mach-stm32/Kconfig"
459
460source "arch/arm/mach-sunxi/Kconfig"
461
462source "arch/arm/mach-tegra/Kconfig"
463
464source "arch/arm/mach-ux500/Kconfig"
465
466source "arch/arm/mach-versatile/Kconfig"
467
468source "arch/arm/mach-vt8500/Kconfig"
469
470source "arch/arm/mach-zte/Kconfig"
471
472source "arch/arm/mach-zynq/Kconfig"
473
474# ARMv7-M architecture
475config ARCH_LPC18XX
476 bool "NXP LPC18xx/LPC43xx (DEPRECATED)"
477 depends on ARM_SINGLE_ARMV7M
478 select ARCH_HAS_RESET_CONTROLLER
479 select ARM_AMBA
480 select CLKSRC_LPC32XX
481 select PINCTRL
482 help
483 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
484 high performance microcontrollers.
485
486 This platform is scheduled for removal in early 2027
487
488config ARCH_MPS2
489 bool "ARM MPS2 platform (DEPRECATED)"
490 depends on ARM_SINGLE_ARMV7M
491 select ARM_AMBA
492 select CLKSRC_MPS2
493 help
494 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
495 with a range of available cores like Cortex-M3/M4/M7.
496
497 Please, note that depends which Application Note is used memory map
498 for the platform may vary, so adjustment of RAM base might be needed.
499
500 This platform is scheduled for removal in early 2027
501
502# Definitions to make life easier
503config ARCH_ACORN
504 bool
505
506config PLAT_ORION
507 bool
508 select CLKSRC_MMIO
509 select GENERIC_IRQ_CHIP
510 select IRQ_DOMAIN
511
512config PLAT_ORION_LEGACY
513 bool
514 select PLAT_ORION
515
516config PLAT_VERSATILE
517 bool
518
519source "arch/arm/mm/Kconfig"
520
521config IWMMXT
522 bool "Enable iWMMXt support (DEPRECATED)"
523 depends on PXA27x || PXA3xx || ARCH_MMP
524 help
525 Enable support for iWMMXt context switching at run time if
526 running on a CPU that supports it.
527
528 Machines that actually support this feature are very rare,
529 and support is deprecated in new gcc-14. While there were a
530 few applications that used this in the past, none are known
531 to still do so.
532
533 If you use this, please send a patch to remove the
534 deprecation, otherwise this will be removed in early
535 2027.
536
537if !MMU
538source "arch/arm/Kconfig-nommu"
539endif
540
541config PJ4B_ERRATA_4742
542 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
543 depends on CPU_PJ4B && MACH_ARMADA_370
544 default y
545 help
546 When coming out of either a Wait for Interrupt (WFI) or a Wait for
547 Event (WFE) IDLE states, a specific timing sensitivity exists between
548 the retiring WFI/WFE instructions and the newly issued subsequent
549 instructions. This sensitivity can result in a CPU hang scenario.
550 Workaround:
551 The software must insert either a Data Synchronization Barrier (DSB)
552 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
553 instruction
554
555config ARM_ERRATA_326103
556 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
557 depends on CPU_V6
558 help
559 Executing a SWP instruction to read-only memory does not set bit 11
560 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
561 treat the access as a read, preventing a COW from occurring and
562 causing the faulting task to livelock.
563
564config ARM_ERRATA_411920
565 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
566 depends on CPU_V6 || CPU_V6K
567 help
568 Invalidation of the Instruction Cache operation can
569 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
570 It does not affect the MPCore. This option enables the ARM Ltd.
571 recommended workaround.
572
573config ARM_ERRATA_430973
574 bool "ARM errata: Stale prediction on replaced interworking branch"
575 depends on CPU_V7
576 help
577 This option enables the workaround for the 430973 Cortex-A8
578 r1p* erratum. If a code sequence containing an ARM/Thumb
579 interworking branch is replaced with another code sequence at the
580 same virtual address, whether due to self-modifying code or virtual
581 to physical address re-mapping, Cortex-A8 does not recover from the
582 stale interworking branch prediction. This results in Cortex-A8
583 executing the new code sequence in the incorrect ARM or Thumb state.
584 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
585 and also flushes the branch target cache at every context switch.
586 Note that setting specific bits in the ACTLR register may not be
587 available in non-secure mode.
588
589config ARM_ERRATA_458693
590 bool "ARM errata: Processor deadlock when a false hazard is created"
591 depends on CPU_V7
592 depends on !ARCH_MULTIPLATFORM
593 help
594 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
595 erratum. For very specific sequences of memory operations, it is
596 possible for a hazard condition intended for a cache line to instead
597 be incorrectly associated with a different cache line. This false
598 hazard might then cause a processor deadlock. The workaround enables
599 the L1 caching of the NEON accesses and disables the PLD instruction
600 in the ACTLR register. Note that setting specific bits in the ACTLR
601 register may not be available in non-secure mode and thus is not
602 available on a multiplatform kernel. This should be applied by the
603 bootloader instead.
604
605config ARM_ERRATA_460075
606 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
607 depends on CPU_V7
608 depends on !ARCH_MULTIPLATFORM
609 help
610 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
611 erratum. Any asynchronous access to the L2 cache may encounter a
612 situation in which recent store transactions to the L2 cache are lost
613 and overwritten with stale memory contents from external memory. The
614 workaround disables the write-allocate mode for the L2 cache via the
615 ACTLR register. Note that setting specific bits in the ACTLR register
616 may not be available in non-secure mode and thus is not available on
617 a multiplatform kernel. This should be applied by the bootloader
618 instead.
619
620config ARM_ERRATA_742230
621 bool "ARM errata: DMB operation may be faulty"
622 depends on CPU_V7 && SMP
623 depends on !ARCH_MULTIPLATFORM
624 help
625 This option enables the workaround for the 742230 Cortex-A9
626 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
627 between two write operations may not ensure the correct visibility
628 ordering of the two writes. This workaround sets a specific bit in
629 the diagnostic register of the Cortex-A9 which causes the DMB
630 instruction to behave as a DSB, ensuring the correct behaviour of
631 the two writes. Note that setting specific bits in the diagnostics
632 register may not be available in non-secure mode and thus is not
633 available on a multiplatform kernel. This should be applied by the
634 bootloader instead.
635
636config ARM_ERRATA_742231
637 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
638 depends on CPU_V7 && SMP
639 depends on !ARCH_MULTIPLATFORM
640 help
641 This option enables the workaround for the 742231 Cortex-A9
642 (r2p0..r2p2) erratum. Under certain conditions, specific to the
643 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
644 accessing some data located in the same cache line, may get corrupted
645 data due to bad handling of the address hazard when the line gets
646 replaced from one of the CPUs at the same time as another CPU is
647 accessing it. This workaround sets specific bits in the diagnostic
648 register of the Cortex-A9 which reduces the linefill issuing
649 capabilities of the processor. Note that setting specific bits in the
650 diagnostics register may not be available in non-secure mode and thus
651 is not available on a multiplatform kernel. This should be applied by
652 the bootloader instead.
653
654config ARM_ERRATA_643719
655 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
656 depends on CPU_V7 && SMP
657 default y
658 help
659 This option enables the workaround for the 643719 Cortex-A9 (prior to
660 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
661 register returns zero when it should return one. The workaround
662 corrects this value, ensuring cache maintenance operations which use
663 it behave as intended and avoiding data corruption.
664
665config ARM_ERRATA_720789
666 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
667 depends on CPU_V7
668 help
669 This option enables the workaround for the 720789 Cortex-A9 (prior to
670 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
671 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
672 As a consequence of this erratum, some TLB entries which should be
673 invalidated are not, resulting in an incoherency in the system page
674 tables. The workaround changes the TLB flushing routines to invalidate
675 entries regardless of the ASID.
676
677config ARM_ERRATA_743622
678 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
679 depends on CPU_V7
680 depends on !ARCH_MULTIPLATFORM
681 help
682 This option enables the workaround for the 743622 Cortex-A9
683 (r2p*) erratum. Under very rare conditions, a faulty
684 optimisation in the Cortex-A9 Store Buffer may lead to data
685 corruption. This workaround sets a specific bit in the diagnostic
686 register of the Cortex-A9 which disables the Store Buffer
687 optimisation, preventing the defect from occurring. This has no
688 visible impact on the overall performance or power consumption of the
689 processor. Note that setting specific bits in the diagnostics register
690 may not be available in non-secure mode and thus is not available on a
691 multiplatform kernel. This should be applied by the bootloader instead.
692
693config ARM_ERRATA_751472
694 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
695 depends on CPU_V7
696 depends on !ARCH_MULTIPLATFORM
697 help
698 This option enables the workaround for the 751472 Cortex-A9 (prior
699 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
700 completion of a following broadcasted operation if the second
701 operation is received by a CPU before the ICIALLUIS has completed,
702 potentially leading to corrupted entries in the cache or TLB.
703 Note that setting specific bits in the diagnostics register may
704 not be available in non-secure mode and thus is not available on
705 a multiplatform kernel. This should be applied by the bootloader
706 instead.
707
708config ARM_ERRATA_754322
709 bool "ARM errata: possible faulty MMU translations following an ASID switch"
710 depends on CPU_V7
711 help
712 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
713 r3p*) erratum. A speculative memory access may cause a page table walk
714 which starts prior to an ASID switch but completes afterwards. This
715 can populate the micro-TLB with a stale entry which may be hit with
716 the new ASID. This workaround places two dsb instructions in the mm
717 switching code so that no page table walks can cross the ASID switch.
718
719config ARM_ERRATA_754327
720 bool "ARM errata: no automatic Store Buffer drain"
721 depends on CPU_V7 && SMP
722 help
723 This option enables the workaround for the 754327 Cortex-A9 (prior to
724 r2p0) erratum. The Store Buffer does not have any automatic draining
725 mechanism and therefore a livelock may occur if an external agent
726 continuously polls a memory location waiting to observe an update.
727 This workaround defines cpu_relax() as smp_mb(), preventing correctly
728 written polling loops from denying visibility of updates to memory.
729
730config ARM_ERRATA_364296
731 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
732 depends on CPU_V6
733 help
734 This options enables the workaround for the 364296 ARM1136
735 r0p2 erratum (possible cache data corruption with
736 hit-under-miss enabled). It sets the undocumented bit 31 in
737 the auxiliary control register and the FI bit in the control
738 register, thus disabling hit-under-miss without putting the
739 processor into full low interrupt latency mode. ARM11MPCore
740 is not affected.
741
742config ARM_ERRATA_764369
743 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
744 depends on CPU_V7 && SMP
745 help
746 This option enables the workaround for erratum 764369
747 affecting Cortex-A9 MPCore with two or more processors (all
748 current revisions). Under certain timing circumstances, a data
749 cache line maintenance operation by MVA targeting an Inner
750 Shareable memory region may fail to proceed up to either the
751 Point of Coherency or to the Point of Unification of the
752 system. This workaround adds a DSB instruction before the
753 relevant cache maintenance functions and sets a specific bit
754 in the diagnostic control register of the SCU.
755
756config ARM_ERRATA_764319
757 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
758 depends on CPU_V7
759 help
760 This option enables the workaround for the 764319 Cortex-A9 erratum.
761 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
762 unexpected Undefined Instruction exception when the DBGSWENABLE
763 external pin is set to 0, even when the CP14 accesses are performed
764 from a privileged mode. This work around catches the exception in a
765 way the kernel does not stop execution.
766
767config ARM_ERRATA_775420
768 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
769 depends on CPU_V7
770 help
771 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
772 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
773 operation aborts with MMU exception, it might cause the processor
774 to deadlock. This workaround puts DSB before executing ISB if
775 an abort may occur on cache maintenance.
776
777config ARM_ERRATA_798181
778 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
779 depends on CPU_V7 && SMP
780 help
781 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
782 adequately shooting down all use of the old entries. This
783 option enables the Linux kernel workaround for this erratum
784 which sends an IPI to the CPUs that are running the same ASID
785 as the one being invalidated.
786
787config ARM_ERRATA_773022
788 bool "ARM errata: incorrect instructions may be executed from loop buffer"
789 depends on CPU_V7
790 help
791 This option enables the workaround for the 773022 Cortex-A15
792 (up to r0p4) erratum. In certain rare sequences of code, the
793 loop buffer may deliver incorrect instructions. This
794 workaround disables the loop buffer to avoid the erratum.
795
796config ARM_ERRATA_818325_852422
797 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
798 depends on CPU_V7
799 help
800 This option enables the workaround for:
801 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
802 instruction might deadlock. Fixed in r0p1.
803 - Cortex-A12 852422: Execution of a sequence of instructions might
804 lead to either a data corruption or a CPU deadlock. Not fixed in
805 any Cortex-A12 cores yet.
806 This workaround for all both errata involves setting bit[12] of the
807 Feature Register. This bit disables an optimisation applied to a
808 sequence of 2 instructions that use opposing condition codes.
809
810config ARM_ERRATA_821420
811 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
812 depends on CPU_V7
813 help
814 This option enables the workaround for the 821420 Cortex-A12
815 (all revs) erratum. In very rare timing conditions, a sequence
816 of VMOV to Core registers instructions, for which the second
817 one is in the shadow of a branch or abort, can lead to a
818 deadlock when the VMOV instructions are issued out-of-order.
819
820config ARM_ERRATA_825619
821 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
822 depends on CPU_V7
823 help
824 This option enables the workaround for the 825619 Cortex-A12
825 (all revs) erratum. Within rare timing constraints, executing a
826 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
827 and Device/Strongly-Ordered loads and stores might cause deadlock
828
829config ARM_ERRATA_857271
830 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
831 depends on CPU_V7
832 help
833 This option enables the workaround for the 857271 Cortex-A12
834 (all revs) erratum. Under very rare timing conditions, the CPU might
835 hang. The workaround is expected to have a < 1% performance impact.
836
837config ARM_ERRATA_852421
838 bool "ARM errata: A17: DMB ST might fail to create order between stores"
839 depends on CPU_V7
840 help
841 This option enables the workaround for the 852421 Cortex-A17
842 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
843 execution of a DMB ST instruction might fail to properly order
844 stores from GroupA and stores from GroupB.
845
846config ARM_ERRATA_852423
847 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
848 depends on CPU_V7
849 help
850 This option enables the workaround for:
851 - Cortex-A17 852423: Execution of a sequence of instructions might
852 lead to either a data corruption or a CPU deadlock. Not fixed in
853 any Cortex-A17 cores yet.
854 This is identical to Cortex-A12 erratum 852422. It is a separate
855 config option from the A12 erratum due to the way errata are checked
856 for and handled.
857
858config ARM_ERRATA_857272
859 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
860 depends on CPU_V7
861 help
862 This option enables the workaround for the 857272 Cortex-A17 erratum.
863 This erratum is not known to be fixed in any A17 revision.
864 This is identical to Cortex-A12 erratum 857271. It is a separate
865 config option from the A12 erratum due to the way errata are checked
866 for and handled.
867
868endmenu
869
870source "arch/arm/common/Kconfig"
871
872menu "Bus support"
873
874config ISA
875 bool
876 help
877 Find out whether you have ISA slots on your motherboard. ISA is the
878 name of a bus system, i.e. the way the CPU talks to the other stuff
879 inside your box. Other bus systems are PCI, EISA, MicroChannel
880 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
881 newer boards don't support it. If you have ISA, say Y, otherwise N.
882
883# Select ISA DMA interface
884config ISA_DMA_API
885 bool
886
887config ARM_ERRATA_814220
888 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
889 depends on CPU_V7
890 help
891 The v7 ARM states that all cache and branch predictor maintenance
892 operations that do not specify an address execute, relative to
893 each other, in program order.
894 However, because of this erratum, an L2 set/way cache maintenance
895 operation can overtake an L1 set/way cache maintenance operation.
896 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
897 r0p4, r0p5.
898
899endmenu
900
901menu "Kernel Features"
902
903config HAVE_SMP
904 bool
905 help
906 This option should be selected by machines which have an SMP-
907 capable CPU.
908
909 The only effect of this option is to make the SMP-related
910 options available to the user for configuration.
911
912config SMP
913 bool "Symmetric Multi-Processing"
914 depends on CPU_V6K || CPU_V7
915 depends on HAVE_SMP
916 depends on MMU || ARM_MPU
917 select IRQ_WORK
918 help
919 This enables support for systems with more than one CPU. If you have
920 a system with only one CPU, say N. If you have a system with more
921 than one CPU, say Y.
922
923 If you say N here, the kernel will run on uni- and multiprocessor
924 machines, but will use only one CPU of a multiprocessor machine. If
925 you say Y here, the kernel will run on many, but not all,
926 uniprocessor machines. On a uniprocessor machine, the kernel
927 will run faster if you say N here.
928
929 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
930 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
931 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
932
933 If you don't know what to do here, say N.
934
935config SMP_ON_UP
936 bool "Allow booting SMP kernel on uniprocessor systems"
937 depends on SMP && MMU
938 default y
939 help
940 SMP kernels contain instructions which fail on non-SMP processors.
941 Enabling this option allows the kernel to modify itself to make
942 these instructions safe. Disabling it allows about 1K of space
943 savings.
944
945 If you don't know what to do here, say Y.
946
947
948config CURRENT_POINTER_IN_TPIDRURO
949 def_bool y
950 depends on CPU_32v6K && !CPU_V6
951
952config IRQSTACKS
953 def_bool y
954 select HAVE_IRQ_EXIT_ON_IRQ_STACK
955 select HAVE_SOFTIRQ_ON_OWN_STACK
956
957config ARM_CPU_TOPOLOGY
958 bool "Support cpu topology definition"
959 depends on SMP && CPU_V7
960 select ARCH_SUPPORTS_SCHED_MC
961 select ARCH_SUPPORTS_SCHED_SMT
962 default y
963 help
964 Support ARM cpu topology definition. The MPIDR register defines
965 affinity between processors which is then used to describe the cpu
966 topology of an ARM System.
967
968config HAVE_ARM_SCU
969 bool
970 help
971 This option enables support for the ARM snoop control unit
972
973config HAVE_ARM_ARCH_TIMER
974 bool "Architected timer support"
975 depends on CPU_V7
976 select ARM_ARCH_TIMER
977 help
978 This option enables support for the ARM architected timer
979
980config HAVE_ARM_TWD
981 bool
982 help
983 This options enables support for the ARM timer and watchdog unit
984
985config MCPM
986 bool "Multi-Cluster Power Management"
987 depends on CPU_V7 && SMP
988 help
989 This option provides the common power management infrastructure
990 for (multi-)cluster based systems, such as big.LITTLE based
991 systems.
992
993config MCPM_QUAD_CLUSTER
994 bool
995 depends on MCPM
996 help
997 To avoid wasting resources unnecessarily, MCPM only supports up
998 to 2 clusters by default.
999 Platforms with 3 or 4 clusters that use MCPM must select this
1000 option to allow the additional clusters to be managed.
1001
1002config BIG_LITTLE
1003 bool "big.LITTLE support (Experimental)"
1004 depends on CPU_V7 && SMP
1005 select MCPM
1006 help
1007 This option enables support selections for the big.LITTLE
1008 system architecture.
1009
1010config BL_SWITCHER
1011 bool "big.LITTLE switcher support"
1012 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1013 select CPU_PM
1014 help
1015 The big.LITTLE "switcher" provides the core functionality to
1016 transparently handle transition between a cluster of A15's
1017 and a cluster of A7's in a big.LITTLE system.
1018
1019config BL_SWITCHER_DUMMY_IF
1020 tristate "Simple big.LITTLE switcher user interface"
1021 depends on BL_SWITCHER && DEBUG_KERNEL
1022 help
1023 This is a simple and dummy char dev interface to control
1024 the big.LITTLE switcher core code. It is meant for
1025 debugging purposes only.
1026
1027choice
1028 prompt "Memory split"
1029 depends on MMU
1030 default VMSPLIT_3G
1031 help
1032 Select the desired split between kernel and user memory.
1033
1034 If you are not absolutely sure what you are doing, leave this
1035 option alone!
1036
1037 config VMSPLIT_3G
1038 bool "3G/1G user/kernel split"
1039 config VMSPLIT_3G_OPT
1040 depends on !ARM_LPAE
1041 bool "3G/1G user/kernel split (for full 1G low memory)"
1042 config VMSPLIT_2G
1043 bool "2G/2G user/kernel split"
1044 config VMSPLIT_1G
1045 bool "1G/3G user/kernel split"
1046endchoice
1047
1048config PAGE_OFFSET
1049 hex
1050 default PHYS_OFFSET if !MMU
1051 default 0x40000000 if VMSPLIT_1G
1052 default 0x80000000 if VMSPLIT_2G
1053 default 0xB0000000 if VMSPLIT_3G_OPT
1054 default 0xC0000000
1055
1056config KASAN_SHADOW_OFFSET
1057 hex
1058 depends on KASAN
1059 default 0x1f000000 if PAGE_OFFSET=0x40000000
1060 default 0x5f000000 if PAGE_OFFSET=0x80000000
1061 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1062 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1063 default 0xffffffff
1064
1065config NR_CPUS
1066 int "Maximum number of CPUs (2-32)"
1067 range 2 16 if DEBUG_KMAP_LOCAL
1068 range 2 32 if !DEBUG_KMAP_LOCAL
1069 depends on SMP
1070 default "4"
1071 help
1072 The maximum number of CPUs that the kernel can support.
1073 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1074 debugging is enabled, which uses half of the per-CPU fixmap
1075 slots as guard regions.
1076
1077config HOTPLUG_CPU
1078 bool "Support for hot-pluggable CPUs"
1079 depends on SMP
1080 select GENERIC_IRQ_MIGRATION
1081 help
1082 Say Y here to experiment with turning CPUs off and on. CPUs
1083 can be controlled through /sys/devices/system/cpu.
1084
1085config ARM_PSCI
1086 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1087 depends on HAVE_ARM_SMCCC
1088 select ARM_PSCI_FW
1089 help
1090 Say Y here if you want Linux to communicate with system firmware
1091 implementing the PSCI specification for CPU-centric power
1092 management operations described in ARM document number ARM DEN
1093 0022A ("Power State Coordination Interface System Software on
1094 ARM processors").
1095
1096config HZ_FIXED
1097 int
1098 default 128 if SOC_AT91RM9200
1099 default 0
1100
1101choice
1102 depends on HZ_FIXED = 0
1103 prompt "Timer frequency"
1104
1105config HZ_100
1106 bool "100 Hz"
1107
1108config HZ_200
1109 bool "200 Hz"
1110
1111config HZ_250
1112 bool "250 Hz"
1113
1114config HZ_300
1115 bool "300 Hz"
1116
1117config HZ_500
1118 bool "500 Hz"
1119
1120config HZ_1000
1121 bool "1000 Hz"
1122
1123endchoice
1124
1125config HZ
1126 int
1127 default HZ_FIXED if HZ_FIXED != 0
1128 default 100 if HZ_100
1129 default 200 if HZ_200
1130 default 250 if HZ_250
1131 default 300 if HZ_300
1132 default 500 if HZ_500
1133 default 1000
1134
1135config SCHED_HRTICK
1136 def_bool HIGH_RES_TIMERS
1137
1138config THUMB2_KERNEL
1139 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1140 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1141 default y if CPU_THUMBONLY
1142 select ARM_UNWIND
1143 help
1144 By enabling this option, the kernel will be compiled in
1145 Thumb-2 mode.
1146
1147 If unsure, say N.
1148
1149config ARM_PATCH_IDIV
1150 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1151 depends on CPU_32v7
1152 default y
1153 help
1154 The ARM compiler inserts calls to __aeabi_idiv() and
1155 __aeabi_uidiv() when it needs to perform division on signed
1156 and unsigned integers. Some v7 CPUs have support for the sdiv
1157 and udiv instructions that can be used to implement those
1158 functions.
1159
1160 Enabling this option allows the kernel to modify itself to
1161 replace the first two instructions of these library functions
1162 with the sdiv or udiv plus "bx lr" instructions when the CPU
1163 it is running on supports them. Typically this will be faster
1164 and less power intensive than running the original library
1165 code to do integer division.
1166
1167config AEABI
1168 bool "Use the ARM EABI to compile the kernel" if CPU_SA110 || CPU_SA1100
1169 default y
1170 help
1171 The Arm EABI is the default ABI on all modern Linux
1172 distributions, replacing the obsolete and "OABI" that was
1173 commonly used on ARMv4 distributions before ca. 2013.
1174
1175 Everyone should enable this, as support for OABI user space
1176 was dropped in gcc-4.8 and most distributions after ca. 2013.
1177
1178 Support for OABI mode will be removed from the kernel
1179 once Intel StrongARM CPUs are phased out.
1180
1181config OABI_COMPAT
1182 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1183 depends on AEABI && !THUMB2_KERNEL
1184 depends on CPU_SA110 || CPU_SA1100
1185 help
1186 This option preserves the old syscall interface along with the
1187 new (ARM EABI) one. It also provides a compatibility layer to
1188 intercept syscalls that have structure arguments which layout
1189 in memory differs between the legacy ABI and the new ARM EABI
1190 (only for non "thumb" binaries). This option adds a tiny
1191 overhead to all syscalls and produces a slightly larger kernel.
1192
1193 The seccomp filter system will not be available when this is
1194 selected, since there is no way yet to sensibly distinguish
1195 between calling conventions during filtering.
1196
1197 Support for OABI_COMPAT will be removed from the kernel
1198 once Intel StrongARM CPUs are phased out.
1199
1200config ARCH_SELECT_MEMORY_MODEL
1201 def_bool y
1202
1203config ARCH_FLATMEM_ENABLE
1204 def_bool !(ARCH_RPC || ARCH_SA1100)
1205
1206config ARCH_SPARSEMEM_ENABLE
1207 def_bool !ARCH_FOOTBRIDGE
1208 select SPARSEMEM_STATIC if SPARSEMEM
1209
1210config HIGHMEM
1211 bool "High Memory Support"
1212 depends on MMU
1213 select KMAP_LOCAL
1214 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1215 help
1216 The address space of ARM processors is only 4 Gigabytes large
1217 and it has to accommodate user address space, kernel address
1218 space as well as some memory mapped IO. That means that, if you
1219 have a large amount of physical memory and/or IO, not all of the
1220 memory can be "permanently mapped" by the kernel. The physical
1221 memory that is not permanently mapped is called "high memory".
1222
1223 Depending on the selected kernel/user memory split, minimum
1224 vmalloc space and actual amount of RAM, you may not need this
1225 option which should result in a slightly faster kernel.
1226
1227 If unsure, say n.
1228
1229config HIGHPTE
1230 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1231 depends on HIGHMEM && !PREEMPT_RT
1232 default y
1233 help
1234 The VM uses one page of physical memory for each page table.
1235 For systems with a lot of processes, this can use a lot of
1236 precious low memory, eventually leading to low memory being
1237 consumed by page tables. Setting this option will allow
1238 user-space 2nd level page tables to reside in high memory.
1239
1240config ARM_PAN
1241 bool "Enable privileged no-access"
1242 depends on MMU
1243 default y
1244 help
1245 Increase kernel security by ensuring that normal kernel accesses
1246 are unable to access userspace addresses. This can help prevent
1247 use-after-free bugs becoming an exploitable privilege escalation
1248 by ensuring that magic values (such as LIST_POISON) will always
1249 fault when dereferenced.
1250
1251 The implementation uses CPU domains when !CONFIG_ARM_LPAE and
1252 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE.
1253
1254config CPU_SW_DOMAIN_PAN
1255 def_bool y
1256 depends on ARM_PAN && !ARM_LPAE
1257 help
1258 Enable use of CPU domains to implement privileged no-access.
1259
1260 CPUs with low-vector mappings use a best-efforts implementation.
1261 Their lower 1MB needs to remain accessible for the vectors, but
1262 the remainder of userspace will become appropriately inaccessible.
1263
1264config CPU_TTBR0_PAN
1265 def_bool y
1266 depends on ARM_PAN && ARM_LPAE
1267 help
1268 Enable privileged no-access by disabling TTBR0 page table walks when
1269 running in kernel mode.
1270
1271config HW_PERF_EVENTS
1272 def_bool y
1273 depends on ARM_PMU
1274
1275config ARM_MODULE_PLTS
1276 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1277 depends on MODULES
1278 select KASAN_VMALLOC if KASAN
1279 default y
1280 help
1281 Allocate PLTs when loading modules so that jumps and calls whose
1282 targets are too far away for their relative offsets to be encoded
1283 in the instructions themselves can be bounced via veneers in the
1284 module's PLT. This allows modules to be allocated in the generic
1285 vmalloc area after the dedicated module memory area has been
1286 exhausted. The modules will use slightly more memory, but after
1287 rounding up to page size, the actual memory footprint is usually
1288 the same.
1289
1290 Disabling this is usually safe for small single-platform
1291 configurations. If unsure, say y.
1292
1293config ARCH_FORCE_MAX_ORDER
1294 int "Order of maximal physically contiguous allocations"
1295 default "11" if SOC_AM33XX
1296 default "8" if SA1111
1297 default "10"
1298 help
1299 The kernel page allocator limits the size of maximal physically
1300 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1301 defines the maximal power of two of number of pages that can be
1302 allocated as a single contiguous block. This option allows
1303 overriding the default setting when ability to allocate very
1304 large blocks of physically contiguous memory is required.
1305
1306 Don't change if unsure.
1307
1308config ALIGNMENT_TRAP
1309 def_bool CPU_CP15_MMU
1310 select HAVE_PROC_CPU if PROC_FS
1311 help
1312 ARM processors cannot fetch/store information which is not
1313 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1314 address divisible by 4. On 32-bit ARM processors, these non-aligned
1315 fetch/store instructions will be emulated in software if you say
1316 here, which has a severe performance impact. This is necessary for
1317 correct operation of some network protocols. With an IP-only
1318 configuration it is safe to say N, otherwise say Y.
1319
1320config UACCESS_WITH_MEMCPY
1321 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1322 depends on MMU
1323 default y if CPU_FEROCEON
1324 help
1325 Implement faster copy_to_user and clear_user methods for CPU
1326 cores where a 8-word STM instruction give significantly higher
1327 memory write throughput than a sequence of individual 32bit stores.
1328
1329 A possible side effect is a slight increase in scheduling latency
1330 between threads sharing the same address space if they invoke
1331 such copy operations with large buffers.
1332
1333 However, if the CPU data cache is using a write-allocate mode,
1334 this option is unlikely to provide any performance gain.
1335
1336config PARAVIRT
1337 bool "Enable paravirtualization code"
1338 select HAVE_PV_STEAL_CLOCK_GEN
1339 help
1340 This changes the kernel so it can modify itself when it is run
1341 under a hypervisor, potentially improving performance significantly
1342 over full virtualization.
1343
1344config PARAVIRT_TIME_ACCOUNTING
1345 bool "Paravirtual steal time accounting"
1346 select PARAVIRT
1347 help
1348 Select this option to enable fine granularity task steal time
1349 accounting. Time spent executing other tasks in parallel with
1350 the current vCPU is discounted from the vCPU power. To account for
1351 that, there can be a small performance impact.
1352
1353 If in doubt, say N here.
1354
1355config XEN_DOM0
1356 def_bool y
1357 depends on XEN
1358
1359config XEN
1360 bool "Xen guest support on ARM"
1361 depends on ARM && AEABI && OF
1362 depends on CPU_V7 && !CPU_V6
1363 depends on !GENERIC_ATOMIC64
1364 depends on MMU
1365 select ARCH_DMA_ADDR_T_64BIT
1366 select ARM_PSCI
1367 select SWIOTLB
1368 select SWIOTLB_XEN
1369 select PARAVIRT
1370 help
1371 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1372
1373config CC_HAVE_STACKPROTECTOR_TLS
1374 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1375
1376config STACKPROTECTOR_PER_TASK
1377 bool "Use a unique stack canary value for each task"
1378 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1379 depends on CC_HAVE_STACKPROTECTOR_TLS
1380 default y
1381 help
1382 Due to the fact that GCC uses an ordinary symbol reference from
1383 which to load the value of the stack canary, this value can only
1384 change at reboot time on SMP systems, and all tasks running in the
1385 kernel's address space are forced to use the same canary value for
1386 the entire duration that the system is up.
1387
1388 Enable this option to switch to a different method that uses a
1389 different canary value for each task.
1390
1391endmenu
1392
1393menu "Boot options"
1394
1395config USE_OF
1396 bool "Flattened Device Tree support"
1397 select IRQ_DOMAIN
1398 select OF
1399 help
1400 Include support for flattened device tree machine descriptions.
1401
1402config ARCH_WANT_FLAT_DTB_INSTALL
1403 def_bool y
1404
1405config ATAGS
1406 bool "Support for the traditional ATAGS boot data passing"
1407 depends on EXPERT
1408 help
1409 This is the traditional way of passing data to the kernel at
1410 boot but is now only used by a few of the oldest ARMv4 and
1411 ARMv5 machines. Users that still rely on ATAGS should plan
1412 on migrating to devicetree based booting.
1413
1414 Support for ATAGS will be removed when the last machine using
1415 it is either converted to DT or removed.
1416
1417config DEPRECATED_PARAM_STRUCT
1418 bool "Provide old way to pass kernel parameters (DEPRECATED)"
1419 depends on ATAGS
1420 help
1421 This was deprecated in 2001 and announced to live on for 5 years.
1422 It is now scheduled for removal in early 2027.
1423
1424# Compressed boot loader in ROM. Yes, we really want to ask about
1425# TEXT and BSS so we preserve their values in the config files.
1426config ZBOOT_ROM_TEXT
1427 hex "Compressed ROM boot loader base address"
1428 default 0x0
1429 help
1430 The physical address at which the ROM-able zImage is to be
1431 placed in the target. Platforms which normally make use of
1432 ROM-able zImage formats normally set this to a suitable
1433 value in their defconfig file.
1434
1435 If ZBOOT_ROM is not enabled, this has no effect.
1436
1437config ZBOOT_ROM_BSS
1438 hex "Compressed ROM boot loader BSS address"
1439 default 0x0
1440 help
1441 The base address of an area of read/write memory in the target
1442 for the ROM-able zImage which must be available while the
1443 decompressor is running. It must be large enough to hold the
1444 entire decompressed kernel plus an additional 128 KiB.
1445 Platforms which normally make use of ROM-able zImage formats
1446 normally set this to a suitable value in their defconfig file.
1447
1448 If ZBOOT_ROM is not enabled, this has no effect.
1449
1450config ZBOOT_ROM
1451 bool "Compressed boot loader in ROM/flash"
1452 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1453 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1454 help
1455 Say Y here if you intend to execute your compressed kernel image
1456 (zImage) directly from ROM or flash. If unsure, say N.
1457
1458config ARM_APPENDED_DTB
1459 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1460 depends on OF
1461 help
1462 With this option, the boot code will look for a device tree binary
1463 (DTB) appended to zImage
1464 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1465
1466 This is meant as a backward compatibility convenience for those
1467 systems with a bootloader that can't be upgraded to accommodate
1468 the documented boot protocol using a device tree.
1469
1470 Beware that there is very little in terms of protection against
1471 this option being confused by leftover garbage in memory that might
1472 look like a DTB header after a reboot if no actual DTB is appended
1473 to zImage. Do not leave this option active in a production kernel
1474 if you don't intend to always append a DTB. Proper passing of the
1475 location into r2 of a bootloader provided DTB is always preferable
1476 to this option.
1477
1478config ARM_ATAG_DTB_COMPAT
1479 bool "Supplement the appended DTB with traditional ATAG information"
1480 depends on ARM_APPENDED_DTB
1481 help
1482 Some old bootloaders can't be updated to a DTB capable one, yet
1483 they provide ATAGs with memory configuration, the ramdisk address,
1484 the kernel cmdline string, etc. Such information is dynamically
1485 provided by the bootloader and can't always be stored in a static
1486 DTB. To allow a device tree enabled kernel to be used with such
1487 bootloaders, this option allows zImage to extract the information
1488 from the ATAG list and store it at run time into the appended DTB.
1489
1490choice
1491 prompt "Kernel command line type"
1492 depends on ARM_ATAG_DTB_COMPAT
1493 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1494
1495config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1496 bool "Use bootloader kernel arguments if available"
1497 help
1498 Uses the command-line options passed by the boot loader instead of
1499 the device tree bootargs property. If the boot loader doesn't provide
1500 any, the device tree bootargs property will be used.
1501
1502config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1503 bool "Extend with bootloader kernel arguments"
1504 help
1505 The command-line arguments provided by the boot loader will be
1506 appended to the the device tree bootargs property.
1507
1508endchoice
1509
1510config CMDLINE
1511 string "Default kernel command string"
1512 default ""
1513 help
1514 On some architectures (e.g. CATS), there is currently no way
1515 for the boot loader to pass arguments to the kernel. For these
1516 architectures, you should supply some command-line options at build
1517 time by entering them here. As a minimum, you should specify the
1518 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1519
1520choice
1521 prompt "Kernel command line type"
1522 depends on CMDLINE != ""
1523 default CMDLINE_FROM_BOOTLOADER
1524
1525config CMDLINE_FROM_BOOTLOADER
1526 bool "Use bootloader kernel arguments if available"
1527 help
1528 Uses the command-line options passed by the boot loader. If
1529 the boot loader doesn't provide any, the default kernel command
1530 string provided in CMDLINE will be used.
1531
1532config CMDLINE_EXTEND
1533 bool "Extend bootloader kernel arguments"
1534 help
1535 The command-line arguments provided by the boot loader will be
1536 appended to the default kernel command string.
1537
1538config CMDLINE_FORCE
1539 bool "Always use the default kernel command string"
1540 help
1541 Always use the default kernel command string, even if the boot
1542 loader passes other arguments to the kernel.
1543 This is useful if you cannot or don't want to change the
1544 command-line options your boot loader passes to the kernel.
1545endchoice
1546
1547config XIP_KERNEL
1548 bool "Kernel Execute-In-Place from ROM"
1549 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1550 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
1551 help
1552 Execute-In-Place allows the kernel to run from non-volatile storage
1553 directly addressable by the CPU, such as NOR flash. This saves RAM
1554 space since the text section of the kernel is not loaded from flash
1555 to RAM. Read-write sections, such as the data section and stack,
1556 are still copied to RAM. The XIP kernel is not compressed since
1557 it has to run directly from flash, so it will take more space to
1558 store it. The flash address used to link the kernel object files,
1559 and for storing it, is configuration dependent. Therefore, if you
1560 say Y here, you must know the proper physical address where to
1561 store the kernel image depending on your own flash memory usage.
1562
1563 Also note that the make target becomes "make xipImage" rather than
1564 "make zImage" or "make Image". The final kernel binary to put in
1565 ROM memory will be arch/arm/boot/xipImage.
1566
1567 If unsure, say N.
1568
1569config XIP_PHYS_ADDR
1570 hex "XIP Kernel Physical Location"
1571 depends on XIP_KERNEL
1572 default "0x00080000"
1573 help
1574 This is the physical address in your flash memory the kernel will
1575 be linked for and stored to. This address is dependent on your
1576 own flash usage.
1577
1578config XIP_DEFLATED_DATA
1579 bool "Store kernel .data section compressed in ROM"
1580 depends on XIP_KERNEL
1581 select ZLIB_INFLATE
1582 help
1583 Before the kernel is actually executed, its .data section has to be
1584 copied to RAM from ROM. This option allows for storing that data
1585 in compressed form and decompressed to RAM rather than merely being
1586 copied, saving some precious ROM space. A possible drawback is a
1587 slightly longer boot delay.
1588
1589config ARCH_SUPPORTS_KEXEC
1590 def_bool (!SMP || PM_SLEEP_SMP) && MMU
1591
1592config ATAGS_PROC
1593 bool "Export atags in procfs"
1594 depends on ATAGS && KEXEC
1595 default y
1596 help
1597 Should the atags used to boot the kernel be exported in an "atags"
1598 file in procfs. Useful with kexec.
1599
1600config ARCH_SUPPORTS_CRASH_DUMP
1601 def_bool y
1602
1603config ARCH_DEFAULT_CRASH_DUMP
1604 def_bool y
1605
1606config AUTO_ZRELADDR
1607 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
1608 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1609 help
1610 ZRELADDR is the physical address where the decompressed kernel
1611 image will be placed. If AUTO_ZRELADDR is selected, the address
1612 will be determined at run-time, either by masking the current IP
1613 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1614 This assumes the zImage being placed in the first 128MB from
1615 start of memory.
1616
1617config EFI_STUB
1618 bool
1619
1620config EFI
1621 bool "UEFI runtime support"
1622 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1623 select UCS2_STRING
1624 select EFI_PARAMS_FROM_FDT
1625 select EFI_STUB
1626 select EFI_GENERIC_STUB
1627 select EFI_RUNTIME_WRAPPERS
1628 help
1629 This option provides support for runtime services provided
1630 by UEFI firmware (such as non-volatile variables, realtime
1631 clock, and platform reset). A UEFI stub is also provided to
1632 allow the kernel to be booted as an EFI application. This
1633 is only useful for kernels that may run on systems that have
1634 UEFI firmware.
1635
1636config DMI
1637 bool "Enable support for SMBIOS (DMI) tables"
1638 depends on EFI
1639 default y
1640 help
1641 This enables SMBIOS/DMI feature for systems.
1642
1643 This option is only useful on systems that have UEFI firmware.
1644 However, even with this option, the resultant kernel should
1645 continue to boot on existing non-UEFI platforms.
1646
1647 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1648 i.e., the the practice of identifying the platform via DMI to
1649 decide whether certain workarounds for buggy hardware and/or
1650 firmware need to be enabled. This would require the DMI subsystem
1651 to be enabled much earlier than we do on ARM, which is non-trivial.
1652
1653endmenu
1654
1655menu "CPU Power Management"
1656
1657source "drivers/cpufreq/Kconfig"
1658
1659source "drivers/cpuidle/Kconfig"
1660
1661endmenu
1662
1663menu "Floating point emulation"
1664
1665comment "At least one emulation must be selected"
1666
1667config FPE_NWFPE
1668 bool "NWFPE math emulation (DEPRECATED)"
1669 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1670 help
1671 Say Y to include the NWFPE floating point emulator in the kernel.
1672
1673 This is only used on OABI userspace binaries, either using a
1674 pure OABI (!CONFIG_AEABI) kernel, or the OABI emulation.
1675
1676 Support for NWFPE will be removed in the future when OABI
1677 support is removed.
1678
1679config FPE_NWFPE_XP
1680 bool "Support extended precision"
1681 depends on FPE_NWFPE
1682 help
1683 Say Y to include 80-bit support in the kernel floating-point
1684 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1685 Note that gcc does not generate 80-bit operations by default,
1686 so in most cases this option only enlarges the size of the
1687 floating point emulator without any good reason.
1688
1689 You almost surely want to say N here.
1690
1691config FPE_FASTFPE
1692 bool "FastFPE math emulation (EXPERIMENTAL)"
1693 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1694 help
1695 Say Y here to include the FAST floating point emulator in the kernel.
1696 This is an experimental much faster emulator which now also has full
1697 precision for the mantissa. It does not support any exceptions.
1698 It is very simple, and approximately 3-6 times faster than NWFPE.
1699
1700 It should be sufficient for most programs. It may be not suitable
1701 for scientific calculations, but you have to check this for yourself.
1702 If you do not feel you need a faster FP emulation you should better
1703 choose NWFPE.
1704
1705config VFP
1706 bool "VFP-format floating point maths"
1707 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1708 help
1709 Say Y to include VFP support code in the kernel. This is needed
1710 if your hardware includes a VFP unit.
1711
1712 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1713 release notes and additional status information.
1714
1715 Say N if your target does not have VFP hardware.
1716
1717config VFPv3
1718 bool
1719 depends on VFP
1720 default y if CPU_V7
1721
1722config NEON
1723 bool "Advanced SIMD (NEON) Extension support"
1724 depends on VFPv3 && CPU_V7
1725 help
1726 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1727 Extension.
1728
1729config KERNEL_MODE_NEON
1730 bool "Support for NEON in kernel mode"
1731 depends on NEON && AEABI
1732 help
1733 Say Y to include support for NEON in kernel mode.
1734
1735endmenu
1736
1737config ARCH_CC_CAN_LINK
1738 bool
1739 default $(cc_can_link_user,-mlittle-endian) if CPU_LITTLE_ENDIAN
1740 default $(cc_can_link_user,-mbig-endian -mbe8) if CPU_ENDIAN_BE8
1741 default $(cc_can_link_user,-mbig-endian -mbe32) if CPU_ENDIAN_BE32
1742
1743config ARCH_USERFLAGS
1744 string
1745 default "-mlittle-endian" if CPU_LITTLE_ENDIAN
1746 default "-mbig-endian -mbe8" if CPU_ENDIAN_BE8
1747 default "-mbig-endian -mbe32" if CPU_ENDIAN_BE32
1748
1749menu "Power management options"
1750
1751source "kernel/power/Kconfig"
1752
1753config ARCH_SUSPEND_POSSIBLE
1754 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1755 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1756 def_bool y
1757
1758config ARM_CPU_SUSPEND
1759 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1760 depends on ARCH_SUSPEND_POSSIBLE
1761
1762config ARCH_HIBERNATION_POSSIBLE
1763 bool
1764 depends on MMU
1765 default y if ARCH_SUSPEND_POSSIBLE
1766
1767endmenu