| 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | menu "Platform selection" |
| 4 | depends on MMU |
| 5 | |
| 6 | comment "CPU Core family selection" |
| 7 | |
| 8 | config ARCH_MULTI_V4 |
| 9 | bool "ARMv4 based platforms (FA526, StrongARM)" |
| 10 | depends on !ARCH_MULTI_V6_V7 |
| 11 | select ARCH_MULTI_V4_V5 |
| 12 | select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) |
| 13 | |
| 14 | config ARCH_MULTI_V4T |
| 15 | bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" |
| 16 | depends on !ARCH_MULTI_V6_V7 |
| 17 | select ARCH_MULTI_V4_V5 |
| 18 | select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ |
| 19 | CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ |
| 20 | CPU_ARM925T || CPU_ARM940T) |
| 21 | |
| 22 | config ARCH_MULTI_V5 |
| 23 | bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" |
| 24 | depends on !ARCH_MULTI_V6_V7 |
| 25 | select ARCH_MULTI_V4_V5 |
| 26 | select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ |
| 27 | CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ |
| 28 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) |
| 29 | |
| 30 | config ARCH_MULTI_V4_V5 |
| 31 | bool |
| 32 | |
| 33 | config ARCH_MULTI_V6 |
| 34 | bool "ARMv6 based platforms (ARM11)" |
| 35 | select ARCH_MULTI_V6_V7 |
| 36 | select CPU_ARM1176 |
| 37 | |
| 38 | config ARCH_MULTI_V7 |
| 39 | bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" |
| 40 | default y |
| 41 | select ARCH_MULTI_V6_V7 |
| 42 | select CPU_V7 |
| 43 | select HAVE_SMP |
| 44 | |
| 45 | config ARCH_MULTI_V6_V7 |
| 46 | bool |
| 47 | select MIGHT_HAVE_CACHE_L2X0 |
| 48 | |
| 49 | config ARCH_MULTI_CPU_AUTO |
| 50 | def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) |
| 51 | select ARCH_MULTI_V5 |
| 52 | |
| 53 | endmenu |
| 54 | |
| 55 | config ARCH_VIRT |
| 56 | bool "Dummy Virtual Machine" |
| 57 | depends on ARCH_MULTI_V7 |
| 58 | select ARM_AMBA |
| 59 | select ARM_GIC |
| 60 | select ARM_GIC_V2M if PCI |
| 61 | select ARM_GIC_V3 |
| 62 | select ARM_GIC_V3_ITS if PCI |
| 63 | select ARM_PSCI |
| 64 | select HAVE_ARM_ARCH_TIMER |
| 65 | |
| 66 | config ARCH_AIROHA |
| 67 | bool "Airoha SoC Support" |
| 68 | depends on ARCH_MULTI_V7 |
| 69 | select ARM_AMBA |
| 70 | select ARM_GIC |
| 71 | select ARM_GIC_V3 |
| 72 | select ARM_PSCI |
| 73 | select HAVE_ARM_ARCH_TIMER |
| 74 | help |
| 75 | Support for Airoha EN7523 SoCs |
| 76 | |
| 77 | config MACH_ASM9260 |
| 78 | bool "Alphascale ASM9260" |
| 79 | depends on ARCH_MULTI_V5 |
| 80 | depends on CPU_LITTLE_ENDIAN |
| 81 | select CPU_ARM926T |
| 82 | select ASM9260_TIMER |
| 83 | help |
| 84 | Support for Alphascale ASM9260 based platform. |
| 85 | |
| 86 | menuconfig ARCH_HPE |
| 87 | bool "HPE SoC support" |
| 88 | depends on ARCH_MULTI_V7 |
| 89 | help |
| 90 | This enables support for HPE ARM based BMC chips. |
| 91 | |
| 92 | if ARCH_HPE |
| 93 | |
| 94 | config ARCH_HPE_GXP |
| 95 | bool "HPE GXP SoC" |
| 96 | depends on ARCH_MULTI_V7 |
| 97 | select ARM_VIC |
| 98 | select GENERIC_IRQ_CHIP |
| 99 | select CLKSRC_MMIO |
| 100 | help |
| 101 | HPE GXP is the name of the HPE Soc. This SoC is used to implement many |
| 102 | BMC features at HPE. It supports ARMv7 architecture based on the Cortex |
| 103 | A9 core. It is capable of using an AXI bus to which a memory controller |
| 104 | is attached. It has multiple SPI interfaces to connect boot flash and |
| 105 | BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It |
| 106 | has multiple i2c engines to drive connectivity with a host |
| 107 | infrastructure. |
| 108 | |
| 109 | endif |
| 110 | |
| 111 | menuconfig ARCH_MOXART |
| 112 | bool "MOXA ART SoC" |
| 113 | depends on ARCH_MULTI_V4 |
| 114 | depends on CPU_LITTLE_ENDIAN |
| 115 | select CPU_FA526 |
| 116 | select ARM_DMA_MEM_BUFFERABLE |
| 117 | select FARADAY_FTINTC010 |
| 118 | select FTTMR010_TIMER |
| 119 | select GPIOLIB |
| 120 | select PHYLIB if NETDEVICES |
| 121 | help |
| 122 | Say Y here if you want to run your kernel on hardware with a |
| 123 | MOXA ART SoC. |
| 124 | The MOXA ART SoC is based on a Faraday FA526 ARMv4 32-bit |
| 125 | 192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX). |
| 126 | Used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341. |
| 127 | |
| 128 | if ARCH_MOXART |
| 129 | |
| 130 | config MACH_UC7112LX |
| 131 | bool "MOXA UC-7112-LX" |
| 132 | depends on ARCH_MOXART |
| 133 | help |
| 134 | Say Y here if you intend to run this kernel on a MOXA |
| 135 | UC-7112-LX embedded computer. |
| 136 | |
| 137 | endif |
| 138 | |
| 139 | config ARCH_NSPIRE |
| 140 | bool "TI-NSPIRE based" |
| 141 | depends on ARCH_MULTI_V4T |
| 142 | depends on CPU_LITTLE_ENDIAN |
| 143 | select CPU_ARM926T |
| 144 | select GENERIC_IRQ_CHIP |
| 145 | select ARM_AMBA |
| 146 | select ARM_VIC |
| 147 | select ARM_TIMER_SP804 |
| 148 | select NSPIRE_TIMER |
| 149 | select POWER_RESET |
| 150 | select POWER_RESET_SYSCON |
| 151 | help |
| 152 | This enables support for systems using the TI-NSPIRE CPU |
| 153 | |
| 154 | config ARCH_RDA |
| 155 | bool "RDA Micro SoCs" |
| 156 | depends on ARCH_MULTI_V7 |
| 157 | select RDA_INTC |
| 158 | select RDA_TIMER |
| 159 | help |
| 160 | This enables support for the RDA Micro 8810PL SoC family. |
| 161 | |
| 162 | menuconfig ARCH_SUNPLUS |
| 163 | bool "Sunplus SoCs" |
| 164 | depends on ARCH_MULTI_V7 |
| 165 | help |
| 166 | Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems, |
| 167 | such as the Banana Pi BPI-F2S development board (and derivatives). |
| 168 | (<http://www.sinovoip.com.cn/ecp_view.asp?id=586>) |
| 169 | (<https://tibbo.com/store/plus1.html>) |
| 170 | |
| 171 | if ARCH_SUNPLUS |
| 172 | |
| 173 | config SOC_SP7021 |
| 174 | bool "Sunplus SP7021 SoC support" |
| 175 | default ARCH_SUNPLUS |
| 176 | select HAVE_ARM_ARCH_TIMER |
| 177 | select ARM_GIC |
| 178 | select ARM_PSCI |
| 179 | select PINCTRL |
| 180 | select PINCTRL_SPPCTL |
| 181 | select SERIAL_SUNPLUS if TTY |
| 182 | select SERIAL_SUNPLUS_CONSOLE if TTY |
| 183 | help |
| 184 | Support for Sunplus SP7021 SoC. It is based on ARM 4-core |
| 185 | Cortex-A7 with various peripherals (e.g.: I2C, SPI, SDIO, |
| 186 | Ethernet, etc.), FPGA interface, chip-to-chip bus. |
| 187 | It is designed for industrial control. |
| 188 | |
| 189 | endif |
| 190 | |
| 191 | config ARCH_UNIPHIER |
| 192 | bool "Socionext UniPhier SoCs" |
| 193 | depends on ARCH_MULTI_V7 |
| 194 | select ARCH_HAS_RESET_CONTROLLER |
| 195 | select ARM_AMBA |
| 196 | select ARM_GLOBAL_TIMER |
| 197 | select ARM_GIC |
| 198 | select HAVE_ARM_SCU |
| 199 | select HAVE_ARM_TWD if SMP |
| 200 | select PINCTRL |
| 201 | select RESET_CONTROLLER |
| 202 | help |
| 203 | Support for UniPhier SoC family developed by Socionext Inc. |
| 204 | (formerly, System LSI Business Division of Panasonic Corporation) |