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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/io.h
4 *
5 * Copyright (C) 1996-2000 Russell King
6 *
7 * Modifications:
8 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
9 * constant addresses and variable addresses.
10 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
11 * specific IO header files.
12 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
13 * 04-Apr-1999 PJB Added check_signature.
14 * 12-Dec-1999 RMK More cleanups
15 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
16 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
17 */
18#ifndef __ASM_ARM_IO_H
19#define __ASM_ARM_IO_H
20
21#ifdef __KERNEL__
22
23#include <linux/string.h>
24#include <linux/types.h>
25#include <asm/byteorder.h>
26#include <asm/page.h>
27#include <asm-generic/pci_iomap.h>
28
29/*
30 * ISA I/O bus memory addresses are 1:1 with the physical address.
31 */
32#define isa_virt_to_bus virt_to_phys
33#define isa_bus_to_virt phys_to_virt
34
35/*
36 * Atomic MMIO-wide IO modify
37 */
38extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
39extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
40
41/*
42 * Generic IO read/write. These perform native-endian accesses. Note
43 * that some architectures will want to re-define __raw_{read,write}w.
44 */
45void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
46void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
47void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
48
49void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
50void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
51void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
52
53#if __LINUX_ARM_ARCH__ < 6
54/*
55 * Half-word accesses are problematic with RiscPC due to limitations of
56 * the bus. Rather than special-case the machine, just let the compiler
57 * generate the access for CPUs prior to ARMv6.
58 */
59#define __raw_writew __raw_writew
60static __no_kasan_or_inline void __raw_writew(u16 val, volatile void __iomem *addr)
61{
62 __chk_io_ptr(addr);
63 *(volatile unsigned short __force *)addr = val;
64}
65
66#define __raw_readw __raw_readw
67static __no_kasan_or_inline u16 __raw_readw(const volatile void __iomem *addr)
68{
69 __chk_io_ptr(addr);
70 return *(const volatile unsigned short __force *)addr;
71}
72#else
73/*
74 * When running under a hypervisor, we want to avoid I/O accesses with
75 * writeback addressing modes as these incur a significant performance
76 * overhead (the address generation must be emulated in software).
77 */
78#define __raw_writew __raw_writew
79static inline void __raw_writew(u16 val, volatile void __iomem *addr)
80{
81 asm volatile("strh %1, %0"
82 : : "Q" (*(volatile u16 __force *)addr), "r" (val));
83}
84
85#define __raw_readw __raw_readw
86static inline u16 __raw_readw(const volatile void __iomem *addr)
87{
88 u16 val;
89 asm volatile("ldrh %0, %1"
90 : "=r" (val)
91 : "Q" (*(volatile u16 __force *)addr));
92 return val;
93}
94#endif
95
96#define __raw_writeb __raw_writeb
97static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
98{
99 asm volatile("strb %1, %0"
100 : : "Qo" (*(volatile u8 __force *)addr), "r" (val));
101}
102
103#define __raw_writel __raw_writel
104static inline void __raw_writel(u32 val, volatile void __iomem *addr)
105{
106 asm volatile("str %1, %0"
107 : : "Qo" (*(volatile u32 __force *)addr), "r" (val));
108}
109
110#define __raw_readb __raw_readb
111static inline u8 __raw_readb(const volatile void __iomem *addr)
112{
113 u8 val;
114 asm volatile("ldrb %0, %1"
115 : "=r" (val)
116 : "Qo" (*(volatile u8 __force *)addr));
117 return val;
118}
119
120#define __raw_readl __raw_readl
121static inline u32 __raw_readl(const volatile void __iomem *addr)
122{
123 u32 val;
124 asm volatile("ldr %0, %1"
125 : "=r" (val)
126 : "Qo" (*(volatile u32 __force *)addr));
127 return val;
128}
129
130/*
131 * Architecture ioremap implementation.
132 */
133#define MT_DEVICE 0
134#define MT_DEVICE_NONSHARED 1
135#define MT_DEVICE_CACHED 2
136#define MT_DEVICE_WC 3
137/*
138 * types 4 onwards can be found in asm/mach/map.h and are undefined
139 * for ioremap
140 */
141
142/*
143 * __arm_ioremap takes CPU physical address.
144 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
145 * The _caller variety takes a __builtin_return_address(0) value for
146 * /proc/vmalloc to use - and should only be used in non-inline functions.
147 */
148extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
149 void *);
150extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
151extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
152void __arm_iomem_set_ro(void __iomem *ptr, size_t size);
153
154extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
155 unsigned int, void *);
156
157/*
158 * Bad read/write accesses...
159 */
160extern void __readwrite_bug(const char *fn);
161
162/*
163 * A typesafe __io() helper
164 */
165static inline void __iomem *__typesafe_io(unsigned long addr)
166{
167 return (void __iomem *)addr;
168}
169
170#define IOMEM(x) ((void __force __iomem *)(x))
171
172/* IO barriers */
173#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
174#include <asm/barrier.h>
175#define __iormb() rmb()
176#define __iowmb() wmb()
177#else
178#define __iormb() do { } while (0)
179#define __iowmb() do { } while (0)
180#endif
181
182/* PCI fixed i/o mapping */
183#define PCI_IO_VIRT_BASE 0xfee00000
184#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
185
186#if defined(CONFIG_PCI) || IS_ENABLED(CONFIG_PCMCIA)
187void pci_ioremap_set_mem_type(int mem_type);
188#else
189static inline void pci_ioremap_set_mem_type(int mem_type) {}
190#endif
191
192struct resource;
193
194#define pci_remap_iospace pci_remap_iospace
195int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
196
197/*
198 * PCI configuration space mapping function.
199 *
200 * The PCI specification does not allow configuration write
201 * transactions to be posted. Add an arch specific
202 * pci_remap_cfgspace() definition that is implemented
203 * through strongly ordered memory mappings.
204 */
205#define pci_remap_cfgspace pci_remap_cfgspace
206void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);
207/*
208 * Now, pick up the machine-defined IO definitions
209 */
210#ifdef CONFIG_NEED_MACH_IO_H
211#include <mach/io.h>
212#else
213#if IS_ENABLED(CONFIG_PCMCIA) || defined(CONFIG_PCI)
214#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
215#else
216#define IO_SPACE_LIMIT ((resource_size_t)0)
217#endif
218#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
219#endif
220
221/*
222 * IO port access primitives
223 * -------------------------
224 *
225 * The ARM doesn't have special IO access instructions; all IO is memory
226 * mapped. Note that these are defined to perform little endian accesses
227 * only. Their primary purpose is to access PCI and ISA peripherals.
228 *
229 * Note that for a big endian machine, this implies that the following
230 * big endian mode connectivity is in place, as described by numerous
231 * ARM documents:
232 *
233 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
234 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
235 *
236 * The machine specific io.h include defines __io to translate an "IO"
237 * address to a memory address.
238 *
239 * Note that we prevent GCC re-ordering or caching values in expressions
240 * by introducing sequence points into the in*() definitions. Note that
241 * __raw_* do not guarantee this behaviour.
242 *
243 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
244 */
245#ifdef __io
246#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
247#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
248 cpu_to_le16(v),__io(p)); })
249#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
250 cpu_to_le32(v),__io(p)); })
251
252#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
253#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
254 __raw_readw(__io(p))); __iormb(); __v; })
255#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
256 __raw_readl(__io(p))); __iormb(); __v; })
257
258#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
259#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
260#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
261
262#define insb(p,d,l) __raw_readsb(__io(p),d,l)
263#define insw(p,d,l) __raw_readsw(__io(p),d,l)
264#define insl(p,d,l) __raw_readsl(__io(p),d,l)
265#endif
266
267/*
268 * String version of IO memory access ops:
269 */
270extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
271extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
272extern void _memset_io(volatile void __iomem *, int, size_t);
273
274/*
275 * Memory access primitives
276 * ------------------------
277 *
278 * These perform PCI memory accesses via an ioremap region. They don't
279 * take an address as such, but a cookie.
280 *
281 * Again, these are defined to perform little endian accesses. See the
282 * IO port primitives for more information.
283 */
284#ifndef readl
285#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
286#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
287 __raw_readw(c)); __r; })
288#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
289 __raw_readl(c)); __r; })
290
291#define writeb_relaxed(v,c) __raw_writeb(v,c)
292#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
293#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
294
295#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
296#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
297#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
298
299#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
300#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
301#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
302
303#define readsb(p,d,l) __raw_readsb(p,d,l)
304#define readsw(p,d,l) __raw_readsw(p,d,l)
305#define readsl(p,d,l) __raw_readsl(p,d,l)
306
307#define writesb(p,d,l) __raw_writesb(p,d,l)
308#define writesw(p,d,l) __raw_writesw(p,d,l)
309#define writesl(p,d,l) __raw_writesl(p,d,l)
310
311#ifndef __ARMBE__
312static inline void memset_io(volatile void __iomem *dst, unsigned c,
313 size_t count)
314{
315 extern void mmioset(void *, unsigned int, size_t);
316 mmioset((void __force *)dst, c, count);
317}
318#define memset_io(dst,c,count) memset_io(dst,c,count)
319
320static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
321 size_t count)
322{
323 extern void mmiocpy(void *, const void *, size_t);
324 mmiocpy(to, (const void __force *)from, count);
325}
326#define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count)
327
328static inline void memcpy_toio(volatile void __iomem *to, const void *from,
329 size_t count)
330{
331 extern void mmiocpy(void *, const void *, size_t);
332 mmiocpy((void __force *)to, from, count);
333}
334#define memcpy_toio(to,from,count) memcpy_toio(to,from,count)
335
336#else
337#define memset_io(c,v,l) _memset_io(c,(v),(l))
338#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
339#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
340#endif
341
342#endif /* readl */
343
344/*
345 * ioremap() and friends.
346 *
347 * ioremap() takes a resource address, and size. Due to the ARM memory
348 * types, it is important to use the correct ioremap() function as each
349 * mapping has specific properties.
350 *
351 * Function Memory type Cacheability Cache hint
352 * ioremap() Device n/a n/a
353 * ioremap_cache() Normal Writeback Read allocate
354 * ioremap_wc() Normal Non-cacheable n/a
355 * ioremap_wt() Normal Non-cacheable n/a
356 *
357 * All device mappings have the following properties:
358 * - no access speculation
359 * - no repetition (eg, on return from an exception)
360 * - number, order and size of accesses are maintained
361 * - unaligned accesses are "unpredictable"
362 * - writes may be delayed before they hit the endpoint device
363 *
364 * All normal memory mappings have the following properties:
365 * - reads can be repeated with no side effects
366 * - repeated reads return the last value written
367 * - reads can fetch additional locations without side effects
368 * - writes can be repeated (in certain cases) with no side effects
369 * - writes can be merged before accessing the target
370 * - unaligned accesses can be supported
371 * - ordering is not guaranteed without explicit dependencies or barrier
372 * instructions
373 * - writes may be delayed before they hit the endpoint memory
374 *
375 * The cache hint is only a performance hint: CPUs may alias these hints.
376 * Eg, a CPU not implementing read allocate but implementing write allocate
377 * will provide a write allocate mapping instead.
378 */
379void __iomem *ioremap(resource_size_t res_cookie, size_t size);
380#define ioremap ioremap
381
382/*
383 * Do not use ioremap_cache for mapping memory. Use memremap instead.
384 */
385void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
386#define ioremap_cache ioremap_cache
387
388void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
389#define ioremap_wc ioremap_wc
390#define ioremap_wt ioremap_wc
391
392void iounmap(volatile void __iomem *io_addr);
393#define iounmap iounmap
394
395void *arch_memremap_wb(phys_addr_t phys_addr, size_t size, unsigned long flags);
396#define arch_memremap_wb arch_memremap_wb
397
398/*
399 * io{read,write}{16,32}be() macros
400 */
401#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
402#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
403
404#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
405#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
406
407#ifndef ioport_map
408#define ioport_map ioport_map
409extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
410#endif
411#ifndef ioport_unmap
412#define ioport_unmap ioport_unmap
413extern void ioport_unmap(void __iomem *addr);
414#endif
415
416struct pci_dev;
417
418#define pci_iounmap pci_iounmap
419extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
420
421#include <asm-generic/io.h>
422
423#ifdef CONFIG_MMU
424#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
425extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
426extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
427extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
428 unsigned long flags);
429#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
430#endif
431
432/*
433 * Register ISA memory and port locations for glibc iopl/inb/outb
434 * emulation.
435 */
436extern void register_isa_ports(unsigned int mmio, unsigned int io,
437 unsigned int io_shift);
438
439#endif /* __KERNEL__ */
440#endif /* __ASM_ARM_IO_H */