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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Debugging macro include header
4 *
5 * Copyright (C) 2011 Xilinx
6 */
7#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
8#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
9#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
10
11#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
12#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
13
14#define UART0_PHYS 0xE0000000
15#define UART0_VIRT 0xF0800000
16#define UART1_PHYS 0xE0001000
17#define UART1_VIRT 0xF0801000
18
19#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
20# define LL_UART_PADDR UART1_PHYS
21# define LL_UART_VADDR UART1_VIRT
22#else
23# define LL_UART_PADDR UART0_PHYS
24# define LL_UART_VADDR UART0_VIRT
25#endif
26
27 .macro addruart, rp, rv, tmp
28 ldr \rp, =LL_UART_PADDR @ physical
29 ldr \rv, =LL_UART_VADDR @ virtual
30 .endm
31
32 .macro senduart,rd,rx
33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
34 .endm
35
36 .macro waituartcts,rd,rx
37 .endm
38
39 .macro waituarttxrdy,rd,rx
401001: ldr \rd, [\rx, #UART_SR_OFFSET]
41ARM_BE8( rev \rd, \rd )
42 tst \rd, #UART_SR_TXEMPTY
43 beq 1001b
44 .endm
45
46 .macro busyuart,rd,rx
471002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
48ARM_BE8( rev \rd, \rd )
49 tst \rd, #UART_SR_TXFULL @
50 bne 1002b @ wait if FIFO is full
51 .endm