| 1 | /* SPDX-License-Identifier: GPL-2.0-only */
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| 2 | /*
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| 3 | * linux/arch/arm/kernel/head-common.S
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| 4 | *
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| 5 | * Copyright (C) 1994-2002 Russell King
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| 6 | * Copyright (c) 2003 ARM Limited
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| 7 | * All Rights Reserved
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| 8 | */
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| 9 | |
| 10 |
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| 11 | |
| 12 | |
| 13 | |
| 14 |
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| 15 | |
| 16 | |
| 17 | |
| 18 | |
| 19 | |
| 20 |
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| 21 | /*
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| 22 | * Exception handling. Something went wrong and we can't proceed. We
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| 23 | * ought to tell the user, but since we don't have any guarantee that
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| 24 | * we're even running on the right architecture, we do virtually nothing.
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| 25 | *
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| 26 | * If CONFIG_DEBUG_LL is set we try to print out something about the error
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| 27 | * and hope for the best (useful if bootloader fails to pass a proper
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| 28 | * machine ID for example).
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| 29 | */
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| 30 | __HEAD
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| 31 |
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| 32 | /* Determine validity of the r2 atags pointer. The heuristic requires
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| 33 | * that the pointer be aligned, in the first 16k of physical RAM and
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| 34 | * that the ATAG_CORE marker is first and present. If CONFIG_OF_FLATTREE
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| 35 | * is selected, then it will also accept a dtb pointer. Future revisions
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| 36 | * of this function may be more lenient with the physical address and
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| 37 | * may also be able to move the ATAGS block if necessary.
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| 38 | *
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| 39 | * Returns:
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| 40 | * r2 either valid atags pointer, valid dtb pointer, or zero
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| 41 | * r5, r6 corrupted
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| 42 | */
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| 43 | __vet_atags:
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| 44 | tst r2, #0x3 @ aligned?
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| 45 | bne 1f
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| 46 |
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| 47 | ldr r5, [r2, #0]
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| 48 | #ifdef CONFIG_OF_FLATTREE
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| 49 | ldr r6, =OF_DT_MAGIC @ is it a DTB?
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| 50 | cmp r5, r6
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| 51 | beq 2f
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| 52 | #endif
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| 53 | cmp r5, #ATAG_CORE_SIZE @ is first tag ATAG_CORE?
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| 54 | cmpne r5, #ATAG_CORE_SIZE_EMPTY
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| 55 | bne 1f
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| 56 | ldr r5, [r2, #4]
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| 57 | ldr r6, =ATAG_CORE
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| 58 | cmp r5, r6
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| 59 | bne 1f
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| 60 |
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| 61 | 2: ret lr @ atag/dtb pointer is ok
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| 62 |
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| 63 | 1: mov r2, #0
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| 64 | ret lr
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| 65 | ENDPROC(__vet_atags)
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| 66 |
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| 67 | /*
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| 68 | * The following fragment of code is executed with the MMU on in MMU mode,
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| 69 | * and uses absolute addresses; this is not position independent.
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| 70 | *
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| 71 | * r0 = cp#15 control register (exc_ret for M-class)
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| 72 | * r1 = machine ID
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| 73 | * r2 = atags/dtb pointer
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| 74 | * r9 = processor ID
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| 75 | */
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| 76 | __INIT
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| 77 | __mmap_switched:
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| 78 |
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| 79 | mov r7, r1
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| 80 | mov r8, r2
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| 81 | mov r10, r0
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| 82 |
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| 83 | adr r4, __mmap_switched_data
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| 84 | mov fp, #0
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| 85 |
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| 86 | #if defined(CONFIG_XIP_DEFLATED_DATA)
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| 87 | ARM( ldr sp, [r4], #4 )
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| 88 | THUMB( ldr sp, [r4] )
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| 89 | THUMB( add r4, #4 )
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| 90 | bl __inflate_kernel_data @ decompress .data to RAM
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| 91 | teq r0, #0
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| 92 | bne __error
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| 93 | #elif defined(CONFIG_XIP_KERNEL)
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| 94 | ARM( ldmia r4!, {r0, r1, r2, sp} )
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| 95 | THUMB( ldmia r4!, {r0, r1, r2, r3} )
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| 96 | THUMB( mov sp, r3 )
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| 97 | sub r2, r2, r1
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| 98 | bl __memcpy @ copy .data to RAM
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| 99 | #endif
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| 100 |
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| 101 | ARM( ldmia r4!, {r0, r1, sp} )
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| 102 | THUMB( ldmia r4!, {r0, r1, r3} )
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| 103 | THUMB( mov sp, r3 )
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| 104 | sub r2, r1, r0
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| 105 | mov r1, #0
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| 106 | bl __memset @ clear .bss
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| 107 |
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| 108 | adr_l r0, init_task @ get swapper task_struct
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| 109 | set_current r0, r1
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| 110 |
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| 111 | ldmia r4, {r0, r1, r2, r3}
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| 112 | str r9, [r0] @ Save processor ID
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| 113 | str r7, [r1] @ Save machine type
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| 114 | str r8, [r2] @ Save atags pointer
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| 115 | cmp r3, #0
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| 116 | strne r10, [r3] @ Save control register values
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| 117 | #ifdef CONFIG_KASAN
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| 118 | bl kasan_early_init
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| 119 | #endif
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| 120 | mov lr, #0
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| 121 | b start_kernel
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| 122 | ENDPROC(__mmap_switched)
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| 123 |
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| 124 | .align 2
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| 125 | .type __mmap_switched_data, %object
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| 126 | __mmap_switched_data:
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| 127 | #ifdef CONFIG_XIP_KERNEL
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| 128 | #ifndef CONFIG_XIP_DEFLATED_DATA
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| 129 | .long _sdata @ r0
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| 130 | .long __data_loc @ r1
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| 131 | .long _edata_loc @ r2
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| 132 | #endif
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| 133 | .long __bss_stop @ sp (temporary stack in .bss)
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| 134 | #endif
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| 135 |
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| 136 | .long __bss_start @ r0
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| 137 | .long __bss_stop @ r1
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| 138 | .long init_thread_union + THREAD_START_SP @ sp
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| 139 |
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| 140 | .long processor_id @ r0
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| 141 | .long __machine_arch_type @ r1
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| 142 | .long __atags_pointer @ r2
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| 143 | #ifdef CONFIG_CPU_CP15
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| 144 | .long cr_alignment @ r3
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| 145 | #else
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| 146 | M_CLASS(.long exc_ret) @ r3
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| 147 | AR_CLASS(.long 0) @ r3
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| 148 | #endif
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| 149 | .size __mmap_switched_data, . - __mmap_switched_data
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| 150 |
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| 151 | __FINIT
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| 152 | .text
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| 153 |
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| 154 | /*
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| 155 | * This provides a C-API version of __lookup_processor_type
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| 156 | */
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| 157 | ENTRY(lookup_processor_type)
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| 158 | stmfd sp!, {r4 - r6, r9, lr}
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| 159 | mov r9, r0
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| 160 | bl __lookup_processor_type
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| 161 | mov r0, r5
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| 162 | ldmfd sp!, {r4 - r6, r9, pc}
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| 163 | ENDPROC(lookup_processor_type)
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| 164 |
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| 165 | /*
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| 166 | * Read processor ID register (CP#15, CR0), and look up in the linker-built
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| 167 | * supported processor list. Note that we can't use the absolute addresses
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| 168 | * for the __proc_info lists since we aren't running with the MMU on
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| 169 | * (and therefore, we are not in the correct address space). We have to
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| 170 | * calculate the offset.
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| 171 | *
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| 172 | * r9 = cpuid
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| 173 | * Returns:
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| 174 | * r3, r4, r6 corrupted
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| 175 | * r5 = proc_info pointer in physical address space
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| 176 | * r9 = cpuid (preserved)
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| 177 | */
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| 178 | __lookup_processor_type:
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| 179 | /*
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| 180 | * Look in <asm/procinfo.h> for information about the __proc_info
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| 181 | * structure.
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| 182 | */
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| 183 | adr_l r5, __proc_info_begin
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| 184 | adr_l r6, __proc_info_end
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| 185 | 1: ldmia r5, {r3, r4} @ value, mask
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| 186 | and r4, r4, r9 @ mask wanted bits
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| 187 | teq r3, r4
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| 188 | beq 2f
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| 189 | add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
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| 190 | cmp r5, r6
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| 191 | blo 1b
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| 192 | mov r5, #0 @ unknown processor
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| 193 | 2: ret lr
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| 194 | ENDPROC(__lookup_processor_type)
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| 195 |
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| 196 | __error_lpae:
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| 197 | #ifdef CONFIG_DEBUG_LL
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| 198 | adr r0, str_lpae
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| 199 | bl printascii
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| 200 | b __error
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| 201 | str_lpae: .asciz "\nError: Kernel with LPAE support, but CPU does not support LPAE.\n"
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| 202 | #else
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| 203 | b __error
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| 204 | #endif
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| 205 | .align
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| 206 | ENDPROC(__error_lpae)
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| 207 |
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| 208 | __error_p:
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| 209 | #ifdef CONFIG_DEBUG_LL
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| 210 | adr r0, str_p1
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| 211 | bl printascii
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| 212 | mov r0, r9
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| 213 | bl printhex8
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| 214 | adr r0, str_p2
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| 215 | bl printascii
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| 216 | b __error
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| 217 | str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x"
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| 218 | str_p2: .asciz ").\n"
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| 219 | .align
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| 220 | #endif
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| 221 | ENDPROC(__error_p)
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| 222 |
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| 223 | __error:
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| 224 | #ifdef CONFIG_ARCH_RPC
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| 225 | /*
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| 226 | * Turn the screen red on a error - RiscPC only.
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| 227 | */
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| 228 | mov r0, #0x02000000
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| 229 | mov r3, #0x11
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| 230 | orr r3, r3, r3, lsl #8
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| 231 | orr r3, r3, r3, lsl #16
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| 232 | str r3, [r0], #4
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| 233 | str r3, [r0], #4
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| 234 | str r3, [r0], #4
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| 235 | str r3, [r0], #4
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| 236 | #endif
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| 237 | 1: mov r0, r0
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| 238 | b 1b
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| 239 | ENDPROC(__error)
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