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| 2 | |
| 3 | * linux/arch/arm/kernel/irq.c
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| 4 | *
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| 5 | * Copyright (C) 1992 Linus Torvalds
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| 6 | * Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
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| 7 | *
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| 8 | * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
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| 9 | * Dynamic Tick Timer written by Tony Lindgren <[email protected]> and
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| 10 | * Tuukka Tikkanen <[email protected]>.
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| 11 | *
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| 12 | * This file contains the code used by various IRQ handling routines:
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| 13 | * asking for different IRQ's should be done through these routines
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| 14 | * instead of just grabbing them. Thus setups with different IRQ numbers
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| 15 | * shouldn't result in any weird surprises, and installing new handlers
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| 16 | * should be easier.
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| 17 | *
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| 18 | * IRQ's are in fact implemented a bit like signal handlers for the kernel.
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| 19 | * Naturally it's not a 1:1 relation, but there are similarities.
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| 20 |
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| 21 | #include <linux/signal.h>
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| 22 | #include <linux/ioport.h>
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| 23 | #include <linux/interrupt.h>
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| 24 | #include <linux/irq.h>
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| 25 | #include <linux/irqchip.h>
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| 26 | #include <linux/random.h>
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| 27 | #include <linux/smp.h>
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| 28 | #include <linux/init.h>
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| 29 | #include <linux/seq_file.h>
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| 30 | #include <linux/errno.h>
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| 31 | #include <linux/list.h>
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| 32 | #include <linux/kallsyms.h>
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| 33 | #include <linux/proc_fs.h>
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| 34 | #include <linux/export.h>
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| 35 | #include <linux/vmalloc.h>
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| 36 |
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| 37 | #include <asm/hardware/cache-l2x0.h>
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| 38 | #include <asm/hardware/cache-uniphier.h>
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| 39 | #include <asm/outercache.h>
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| 40 | #include <asm/softirq_stack.h>
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| 41 | #include <asm/exception.h>
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| 42 | #include <asm/mach/arch.h>
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| 43 | #include <asm/mach/irq.h>
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| 44 | #include <asm/mach/time.h>
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| 45 |
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| 46 | #include "reboot.h"
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| 47 |
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| 48 | unsigned long irq_err_count;
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| 49 |
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| 50 | #ifdef CONFIG_IRQSTACKS
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| 51 |
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| 52 | asmlinkage DEFINE_PER_CPU_READ_MOSTLY(u8 *, irq_stack_ptr);
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| 53 |
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| 54 | static void __init init_irq_stacks(void)
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| 55 | {
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| 56 | u8 *stack;
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| 57 | int cpu;
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| 58 |
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| 59 | for_each_possible_cpu(cpu) {
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| 60 | if (!IS_ENABLED(CONFIG_VMAP_STACK))
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| 61 | stack = (u8 *)__get_free_pages(GFP_KERNEL,
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| 62 | THREAD_SIZE_ORDER);
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| 63 | else
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| 64 | stack = __vmalloc_node(THREAD_SIZE, THREAD_ALIGN,
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| 65 | THREADINFO_GFP, NUMA_NO_NODE,
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| 66 | __builtin_return_address(0));
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| 67 |
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| 68 | if (WARN_ON(!stack))
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| 69 | break;
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| 70 | per_cpu(irq_stack_ptr, cpu) = &stack[THREAD_SIZE];
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| 71 | }
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| 72 | }
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| 73 |
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| 74 | #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
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| 75 | static void ____do_softirq(void *arg)
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| 76 | {
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| 77 | __do_softirq();
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| 78 | }
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| 79 |
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| 80 | void do_softirq_own_stack(void)
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| 81 | {
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| 82 | call_with_stack(____do_softirq, NULL,
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| 83 | __this_cpu_read(irq_stack_ptr));
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| 84 | }
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| 85 | #endif
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| 86 | #endif
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| 87 |
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| 88 | int arch_show_interrupts(struct seq_file *p, int prec)
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| 89 | {
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| 90 | #ifdef CONFIG_FIQ
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| 91 | show_fiq_list(p, prec);
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| 92 | #endif
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| 93 | #ifdef CONFIG_SMP
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| 94 | show_ipi_list(p, prec);
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| 95 | #endif
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| 96 | seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
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| 97 | return 0;
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| 98 | }
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| 99 |
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| 100 | |
| 101 | * handle_IRQ handles all hardware IRQ's. Decoded IRQs should
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| 102 | * not come via this function. Instead, they should provide their
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| 103 | * own 'handler'. Used by platform code implementing C-based 1st
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| 104 | * level decoding.
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| 105 |
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| 106 | void handle_IRQ(unsigned int irq, struct pt_regs *regs)
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| 107 | {
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| 108 | struct irq_desc *desc;
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| 109 |
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| 110 | |
| 111 | * Some hardware gives randomly wrong interrupts. Rather
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| 112 | * than crashing, do something sensible.
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| 113 |
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| 114 | if (unlikely(!irq || irq >= irq_get_nr_irqs()))
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| 115 | desc = NULL;
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| 116 | else
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| 117 | desc = irq_to_desc(irq);
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| 118 |
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| 119 | if (likely(desc))
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| 120 | handle_irq_desc(desc);
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| 121 | else
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| 122 | ack_bad_irq(irq);
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| 123 | }
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| 124 |
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| 125 | void __init init_IRQ(void)
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| 126 | {
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| 127 | int ret;
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| 128 |
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| 129 | #ifdef CONFIG_IRQSTACKS
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| 130 | init_irq_stacks();
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| 131 | #endif
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| 132 |
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| 133 | if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
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| 134 | irqchip_init();
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| 135 | else
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| 136 | machine_desc->init_irq();
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| 137 |
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| 138 | if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
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| 139 | (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
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| 140 | if (!outer_cache.write_sec)
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| 141 | outer_cache.write_sec = machine_desc->l2c_write_sec;
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| 142 | ret = l2x0_of_init(machine_desc->l2c_aux_val,
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| 143 | machine_desc->l2c_aux_mask);
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| 144 | if (ret && ret != -ENODEV)
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| 145 | pr_err("L2C: failed to init: %d\n", ret);
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| 146 | }
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| 147 |
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| 148 | uniphier_cache_init();
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| 149 | }
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| 150 |
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| 151 | #ifdef CONFIG_SPARSE_IRQ
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| 152 | int __init arch_probe_nr_irqs(void)
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| 153 | {
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| 154 | return irq_set_nr_irqs(machine_desc->nr_irqs ? : NR_IRQS);
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| 155 | }
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| 156 | #endif
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