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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5#ifndef __ASM_PGTABLE_H
6#define __ASM_PGTABLE_H
7
8#include <asm/bug.h>
9#include <asm/proc-fns.h>
10
11#include <asm/memory.h>
12#include <asm/mte.h>
13#include <asm/pgtable-hwdef.h>
14#include <asm/pgtable-prot.h>
15#include <asm/tlbflush.h>
16
17/*
18 * VMALLOC range.
19 *
20 * VMALLOC_START: beginning of the kernel vmalloc space
21 * VMALLOC_END: extends to the available space below vmemmap
22 */
23#define VMALLOC_START (MODULES_END)
24#if VA_BITS == VA_BITS_MIN
25#define VMALLOC_END (VMEMMAP_START - SZ_8M)
26#else
27#define VMEMMAP_UNUSED_NPAGES ((_PAGE_OFFSET(vabits_actual) - PAGE_OFFSET) >> PAGE_SHIFT)
28#define VMALLOC_END (VMEMMAP_START + VMEMMAP_UNUSED_NPAGES * sizeof(struct page) - SZ_8M)
29#endif
30
31#define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
32
33#ifndef __ASSEMBLER__
34
35#include <asm/cmpxchg.h>
36#include <asm/fixmap.h>
37#include <asm/por.h>
38#include <linux/mmdebug.h>
39#include <linux/mm_types.h>
40#include <linux/sched.h>
41#include <linux/page_table_check.h>
42
43static inline void emit_pte_barriers(void)
44{
45 /*
46 * These barriers are emitted under certain conditions after a pte entry
47 * was modified (see e.g. __set_pte_complete()). The dsb makes the store
48 * visible to the table walker. The isb ensures that any previous
49 * speculative "invalid translation" marker that is in the CPU's
50 * pipeline gets cleared, so that any access to that address after
51 * setting the pte to valid won't cause a spurious fault. If the thread
52 * gets preempted after storing to the pgtable but before emitting these
53 * barriers, __switch_to() emits a dsb which ensure the walker gets to
54 * see the store. There is no guarantee of an isb being issued though.
55 * This is safe because it will still get issued (albeit on a
56 * potentially different CPU) when the thread starts running again,
57 * before any access to the address.
58 */
59 dsb(ishst);
60 isb();
61}
62
63static inline void queue_pte_barriers(void)
64{
65 if (is_lazy_mmu_mode_active()) {
66 /* Avoid the atomic op if already set. */
67 if (!test_thread_flag(TIF_LAZY_MMU_PENDING))
68 set_thread_flag(TIF_LAZY_MMU_PENDING);
69 } else {
70 emit_pte_barriers();
71 }
72}
73
74static inline void arch_enter_lazy_mmu_mode(void) {}
75
76static inline void arch_flush_lazy_mmu_mode(void)
77{
78 if (test_and_clear_thread_flag(TIF_LAZY_MMU_PENDING))
79 emit_pte_barriers();
80}
81
82static inline void arch_leave_lazy_mmu_mode(void)
83{
84 arch_flush_lazy_mmu_mode();
85}
86
87#ifdef CONFIG_TRANSPARENT_HUGEPAGE
88#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
89
90/* Set stride and tlb_level in flush_*_tlb_range */
91#define flush_pmd_tlb_range(vma, addr, end) \
92 __flush_tlb_range(vma, addr, end, PMD_SIZE, 2, TLBF_NONE)
93#define flush_pud_tlb_range(vma, addr, end) \
94 __flush_tlb_range(vma, addr, end, PUD_SIZE, 1, TLBF_NONE)
95#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
96
97/*
98 * We use local TLB invalidation instruction when reusing page in
99 * write protection fault handler to avoid TLBI broadcast in the hot
100 * path. This will cause spurious page faults if stale read-only TLB
101 * entries exist.
102 */
103#define flush_tlb_fix_spurious_fault(vma, address, ptep) \
104 __flush_tlb_page(vma, address, TLBF_NOBROADCAST | TLBF_NONOTIFY)
105
106#define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp) \
107 __flush_tlb_range(vma, address, address + PMD_SIZE, PMD_SIZE, 2, \
108 TLBF_NOBROADCAST | TLBF_NONOTIFY | TLBF_NOWALKCACHE)
109
110#define pte_ERROR(e) \
111 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
112
113#ifdef CONFIG_ARM64_PA_BITS_52
114static inline phys_addr_t __pte_to_phys(pte_t pte)
115{
116 pte_val(pte) &= ~PTE_MAYBE_SHARED;
117 return (pte_val(pte) & PTE_ADDR_LOW) |
118 ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT);
119}
120static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
121{
122 return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PHYS_TO_PTE_ADDR_MASK;
123}
124#else
125static inline phys_addr_t __pte_to_phys(pte_t pte)
126{
127 return pte_val(pte) & PTE_ADDR_LOW;
128}
129
130static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
131{
132 return phys;
133}
134#endif
135
136#define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
137#define pfn_pte(pfn,prot) \
138 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
139
140#define pte_none(pte) (!pte_val(pte))
141#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
142
143#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
144#define pte_present_invalid(pte) \
145 ((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID)
146
147/*
148 * The following only work if pte_present(). Undefined behaviour otherwise.
149 */
150static __always_inline bool pte_present(pte_t pte)
151{
152 return pte_valid(pte) || pte_present_invalid(pte);
153}
154#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
155#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
156#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
157#define pte_rdonly(pte) (!!(pte_val(pte) & PTE_RDONLY))
158#define pte_user(pte) (!!(pte_val(pte) & PTE_USER))
159#define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
160#define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
161#define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
162 PTE_ATTRINDX(MT_NORMAL_TAGGED))
163
164#define pte_cont_addr_end(addr, end) \
165({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
166 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
167})
168
169#define pmd_cont_addr_end(addr, end) \
170({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
171 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
172})
173
174#define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte))
175#define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
176#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
177
178/*
179 * Execute-only user mappings do not have the PTE_USER bit set. All valid
180 * kernel mappings have the PTE_UXN bit set.
181 */
182#define pte_valid_not_user(pte) \
183 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
184/*
185 * Returns true if the pte is valid and has the contiguous bit set.
186 */
187#define pte_valid_cont(pte) (pte_valid(pte) && pte_cont(pte))
188/*
189 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
190 * so that we don't erroneously return false for pages that have been
191 * remapped as PROT_NONE but are yet to be flushed from the TLB.
192 * Note that we can't make any assumptions based on the state of the access
193 * flag, since __ptep_clear_flush_young() elides a DSB when invalidating the
194 * TLB.
195 */
196#define pte_accessible(mm, pte) \
197 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
198
199static inline bool por_el0_allows_pkey(u8 pkey, bool write, bool execute)
200{
201 u64 por;
202
203 if (!system_supports_poe())
204 return true;
205
206 por = read_sysreg_s(SYS_POR_EL0);
207
208 if (write)
209 return por_elx_allows_write(por, pkey);
210
211 if (execute)
212 return por_elx_allows_exec(por, pkey);
213
214 return por_elx_allows_read(por, pkey);
215}
216
217/*
218 * p??_access_permitted() is true for valid user mappings (PTE_USER
219 * bit set, subject to the write permission check). For execute-only
220 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits
221 * not set) must return false. PROT_NONE mappings do not have the
222 * PTE_VALID bit set.
223 */
224#define pte_access_permitted_no_overlay(pte, write) \
225 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
226#define pte_access_permitted(pte, write) \
227 (pte_access_permitted_no_overlay(pte, write) && \
228 por_el0_allows_pkey(FIELD_GET(PTE_PO_IDX_MASK, pte_val(pte)), write, false))
229#define pmd_access_permitted(pmd, write) \
230 (pte_access_permitted(pmd_pte(pmd), (write)))
231#define pud_access_permitted(pud, write) \
232 (pte_access_permitted(pud_pte(pud), (write)))
233
234static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
235{
236 pte_val(pte) &= ~pgprot_val(prot);
237 return pte;
238}
239
240static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
241{
242 pte_val(pte) |= pgprot_val(prot);
243 return pte;
244}
245
246static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
247{
248 pmd_val(pmd) &= ~pgprot_val(prot);
249 return pmd;
250}
251
252static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
253{
254 pmd_val(pmd) |= pgprot_val(prot);
255 return pmd;
256}
257
258static inline pte_t pte_mkwrite_novma(pte_t pte)
259{
260 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
261 if (pte_sw_dirty(pte))
262 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
263 return pte;
264}
265
266static inline pte_t pte_mkclean(pte_t pte)
267{
268 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
269 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
270
271 return pte;
272}
273
274static inline pte_t pte_mkdirty(pte_t pte)
275{
276 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
277
278 if (pte_write(pte))
279 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
280
281 return pte;
282}
283
284static inline pte_t pte_wrprotect(pte_t pte)
285{
286 /*
287 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
288 * clear), set the PTE_DIRTY bit.
289 */
290 if (pte_hw_dirty(pte))
291 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
292
293 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
294 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
295 return pte;
296}
297
298static inline pte_t pte_mkold(pte_t pte)
299{
300 return clear_pte_bit(pte, __pgprot(PTE_AF));
301}
302
303static inline pte_t pte_mkyoung(pte_t pte)
304{
305 return set_pte_bit(pte, __pgprot(PTE_AF));
306}
307
308static inline pte_t pte_mkspecial(pte_t pte)
309{
310 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
311}
312
313static inline pte_t pte_mkcont(pte_t pte)
314{
315 return set_pte_bit(pte, __pgprot(PTE_CONT));
316}
317
318static inline pte_t pte_mknoncont(pte_t pte)
319{
320 return clear_pte_bit(pte, __pgprot(PTE_CONT));
321}
322
323static inline pte_t pte_mkvalid_k(pte_t pte)
324{
325 pte = clear_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID));
326 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_VALID_KERNEL));
327 return pte;
328}
329
330static inline pte_t pte_mkinvalid(pte_t pte)
331{
332 pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID));
333 pte = clear_pte_bit(pte, __pgprot(PTE_VALID));
334 return pte;
335}
336
337static inline pmd_t pmd_mkcont(pmd_t pmd)
338{
339 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
340}
341
342static inline pmd_t pmd_mknoncont(pmd_t pmd)
343{
344 return __pmd(pmd_val(pmd) & ~PMD_SECT_CONT);
345}
346
347#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
348static inline int pte_uffd(pte_t pte)
349{
350 return !!(pte_val(pte) & PTE_UFFD);
351}
352
353static inline pte_t pte_mkuffd(pte_t pte)
354{
355 return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD)));
356}
357
358static inline pte_t pte_clear_uffd(pte_t pte)
359{
360 return clear_pte_bit(pte, __pgprot(PTE_UFFD));
361}
362#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
363
364static inline void __set_pte_nosync(pte_t *ptep, pte_t pte)
365{
366 WRITE_ONCE(*ptep, pte);
367}
368
369static inline void __set_pte_complete(pte_t pte)
370{
371 /*
372 * Only if the new pte is valid and kernel, otherwise TLB maintenance
373 * has the necessary barriers.
374 */
375 if (pte_valid_not_user(pte))
376 queue_pte_barriers();
377}
378
379static inline void __set_pte(pte_t *ptep, pte_t pte)
380{
381 __set_pte_nosync(ptep, pte);
382 __set_pte_complete(pte);
383}
384
385static inline pte_t __ptep_get(pte_t *ptep)
386{
387 return READ_ONCE(*ptep);
388}
389
390extern void __sync_icache_dcache(pte_t pteval);
391bool pgattr_change_is_safe(pteval_t old, pteval_t new);
392
393/*
394 * PTE bits configuration in the presence of hardware Dirty Bit Management
395 * (PTE_WRITE == PTE_DBM):
396 *
397 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
398 * 0 0 | 1 0 0
399 * 0 1 | 1 1 0
400 * 1 0 | 1 0 1
401 * 1 1 | 0 1 x
402 *
403 * When hardware DBM is not present, the software PTE_DIRTY bit is updated via
404 * the page fault mechanism. Checking the dirty status of a pte becomes:
405 *
406 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
407 */
408
409static inline void __check_safe_pte_update(struct mm_struct *mm, pte_t *ptep,
410 pte_t pte)
411{
412 pte_t old_pte;
413
414 if (!IS_ENABLED(CONFIG_DEBUG_VM))
415 return;
416
417 old_pte = __ptep_get(ptep);
418
419 if (!pte_valid(old_pte) || !pte_valid(pte))
420 return;
421 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
422 return;
423
424 /*
425 * Check for potential race with hardware updates of the pte
426 * (__ptep_set_access_flags safely changes valid ptes without going
427 * through an invalid entry).
428 */
429 VM_WARN_ONCE(!pte_young(pte),
430 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
431 __func__, pte_val(old_pte), pte_val(pte));
432 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
433 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
434 __func__, pte_val(old_pte), pte_val(pte));
435 VM_WARN_ONCE(!pgattr_change_is_safe(pte_val(old_pte), pte_val(pte)),
436 "%s: unsafe attribute change: 0x%016llx -> 0x%016llx",
437 __func__, pte_val(old_pte), pte_val(pte));
438}
439
440static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages)
441{
442 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
443 __sync_icache_dcache(pte);
444
445 /*
446 * If the PTE would provide user space access to the tags associated
447 * with it then ensure that the MTE tags are synchronised. Although
448 * pte_access_permitted_no_overlay() returns false for exec only
449 * mappings, they don't expose tags (instruction fetches don't check
450 * tags).
451 */
452 if (system_supports_mte() && pte_access_permitted_no_overlay(pte, false) &&
453 !pte_special(pte) && pte_tagged(pte))
454 mte_sync_tags(pte, nr_pages);
455}
456
457/*
458 * Select all bits except the pfn
459 */
460#define pte_pgprot pte_pgprot
461static inline pgprot_t pte_pgprot(pte_t pte)
462{
463 unsigned long pfn = pte_pfn(pte);
464
465 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte));
466}
467
468#define pte_advance_pfn pte_advance_pfn
469static inline pte_t pte_advance_pfn(pte_t pte, unsigned long nr)
470{
471 return pfn_pte(pte_pfn(pte) + nr, pte_pgprot(pte));
472}
473
474/*
475 * Hugetlb definitions.
476 */
477#define HUGE_MAX_HSTATE 4
478#define HPAGE_SHIFT PMD_SHIFT
479#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
480#define HPAGE_MASK (~(HPAGE_SIZE - 1))
481#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
482
483static inline pte_t pgd_pte(pgd_t pgd)
484{
485 return __pte(pgd_val(pgd));
486}
487
488static inline pte_t p4d_pte(p4d_t p4d)
489{
490 return __pte(p4d_val(p4d));
491}
492
493static inline pte_t pud_pte(pud_t pud)
494{
495 return __pte(pud_val(pud));
496}
497
498static inline pud_t pte_pud(pte_t pte)
499{
500 return __pud(pte_val(pte));
501}
502
503static inline pmd_t pud_pmd(pud_t pud)
504{
505 return __pmd(pud_val(pud));
506}
507
508static inline pte_t pmd_pte(pmd_t pmd)
509{
510 return __pte(pmd_val(pmd));
511}
512
513static inline pmd_t pte_pmd(pte_t pte)
514{
515 return __pmd(pte_val(pte));
516}
517
518static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
519{
520 return __pgprot((pgprot_val(prot) & ~PUD_TYPE_MASK) | PUD_TYPE_SECT);
521}
522
523static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
524{
525 return __pgprot((pgprot_val(prot) & ~PMD_TYPE_MASK) | PMD_TYPE_SECT);
526}
527
528static inline pte_t pte_swp_mkexclusive(pte_t pte)
529{
530 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
531}
532
533static inline bool pte_swp_exclusive(pte_t pte)
534{
535 return pte_val(pte) & PTE_SWP_EXCLUSIVE;
536}
537
538static inline pte_t pte_swp_clear_exclusive(pte_t pte)
539{
540 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
541}
542
543#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
544static inline pte_t pte_swp_mkuffd(pte_t pte)
545{
546 return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD));
547}
548
549static inline int pte_swp_uffd(pte_t pte)
550{
551 return !!(pte_val(pte) & PTE_SWP_UFFD);
552}
553
554static inline pte_t pte_swp_clear_uffd(pte_t pte)
555{
556 return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD));
557}
558#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
559
560#ifdef CONFIG_ARCH_HAS_PTE_PROTNONE
561static inline int pte_protnone(pte_t pte)
562{
563 /*
564 * pte_present_invalid() tells us that the pte is invalid from HW
565 * perspective but present from SW perspective, so the fields are to be
566 * interpreted as per the HW layout. The second 2 checks are the unique
567 * encoding that we use for PROT_NONE. It is insufficient to only use
568 * the first check because we share the same encoding scheme with pmds
569 * which support pmd_mkinvalid(), so can be present-invalid without
570 * being PROT_NONE.
571 */
572 return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte);
573}
574
575static inline int pmd_protnone(pmd_t pmd)
576{
577 return pte_protnone(pmd_pte(pmd));
578}
579#endif /* CONFIG_ARCH_HAS_PTE_PROTNONE */
580
581#define pmd_present(pmd) pte_present(pmd_pte(pmd))
582#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
583#define pmd_young(pmd) pte_young(pmd_pte(pmd))
584#define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
585#define pmd_user(pmd) pte_user(pmd_pte(pmd))
586#define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd))
587#define pmd_cont(pmd) pte_cont(pmd_pte(pmd))
588#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
589#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
590#define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd)))
591#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
592#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
593#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
594#define pmd_mkvalid_k(pmd) pte_pmd(pte_mkvalid_k(pmd_pte(pmd)))
595#define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd)))
596#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
597#define pmd_uffd(pmd) pte_uffd(pmd_pte(pmd))
598#define pmd_mkuffd(pmd) pte_pmd(pte_mkuffd(pmd_pte(pmd)))
599#define pmd_clear_uffd(pmd) pte_pmd(pte_clear_uffd(pmd_pte(pmd)))
600#define pmd_swp_uffd(pmd) pte_swp_uffd(pmd_pte(pmd))
601#define pmd_swp_mkuffd(pmd) pte_pmd(pte_swp_mkuffd(pmd_pte(pmd)))
602#define pmd_swp_clear_uffd(pmd) \
603 pte_pmd(pte_swp_clear_uffd(pmd_pte(pmd)))
604#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
605
606#define pmd_write(pmd) pte_write(pmd_pte(pmd))
607
608static inline pmd_t pmd_mkhuge(pmd_t pmd)
609{
610 /*
611 * It's possible that the pmd is present-invalid on entry
612 * and in that case it needs to remain present-invalid on
613 * exit. So ensure the VALID bit does not get modified.
614 */
615 pmdval_t mask = PMD_TYPE_MASK & ~PTE_VALID;
616 pmdval_t val = PMD_TYPE_SECT & ~PTE_VALID;
617
618 return __pmd((pmd_val(pmd) & ~mask) | val);
619}
620
621#ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP
622#define pmd_special(pte) (!!((pmd_val(pte) & PTE_SPECIAL)))
623static inline pmd_t pmd_mkspecial(pmd_t pmd)
624{
625 return set_pmd_bit(pmd, __pgprot(PTE_SPECIAL));
626}
627#endif
628
629#define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
630#define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
631#define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
632#define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
633
634#define pud_young(pud) pte_young(pud_pte(pud))
635#define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
636#define pud_mkwrite_novma(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud)))
637#define pud_mkvalid_k(pud) pte_pud(pte_mkvalid_k(pud_pte(pud)))
638#define pud_write(pud) pte_write(pud_pte(pud))
639
640static inline pud_t pud_mkhuge(pud_t pud)
641{
642 /*
643 * It's possible that the pud is present-invalid on entry
644 * and in that case it needs to remain present-invalid on
645 * exit. So ensure the VALID bit does not get modified.
646 */
647 pudval_t mask = PUD_TYPE_MASK & ~PTE_VALID;
648 pudval_t val = PUD_TYPE_SECT & ~PTE_VALID;
649
650 return __pud((pud_val(pud) & ~mask) | val);
651}
652
653#define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
654#define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
655#define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
656#define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
657
658#define pmd_pgprot pmd_pgprot
659static inline pgprot_t pmd_pgprot(pmd_t pmd)
660{
661 unsigned long pfn = pmd_pfn(pmd);
662
663 return __pgprot(pmd_val(pfn_pmd(pfn, __pgprot(0))) ^ pmd_val(pmd));
664}
665
666#define pud_pgprot pud_pgprot
667static inline pgprot_t pud_pgprot(pud_t pud)
668{
669 unsigned long pfn = pud_pfn(pud);
670
671 return __pgprot(pud_val(pfn_pud(pfn, __pgprot(0))) ^ pud_val(pud));
672}
673
674static inline void __set_ptes_anysz(struct mm_struct *mm, unsigned long addr,
675 pte_t *ptep, pte_t pte, unsigned int nr,
676 unsigned long pgsize)
677{
678 unsigned long stride = pgsize >> PAGE_SHIFT;
679
680 switch (pgsize) {
681 case PAGE_SIZE:
682 page_table_check_ptes_set(mm, addr, ptep, pte, nr);
683 break;
684 case PMD_SIZE:
685 page_table_check_pmds_set(mm, addr, (pmd_t *)ptep,
686 pte_pmd(pte), nr);
687 break;
688#ifndef __PAGETABLE_PMD_FOLDED
689 case PUD_SIZE:
690 page_table_check_puds_set(mm, addr, (pud_t *)ptep,
691 pte_pud(pte), nr);
692 break;
693#endif
694 default:
695 VM_WARN_ON(1);
696 }
697
698 __sync_cache_and_tags(pte, nr * stride);
699
700 for (;;) {
701 __check_safe_pte_update(mm, ptep, pte);
702 __set_pte_nosync(ptep, pte);
703 if (--nr == 0)
704 break;
705 ptep++;
706 pte = pte_advance_pfn(pte, stride);
707 }
708
709 __set_pte_complete(pte);
710}
711
712static inline void __set_ptes(struct mm_struct *mm, unsigned long addr,
713 pte_t *ptep, pte_t pte, unsigned int nr)
714{
715 __set_ptes_anysz(mm, addr, ptep, pte, nr, PAGE_SIZE);
716}
717
718static inline void __set_pmds(struct mm_struct *mm, unsigned long addr,
719 pmd_t *pmdp, pmd_t pmd, unsigned int nr)
720{
721 __set_ptes_anysz(mm, addr, (pte_t *)pmdp, pmd_pte(pmd), nr, PMD_SIZE);
722}
723#define set_pmd_at(mm, addr, pmdp, pmd) __set_pmds(mm, addr, pmdp, pmd, 1)
724
725static inline void __set_puds(struct mm_struct *mm, unsigned long addr,
726 pud_t *pudp, pud_t pud, unsigned int nr)
727{
728 __set_ptes_anysz(mm, addr, (pte_t *)pudp, pud_pte(pud), nr, PUD_SIZE);
729}
730#define set_pud_at(mm, addr, pudp, pud) __set_puds(mm, addr, pudp, pud, 1)
731
732#define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
733#define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
734
735#define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
736#define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
737
738#define __pgprot_modify(prot,mask,bits) \
739 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
740
741#define pgprot_nx(prot) \
742 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
743
744#define pgprot_decrypted(prot) \
745 __pgprot_modify(prot, PROT_NS_SHARED, PROT_NS_SHARED)
746#define pgprot_encrypted(prot) \
747 __pgprot_modify(prot, PROT_NS_SHARED, 0)
748
749/*
750 * Mark the prot value as uncacheable and unbufferable.
751 */
752#define pgprot_noncached(prot) \
753 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
754#define pgprot_writecombine(prot) \
755 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
756#define pgprot_device(prot) \
757 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
758#define pgprot_tagged(prot) \
759 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
760#define pgprot_mhp pgprot_tagged
761/*
762 * DMA allocations for non-coherent devices use what the Arm architecture calls
763 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
764 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
765 * is intended for MMIO and thus forbids speculation, preserves access size,
766 * requires strict alignment and can also force write responses to come from the
767 * endpoint.
768 */
769#define pgprot_dmacoherent(prot) \
770 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
771 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
772
773#define __HAVE_PHYS_MEM_ACCESS_PROT
774struct file;
775extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
776 unsigned long size, pgprot_t vma_prot);
777
778#define pmd_none(pmd) (!pmd_val(pmd))
779
780#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
781 PMD_TYPE_TABLE)
782
783#define pmd_leaf pmd_leaf
784static inline bool pmd_leaf(pmd_t pmd)
785{
786 return pmd_present(pmd) && !pmd_table(pmd);
787}
788
789#define pmd_bad(pmd) (!pmd_table(pmd))
790
791#define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
792#define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
793
794#ifdef CONFIG_TRANSPARENT_HUGEPAGE
795static inline int pmd_trans_huge(pmd_t pmd)
796{
797 /*
798 * If pmd is present-invalid, pmd_table() won't detect it
799 * as a table, so force the valid bit for the comparison.
800 */
801 return pmd_present(pmd) && !pmd_table(__pmd(pmd_val(pmd) | PTE_VALID));
802}
803#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
804
805#if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
806static inline bool pud_table(pud_t pud) { return true; }
807#else
808#define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
809 PUD_TYPE_TABLE)
810#endif
811
812extern pgd_t swapper_pg_dir[];
813extern pgd_t idmap_pg_dir[];
814extern pgd_t tramp_pg_dir[];
815extern pgd_t reserved_pg_dir[];
816
817extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
818
819static inline bool in_swapper_pgdir(void *addr)
820{
821 return ((unsigned long)addr & PAGE_MASK) ==
822 ((unsigned long)swapper_pg_dir & PAGE_MASK);
823}
824
825static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
826{
827#ifdef __PAGETABLE_PMD_FOLDED
828 if (in_swapper_pgdir(pmdp)) {
829 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
830 return;
831 }
832#endif /* __PAGETABLE_PMD_FOLDED */
833
834 WRITE_ONCE(*pmdp, pmd);
835
836 if (pmd_valid(pmd))
837 queue_pte_barriers();
838}
839
840static inline void pmd_clear(pmd_t *pmdp)
841{
842 set_pmd(pmdp, __pmd(0));
843}
844
845static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
846{
847 return __pmd_to_phys(pmd);
848}
849
850static inline unsigned long pmd_page_vaddr(pmd_t pmd)
851{
852 return (unsigned long)__va(pmd_page_paddr(pmd));
853}
854
855/* Find an entry in the third-level page table. */
856#define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
857
858#define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
859#define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
860#define pte_clear_fixmap() clear_fixmap(FIX_PTE)
861
862#define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
863
864/* use ONLY for statically allocated translation tables */
865#define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
866
867#if CONFIG_PGTABLE_LEVELS > 2
868
869#define pmd_ERROR(e) \
870 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
871
872#define pud_none(pud) (!pud_val(pud))
873#define pud_bad(pud) ((pud_val(pud) & PUD_TYPE_MASK) != \
874 PUD_TYPE_TABLE)
875#define pud_present(pud) pte_present(pud_pte(pud))
876#ifndef __PAGETABLE_PMD_FOLDED
877#define pud_leaf pud_leaf
878static inline bool pud_leaf(pud_t pud)
879{
880 return pud_present(pud) && !pud_table(pud);
881}
882#else
883#define pud_leaf(pud) false
884#endif
885#define pud_valid(pud) pte_valid(pud_pte(pud))
886#define pud_user(pud) pte_user(pud_pte(pud))
887#define pud_user_exec(pud) pte_user_exec(pud_pte(pud))
888
889static inline bool pgtable_l4_enabled(void);
890
891static inline void set_pud(pud_t *pudp, pud_t pud)
892{
893 if (!pgtable_l4_enabled() && in_swapper_pgdir(pudp)) {
894 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
895 return;
896 }
897
898 WRITE_ONCE(*pudp, pud);
899
900 if (pud_valid(pud))
901 queue_pte_barriers();
902}
903
904static inline void pud_clear(pud_t *pudp)
905{
906 set_pud(pudp, __pud(0));
907}
908
909static inline phys_addr_t pud_page_paddr(pud_t pud)
910{
911 return __pud_to_phys(pud);
912}
913
914static inline pmd_t *pud_pgtable(pud_t pud)
915{
916 return (pmd_t *)__va(pud_page_paddr(pud));
917}
918
919/* Find an entry in the second-level page table. */
920#define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
921
922#define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
923#define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
924#define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
925
926#define pud_page(pud) phys_to_page(__pud_to_phys(pud))
927
928/* use ONLY for statically allocated translation tables */
929#define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
930
931#else
932
933#define pud_valid(pud) false
934#define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
935#define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */
936
937/* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
938#define pmd_set_fixmap(addr) NULL
939#define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
940#define pmd_clear_fixmap()
941
942#define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
943
944#endif /* CONFIG_PGTABLE_LEVELS > 2 */
945
946#if CONFIG_PGTABLE_LEVELS > 3
947
948static __always_inline bool pgtable_l4_enabled(void)
949{
950 if (CONFIG_PGTABLE_LEVELS > 4 || !IS_ENABLED(CONFIG_ARM64_LPA2))
951 return true;
952 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT))
953 return vabits_actual == VA_BITS;
954 return alternative_has_cap_unlikely(ARM64_HAS_VA52);
955}
956
957static inline bool mm_pud_folded(const struct mm_struct *mm)
958{
959 return !pgtable_l4_enabled();
960}
961#define mm_pud_folded mm_pud_folded
962
963#define pud_ERROR(e) \
964 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
965
966#define p4d_none(p4d) (pgtable_l4_enabled() && !p4d_val(p4d))
967#define p4d_bad(p4d) (pgtable_l4_enabled() && \
968 ((p4d_val(p4d) & P4D_TYPE_MASK) != \
969 P4D_TYPE_TABLE))
970#define p4d_present(p4d) (!p4d_none(p4d))
971
972static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
973{
974 if (in_swapper_pgdir(p4dp)) {
975 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
976 return;
977 }
978
979 WRITE_ONCE(*p4dp, p4d);
980 queue_pte_barriers();
981}
982
983static inline void p4d_clear(p4d_t *p4dp)
984{
985 if (pgtable_l4_enabled())
986 set_p4d(p4dp, __p4d(0));
987}
988
989static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
990{
991 return __p4d_to_phys(p4d);
992}
993
994#define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
995
996static inline pud_t *p4d_to_folded_pud(p4d_t *p4dp, unsigned long addr)
997{
998 /* Ensure that 'p4dp' indexes a page table according to 'addr' */
999 VM_BUG_ON(((addr >> P4D_SHIFT) ^ ((u64)p4dp >> 3)) % PTRS_PER_P4D);
1000
1001 return (pud_t *)PTR_ALIGN_DOWN(p4dp, PAGE_SIZE) + pud_index(addr);
1002}
1003
1004static inline pud_t *p4d_pgtable(p4d_t p4d)
1005{
1006 return (pud_t *)__va(p4d_page_paddr(p4d));
1007}
1008
1009static inline phys_addr_t pud_offset_phys(p4d_t *p4dp, unsigned long addr)
1010{
1011 VM_WARN_ON_ONCE(!pgtable_l4_enabled());
1012
1013 return p4d_page_paddr(READ_ONCE(*p4dp)) + pud_index(addr) * sizeof(pud_t);
1014}
1015
1016static inline
1017pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long addr)
1018{
1019 if (!pgtable_l4_enabled())
1020 return p4d_to_folded_pud(p4dp, addr);
1021 return (pud_t *)__va(p4d_page_paddr(p4d)) + pud_index(addr);
1022}
1023#define pud_offset_lockless pud_offset_lockless
1024
1025static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long addr)
1026{
1027 return pud_offset_lockless(p4dp, READ_ONCE(*p4dp), addr);
1028}
1029#define pud_offset pud_offset
1030
1031static inline pud_t *pud_set_fixmap(unsigned long addr)
1032{
1033 if (!pgtable_l4_enabled())
1034 return NULL;
1035 return (pud_t *)set_fixmap_offset(FIX_PUD, addr);
1036}
1037
1038static inline pud_t *pud_set_fixmap_offset(p4d_t *p4dp, unsigned long addr)
1039{
1040 if (!pgtable_l4_enabled())
1041 return p4d_to_folded_pud(p4dp, addr);
1042 return pud_set_fixmap(pud_offset_phys(p4dp, addr));
1043}
1044
1045static inline void pud_clear_fixmap(void)
1046{
1047 if (pgtable_l4_enabled())
1048 clear_fixmap(FIX_PUD);
1049}
1050
1051/* use ONLY for statically allocated translation tables */
1052static inline pud_t *pud_offset_kimg(p4d_t *p4dp, u64 addr)
1053{
1054 if (!pgtable_l4_enabled())
1055 return p4d_to_folded_pud(p4dp, addr);
1056 return (pud_t *)__phys_to_kimg(pud_offset_phys(p4dp, addr));
1057}
1058
1059#define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
1060
1061#else
1062
1063static inline bool pgtable_l4_enabled(void) { return false; }
1064
1065#define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
1066
1067/* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
1068#define pud_set_fixmap(addr) NULL
1069#define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
1070#define pud_clear_fixmap()
1071
1072#define pud_offset_kimg(dir,addr) ((pud_t *)dir)
1073
1074#endif /* CONFIG_PGTABLE_LEVELS > 3 */
1075
1076#if CONFIG_PGTABLE_LEVELS > 4
1077
1078static __always_inline bool pgtable_l5_enabled(void)
1079{
1080 if (!alternative_has_cap_likely(ARM64_ALWAYS_BOOT))
1081 return vabits_actual == VA_BITS;
1082 return alternative_has_cap_unlikely(ARM64_HAS_VA52);
1083}
1084
1085static inline bool mm_p4d_folded(const struct mm_struct *mm)
1086{
1087 return !pgtable_l5_enabled();
1088}
1089#define mm_p4d_folded mm_p4d_folded
1090
1091#define p4d_ERROR(e) \
1092 pr_err("%s:%d: bad p4d %016llx.\n", __FILE__, __LINE__, p4d_val(e))
1093
1094#define pgd_none(pgd) (pgtable_l5_enabled() && !pgd_val(pgd))
1095#define pgd_bad(pgd) (pgtable_l5_enabled() && \
1096 ((pgd_val(pgd) & PGD_TYPE_MASK) != \
1097 PGD_TYPE_TABLE))
1098#define pgd_present(pgd) (!pgd_none(pgd))
1099
1100static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
1101{
1102 if (in_swapper_pgdir(pgdp)) {
1103 set_swapper_pgd(pgdp, __pgd(pgd_val(pgd)));
1104 return;
1105 }
1106
1107 WRITE_ONCE(*pgdp, pgd);
1108 queue_pte_barriers();
1109}
1110
1111static inline void pgd_clear(pgd_t *pgdp)
1112{
1113 if (pgtable_l5_enabled())
1114 set_pgd(pgdp, __pgd(0));
1115}
1116
1117static inline phys_addr_t pgd_page_paddr(pgd_t pgd)
1118{
1119 return __pgd_to_phys(pgd);
1120}
1121
1122#define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1))
1123
1124static inline p4d_t *pgd_to_folded_p4d(pgd_t *pgdp, unsigned long addr)
1125{
1126 /* Ensure that 'pgdp' indexes a page table according to 'addr' */
1127 VM_BUG_ON(((addr >> PGDIR_SHIFT) ^ ((u64)pgdp >> 3)) % PTRS_PER_PGD);
1128
1129 return (p4d_t *)PTR_ALIGN_DOWN(pgdp, PAGE_SIZE) + p4d_index(addr);
1130}
1131
1132static inline phys_addr_t p4d_offset_phys(pgd_t *pgdp, unsigned long addr)
1133{
1134 VM_WARN_ON_ONCE(!pgtable_l5_enabled());
1135
1136 return pgd_page_paddr(READ_ONCE(*pgdp)) + p4d_index(addr) * sizeof(p4d_t);
1137}
1138
1139static inline
1140p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long addr)
1141{
1142 if (!pgtable_l5_enabled())
1143 return pgd_to_folded_p4d(pgdp, addr);
1144 return (p4d_t *)__va(pgd_page_paddr(pgd)) + p4d_index(addr);
1145}
1146#define p4d_offset_lockless p4d_offset_lockless
1147
1148static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long addr)
1149{
1150 return p4d_offset_lockless(pgdp, READ_ONCE(*pgdp), addr);
1151}
1152
1153static inline p4d_t *p4d_set_fixmap(unsigned long addr)
1154{
1155 if (!pgtable_l5_enabled())
1156 return NULL;
1157 return (p4d_t *)set_fixmap_offset(FIX_P4D, addr);
1158}
1159
1160static inline p4d_t *p4d_set_fixmap_offset(pgd_t *pgdp, unsigned long addr)
1161{
1162 if (!pgtable_l5_enabled())
1163 return pgd_to_folded_p4d(pgdp, addr);
1164 return p4d_set_fixmap(p4d_offset_phys(pgdp, addr));
1165}
1166
1167static inline void p4d_clear_fixmap(void)
1168{
1169 if (pgtable_l5_enabled())
1170 clear_fixmap(FIX_P4D);
1171}
1172
1173/* use ONLY for statically allocated translation tables */
1174static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr)
1175{
1176 if (!pgtable_l5_enabled())
1177 return pgd_to_folded_p4d(pgdp, addr);
1178 return (p4d_t *)__phys_to_kimg(p4d_offset_phys(pgdp, addr));
1179}
1180
1181#define pgd_page(pgd) pfn_to_page(__phys_to_pfn(__pgd_to_phys(pgd)))
1182
1183#else
1184
1185static inline bool pgtable_l5_enabled(void) { return false; }
1186
1187#define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1))
1188
1189/* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */
1190#define p4d_set_fixmap(addr) NULL
1191#define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp)
1192#define p4d_clear_fixmap()
1193
1194#define p4d_offset_kimg(dir,addr) ((p4d_t *)dir)
1195
1196static inline
1197p4d_t *p4d_offset_lockless_folded(pgd_t *pgdp, pgd_t pgd, unsigned long addr)
1198{
1199 /*
1200 * With runtime folding of the pud, pud_offset_lockless() passes
1201 * the 'pgd_t *' we return here to p4d_to_folded_pud(), which
1202 * will offset the pointer assuming that it points into
1203 * a page-table page. However, the fast GUP path passes us a
1204 * pgd_t allocated on the stack and so we must use the original
1205 * pointer in 'pgdp' to construct the p4d pointer instead of
1206 * using the generic p4d_offset_lockless() implementation.
1207 *
1208 * Note: reusing the original pointer means that we may
1209 * dereference the same (live) page-table entry multiple times.
1210 * This is safe because it is still only loaded once in the
1211 * context of each level and the CPU guarantees same-address
1212 * read-after-read ordering.
1213 */
1214 return p4d_offset(pgdp, addr);
1215}
1216#define p4d_offset_lockless p4d_offset_lockless_folded
1217
1218#endif /* CONFIG_PGTABLE_LEVELS > 4 */
1219
1220#define pgd_ERROR(e) \
1221 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
1222
1223#define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
1224#define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
1225
1226static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1227{
1228 /*
1229 * Normal and Normal-Tagged are two different memory types and indices
1230 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
1231 */
1232 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
1233 PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE |
1234 PTE_GP | PTE_ATTRINDX_MASK | PTE_PO_IDX_MASK;
1235
1236 /* preserve the hardware dirty information */
1237 if (pte_hw_dirty(pte))
1238 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
1239
1240 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
1241 /*
1242 * If we end up clearing hw dirtiness for a sw-dirty PTE, set hardware
1243 * dirtiness again.
1244 */
1245 if (pte_sw_dirty(pte))
1246 pte = pte_mkdirty(pte);
1247 return pte;
1248}
1249
1250static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1251{
1252 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
1253}
1254
1255extern int __ptep_set_access_flags_anysz(struct vm_area_struct *vma,
1256 unsigned long address, pte_t *ptep,
1257 pte_t entry, int dirty,
1258 unsigned long pgsize);
1259
1260static inline int __ptep_set_access_flags(struct vm_area_struct *vma,
1261 unsigned long address, pte_t *ptep,
1262 pte_t entry, int dirty)
1263{
1264 return __ptep_set_access_flags_anysz(vma, address, ptep, entry, dirty,
1265 PAGE_SIZE);
1266}
1267
1268#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1269#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1270static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
1271 unsigned long address, pmd_t *pmdp,
1272 pmd_t entry, int dirty)
1273{
1274 return __ptep_set_access_flags_anysz(vma, address, (pte_t *)pmdp,
1275 pmd_pte(entry), dirty, PMD_SIZE);
1276}
1277#endif
1278
1279#ifdef CONFIG_PAGE_TABLE_CHECK
1280static inline bool pte_user_accessible_page(struct mm_struct *mm, unsigned long addr, pte_t pte)
1281{
1282 return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte));
1283}
1284
1285static inline bool pmd_user_accessible_page(struct mm_struct *mm, unsigned long addr, pmd_t pmd)
1286{
1287 return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd));
1288}
1289
1290static inline bool pud_user_accessible_page(struct mm_struct *mm, unsigned long addr, pud_t pud)
1291{
1292 return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud));
1293}
1294#endif
1295
1296/*
1297 * Atomic pte/pmd modifications.
1298 */
1299
1300static inline void __pte_clear(struct mm_struct *mm,
1301 unsigned long addr, pte_t *ptep)
1302{
1303 __set_pte(ptep, __pte(0));
1304}
1305
1306static inline bool __ptep_test_and_clear_young(struct vm_area_struct *vma,
1307 unsigned long address, pte_t *ptep)
1308{
1309 pte_t old_pte, pte;
1310
1311 pte = __ptep_get(ptep);
1312 do {
1313 old_pte = pte;
1314 pte = pte_mkold(pte);
1315 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
1316 pte_val(old_pte), pte_val(pte));
1317 } while (pte_val(pte) != pte_val(old_pte));
1318
1319 return pte_young(pte);
1320}
1321
1322static inline bool __ptep_clear_flush_young(struct vm_area_struct *vma,
1323 unsigned long address, pte_t *ptep)
1324{
1325 bool young = __ptep_test_and_clear_young(vma, address, ptep);
1326
1327 if (young) {
1328 /*
1329 * We can elide the trailing DSB here since the worst that can
1330 * happen is that a CPU continues to use the young entry in its
1331 * TLB and we mistakenly reclaim the associated page. The
1332 * window for such an event is bounded by the next
1333 * context-switch, which provides a DSB to complete the TLB
1334 * invalidation.
1335 */
1336 __flush_tlb_page(vma, address, TLBF_NOSYNC);
1337 }
1338
1339 return young;
1340}
1341
1342#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG)
1343#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1344static inline bool pmdp_test_and_clear_young(struct vm_area_struct *vma,
1345 unsigned long address, pmd_t *pmdp)
1346{
1347 /* Operation applies to PMD table entry only if FEAT_HAFT is enabled */
1348 VM_WARN_ON(pmd_table(READ_ONCE(*pmdp)) && !system_supports_haft());
1349 return __ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
1350}
1351#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG */
1352
1353static inline pte_t __ptep_get_and_clear_anysz(struct mm_struct *mm,
1354 unsigned long address,
1355 pte_t *ptep,
1356 unsigned long pgsize)
1357{
1358 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0));
1359
1360 switch (pgsize) {
1361 case PAGE_SIZE:
1362 page_table_check_pte_clear(mm, address, pte);
1363 break;
1364 case PMD_SIZE:
1365 page_table_check_pmd_clear(mm, address, pte_pmd(pte));
1366 break;
1367#ifndef __PAGETABLE_PMD_FOLDED
1368 case PUD_SIZE:
1369 page_table_check_pud_clear(mm, address, pte_pud(pte));
1370 break;
1371#endif
1372 default:
1373 VM_WARN_ON(1);
1374 }
1375
1376 return pte;
1377}
1378
1379static inline pte_t __ptep_get_and_clear(struct mm_struct *mm,
1380 unsigned long address, pte_t *ptep)
1381{
1382 return __ptep_get_and_clear_anysz(mm, address, ptep, PAGE_SIZE);
1383}
1384
1385static inline void __clear_full_ptes(struct mm_struct *mm, unsigned long addr,
1386 pte_t *ptep, unsigned int nr, int full)
1387{
1388 for (;;) {
1389 __ptep_get_and_clear(mm, addr, ptep);
1390 if (--nr == 0)
1391 break;
1392 ptep++;
1393 addr += PAGE_SIZE;
1394 }
1395}
1396
1397static inline pte_t __get_and_clear_full_ptes(struct mm_struct *mm,
1398 unsigned long addr, pte_t *ptep,
1399 unsigned int nr, int full)
1400{
1401 pte_t pte, tmp_pte;
1402
1403 pte = __ptep_get_and_clear(mm, addr, ptep);
1404 while (--nr) {
1405 ptep++;
1406 addr += PAGE_SIZE;
1407 tmp_pte = __ptep_get_and_clear(mm, addr, ptep);
1408 if (pte_dirty(tmp_pte))
1409 pte = pte_mkdirty(pte);
1410 if (pte_young(tmp_pte))
1411 pte = pte_mkyoung(pte);
1412 }
1413 return pte;
1414}
1415
1416#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1417#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1418static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1419 unsigned long address, pmd_t *pmdp)
1420{
1421 return pte_pmd(__ptep_get_and_clear_anysz(mm, address, (pte_t *)pmdp, PMD_SIZE));
1422}
1423#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1424
1425static inline void ___ptep_set_wrprotect(struct mm_struct *mm,
1426 unsigned long address, pte_t *ptep,
1427 pte_t pte)
1428{
1429 pte_t old_pte;
1430
1431 do {
1432 old_pte = pte;
1433 pte = pte_wrprotect(pte);
1434 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
1435 pte_val(old_pte), pte_val(pte));
1436 } while (pte_val(pte) != pte_val(old_pte));
1437}
1438
1439/*
1440 * __ptep_set_wrprotect - mark read-only while transferring potential hardware
1441 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
1442 */
1443static inline void __ptep_set_wrprotect(struct mm_struct *mm,
1444 unsigned long address, pte_t *ptep)
1445{
1446 ___ptep_set_wrprotect(mm, address, ptep, __ptep_get(ptep));
1447}
1448
1449static inline void __wrprotect_ptes(struct mm_struct *mm, unsigned long address,
1450 pte_t *ptep, unsigned int nr)
1451{
1452 unsigned int i;
1453
1454 for (i = 0; i < nr; i++, address += PAGE_SIZE, ptep++)
1455 __ptep_set_wrprotect(mm, address, ptep);
1456}
1457
1458static inline void __clear_young_dirty_pte(struct vm_area_struct *vma,
1459 unsigned long addr, pte_t *ptep,
1460 pte_t pte, cydp_t flags)
1461{
1462 pte_t old_pte;
1463
1464 do {
1465 old_pte = pte;
1466
1467 if (flags & CYDP_CLEAR_YOUNG)
1468 pte = pte_mkold(pte);
1469 if (flags & CYDP_CLEAR_DIRTY)
1470 pte = pte_mkclean(pte);
1471
1472 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
1473 pte_val(old_pte), pte_val(pte));
1474 } while (pte_val(pte) != pte_val(old_pte));
1475}
1476
1477static inline void __clear_young_dirty_ptes(struct vm_area_struct *vma,
1478 unsigned long addr, pte_t *ptep,
1479 unsigned int nr, cydp_t flags)
1480{
1481 pte_t pte;
1482
1483 for (;;) {
1484 pte = __ptep_get(ptep);
1485
1486 if (flags == (CYDP_CLEAR_YOUNG | CYDP_CLEAR_DIRTY))
1487 __set_pte(ptep, pte_mkclean(pte_mkold(pte)));
1488 else
1489 __clear_young_dirty_pte(vma, addr, ptep, pte, flags);
1490
1491 if (--nr == 0)
1492 break;
1493 ptep++;
1494 addr += PAGE_SIZE;
1495 }
1496}
1497
1498#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1499#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1500static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1501 unsigned long address, pmd_t *pmdp)
1502{
1503 __ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
1504}
1505
1506#define pmdp_establish pmdp_establish
1507static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
1508 unsigned long address, pmd_t *pmdp, pmd_t pmd)
1509{
1510 page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd);
1511 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
1512}
1513#endif
1514
1515/*
1516 * Encode and decode a swap entry:
1517 * bits 0-1: present (must be zero)
1518 * bits 2: remember PG_anon_exclusive
1519 * bit 3: remember uffd state
1520 * bits 6-10: swap type
1521 * bit 11: PTE_PRESENT_INVALID (must be zero)
1522 * bits 12-61: swap offset
1523 */
1524#define __SWP_TYPE_SHIFT 6
1525#define __SWP_TYPE_BITS 5
1526#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
1527#define __SWP_OFFSET_SHIFT 12
1528#define __SWP_OFFSET_BITS 50
1529#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
1530
1531#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
1532#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
1533#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
1534
1535#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1536#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
1537
1538#ifdef CONFIG_ARCH_HAS_PMD_SOFTLEAVES
1539#define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
1540#define __swp_entry_to_pmd(swp) __pmd((swp).val)
1541#endif /* CONFIG_ARCH_HAS_PMD_SOFTLEAVES */
1542
1543/*
1544 * Ensure that there are not more swap files than can be encoded in the kernel
1545 * PTEs.
1546 */
1547#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
1548
1549#ifdef CONFIG_ARM64_MTE
1550
1551#define __HAVE_ARCH_PREPARE_TO_SWAP
1552extern int arch_prepare_to_swap(struct folio *folio);
1553
1554#define __HAVE_ARCH_SWAP_INVALIDATE
1555static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
1556{
1557 if (system_supports_mte())
1558 mte_invalidate_tags(type, offset);
1559}
1560
1561static inline void arch_swap_invalidate_area(int type)
1562{
1563 if (system_supports_mte())
1564 mte_invalidate_tags_area(type);
1565}
1566
1567#define __HAVE_ARCH_SWAP_RESTORE
1568extern void arch_swap_restore(swp_entry_t entry, struct folio *folio);
1569
1570#endif /* CONFIG_ARM64_MTE */
1571
1572/*
1573 * On AArch64, the cache coherency is handled via the __set_ptes() function.
1574 */
1575static inline void update_mmu_cache_range(struct vm_fault *vmf,
1576 struct vm_area_struct *vma, unsigned long addr, pte_t *ptep,
1577 unsigned int nr)
1578{
1579 /*
1580 * We don't do anything here, so there's a very small chance of
1581 * us retaking a user fault which we just fixed up. The alternative
1582 * is doing a dsb(ishst), but that penalises the fastpath.
1583 */
1584}
1585
1586#define update_mmu_cache(vma, addr, ptep) \
1587 update_mmu_cache_range(NULL, vma, addr, ptep, 1)
1588#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
1589
1590#ifdef CONFIG_ARM64_PA_BITS_52
1591#define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
1592#else
1593#define phys_to_ttbr(addr) (addr)
1594#endif
1595
1596/*
1597 * On arm64 without hardware Access Flag, copying from user will fail because
1598 * the pte is old and cannot be marked young. So we always end up with zeroed
1599 * page after fork() + CoW for pfn mappings. We don't always have a
1600 * hardware-managed access flag on arm64.
1601 */
1602#define arch_has_hw_pte_young cpu_has_hw_af
1603
1604#ifdef CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG
1605#define arch_has_hw_nonleaf_pmd_young system_supports_haft
1606#endif
1607
1608/*
1609 * Experimentally, it's cheap to set the access flag in hardware and we
1610 * benefit from prefaulting mappings as 'old' to start with.
1611 */
1612#define arch_wants_old_prefaulted_pte cpu_has_hw_af
1613
1614/*
1615 * Request exec memory is read into pagecache in at least 64K folios. This size
1616 * can be contpte-mapped when 4K base pages are in use (16 pages into 1 iTLB
1617 * entry), and HPA can coalesce it (4 pages into 1 TLB entry) when 16K base
1618 * pages are in use.
1619 */
1620#define exec_folio_order() ilog2(SZ_64K >> PAGE_SHIFT)
1621
1622static inline bool pud_sect_supported(void)
1623{
1624 return PAGE_SIZE == SZ_4K;
1625}
1626
1627
1628#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1629#define ptep_modify_prot_start ptep_modify_prot_start
1630extern pte_t ptep_modify_prot_start(struct vm_area_struct *vma,
1631 unsigned long addr, pte_t *ptep);
1632
1633#define ptep_modify_prot_commit ptep_modify_prot_commit
1634extern void ptep_modify_prot_commit(struct vm_area_struct *vma,
1635 unsigned long addr, pte_t *ptep,
1636 pte_t old_pte, pte_t new_pte);
1637
1638#define modify_prot_start_ptes modify_prot_start_ptes
1639extern pte_t modify_prot_start_ptes(struct vm_area_struct *vma,
1640 unsigned long addr, pte_t *ptep,
1641 unsigned int nr);
1642
1643#define modify_prot_commit_ptes modify_prot_commit_ptes
1644extern void modify_prot_commit_ptes(struct vm_area_struct *vma, unsigned long addr,
1645 pte_t *ptep, pte_t old_pte, pte_t pte,
1646 unsigned int nr);
1647
1648#ifdef CONFIG_ARM64_CONTPTE
1649
1650/*
1651 * The contpte APIs are used to transparently manage the contiguous bit in ptes
1652 * where it is possible and makes sense to do so. The PTE_CONT bit is considered
1653 * a private implementation detail of the public ptep API (see below).
1654 */
1655extern void __contpte_try_fold(struct mm_struct *mm, unsigned long addr,
1656 pte_t *ptep, pte_t pte);
1657extern void __contpte_try_unfold(struct mm_struct *mm, unsigned long addr,
1658 pte_t *ptep, pte_t pte);
1659extern pte_t contpte_ptep_get(pte_t *ptep, pte_t orig_pte);
1660extern pte_t contpte_ptep_get_lockless(pte_t *orig_ptep);
1661extern void contpte_set_ptes(struct mm_struct *mm, unsigned long addr,
1662 pte_t *ptep, pte_t pte, unsigned int nr);
1663extern void contpte_clear_full_ptes(struct mm_struct *mm, unsigned long addr,
1664 pte_t *ptep, unsigned int nr, int full);
1665extern pte_t contpte_get_and_clear_full_ptes(struct mm_struct *mm,
1666 unsigned long addr, pte_t *ptep,
1667 unsigned int nr, int full);
1668bool contpte_test_and_clear_young_ptes(struct vm_area_struct *vma,
1669 unsigned long addr, pte_t *ptep, unsigned int nr);
1670bool contpte_clear_flush_young_ptes(struct vm_area_struct *vma,
1671 unsigned long addr, pte_t *ptep, unsigned int nr);
1672extern void contpte_wrprotect_ptes(struct mm_struct *mm, unsigned long addr,
1673 pte_t *ptep, unsigned int nr);
1674extern int contpte_ptep_set_access_flags(struct vm_area_struct *vma,
1675 unsigned long addr, pte_t *ptep,
1676 pte_t entry, int dirty);
1677extern void contpte_clear_young_dirty_ptes(struct vm_area_struct *vma,
1678 unsigned long addr, pte_t *ptep,
1679 unsigned int nr, cydp_t flags);
1680
1681static __always_inline void contpte_try_fold(struct mm_struct *mm,
1682 unsigned long addr, pte_t *ptep, pte_t pte)
1683{
1684 /*
1685 * Only bother trying if both the virtual and physical addresses are
1686 * aligned and correspond to the last entry in a contig range. The core
1687 * code mostly modifies ranges from low to high, so this is the likely
1688 * the last modification in the contig range, so a good time to fold.
1689 * We can't fold special mappings, because there is no associated folio.
1690 */
1691
1692 const unsigned long contmask = CONT_PTES - 1;
1693 bool valign = ((addr >> PAGE_SHIFT) & contmask) == contmask;
1694
1695 if (unlikely(valign)) {
1696 bool palign = (pte_pfn(pte) & contmask) == contmask;
1697
1698 if (unlikely(palign &&
1699 pte_valid(pte) && !pte_cont(pte) && !pte_special(pte)))
1700 __contpte_try_fold(mm, addr, ptep, pte);
1701 }
1702}
1703
1704static __always_inline void contpte_try_unfold(struct mm_struct *mm,
1705 unsigned long addr, pte_t *ptep, pte_t pte)
1706{
1707 if (unlikely(pte_valid_cont(pte)))
1708 __contpte_try_unfold(mm, addr, ptep, pte);
1709}
1710
1711#define pte_batch_hint pte_batch_hint
1712static inline unsigned int pte_batch_hint(pte_t *ptep, pte_t pte)
1713{
1714 if (!pte_valid_cont(pte))
1715 return 1;
1716
1717 return CONT_PTES - (((unsigned long)ptep >> 3) & (CONT_PTES - 1));
1718}
1719
1720/*
1721 * The below functions constitute the public API that arm64 presents to the
1722 * core-mm to manipulate PTE entries within their page tables (or at least this
1723 * is the subset of the API that arm64 needs to implement). These public
1724 * versions will automatically and transparently apply the contiguous bit where
1725 * it makes sense to do so. Therefore any users that are contig-aware (e.g.
1726 * hugetlb, kernel mapper) should NOT use these APIs, but instead use the
1727 * private versions, which are prefixed with double underscore. All of these
1728 * APIs except for ptep_get_lockless() are expected to be called with the PTL
1729 * held. Although the contiguous bit is considered private to the
1730 * implementation, it is deliberately allowed to leak through the getters (e.g.
1731 * ptep_get()), back to core code. This is required so that pte_leaf_size() can
1732 * provide an accurate size for perf_get_pgtable_size(). But this leakage means
1733 * its possible a pte will be passed to a setter with the contiguous bit set, so
1734 * we explicitly clear the contiguous bit in those cases to prevent accidentally
1735 * setting it in the pgtable.
1736 */
1737
1738#define ptep_get ptep_get
1739static inline pte_t ptep_get(pte_t *ptep)
1740{
1741 pte_t pte = __ptep_get(ptep);
1742
1743 if (likely(!pte_valid_cont(pte)))
1744 return pte;
1745
1746 return contpte_ptep_get(ptep, pte);
1747}
1748
1749#define ptep_get_lockless ptep_get_lockless
1750static inline pte_t ptep_get_lockless(pte_t *ptep)
1751{
1752 pte_t pte = __ptep_get(ptep);
1753
1754 if (likely(!pte_valid_cont(pte)))
1755 return pte;
1756
1757 return contpte_ptep_get_lockless(ptep);
1758}
1759
1760static inline void set_pte(pte_t *ptep, pte_t pte)
1761{
1762 /*
1763 * We don't have the mm or vaddr so cannot unfold contig entries (since
1764 * it requires tlb maintenance). set_pte() is not used in core code, so
1765 * this should never even be called. Regardless do our best to service
1766 * any call and emit a warning if there is any attempt to set a pte on
1767 * top of an existing contig range.
1768 */
1769 pte_t orig_pte = __ptep_get(ptep);
1770
1771 WARN_ON_ONCE(pte_valid_cont(orig_pte));
1772 __set_pte(ptep, pte_mknoncont(pte));
1773}
1774
1775#define set_ptes set_ptes
1776static __always_inline void set_ptes(struct mm_struct *mm, unsigned long addr,
1777 pte_t *ptep, pte_t pte, unsigned int nr)
1778{
1779 pte = pte_mknoncont(pte);
1780
1781 if (likely(nr == 1)) {
1782 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep));
1783 __set_ptes(mm, addr, ptep, pte, 1);
1784 contpte_try_fold(mm, addr, ptep, pte);
1785 } else {
1786 contpte_set_ptes(mm, addr, ptep, pte, nr);
1787 }
1788}
1789
1790static inline void pte_clear(struct mm_struct *mm,
1791 unsigned long addr, pte_t *ptep)
1792{
1793 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep));
1794 __pte_clear(mm, addr, ptep);
1795}
1796
1797#define clear_full_ptes clear_full_ptes
1798static inline void clear_full_ptes(struct mm_struct *mm, unsigned long addr,
1799 pte_t *ptep, unsigned int nr, int full)
1800{
1801 if (likely(nr == 1)) {
1802 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep));
1803 __clear_full_ptes(mm, addr, ptep, nr, full);
1804 } else {
1805 contpte_clear_full_ptes(mm, addr, ptep, nr, full);
1806 }
1807}
1808
1809#define get_and_clear_full_ptes get_and_clear_full_ptes
1810static inline pte_t get_and_clear_full_ptes(struct mm_struct *mm,
1811 unsigned long addr, pte_t *ptep,
1812 unsigned int nr, int full)
1813{
1814 pte_t pte;
1815
1816 if (likely(nr == 1)) {
1817 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep));
1818 pte = __get_and_clear_full_ptes(mm, addr, ptep, nr, full);
1819 } else {
1820 pte = contpte_get_and_clear_full_ptes(mm, addr, ptep, nr, full);
1821 }
1822
1823 return pte;
1824}
1825
1826#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1827static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1828 unsigned long addr, pte_t *ptep)
1829{
1830 contpte_try_unfold(mm, addr, ptep, __ptep_get(ptep));
1831 return __ptep_get_and_clear(mm, addr, ptep);
1832}
1833
1834static inline bool ptep_try_set(pte_t *ptep, pte_t new_pte)
1835{
1836 pteval_t old = 0;
1837
1838 if (!try_cmpxchg(&pte_val(*ptep), &old, pte_val(new_pte)))
1839 return false;
1840
1841 /*
1842 * The store must be complete by the time this returns, but the caller
1843 * may be in lazy MMU mode, where __set_pte_complete() would defer the
1844 * barriers. Issue them directly.
1845 */
1846 emit_pte_barriers();
1847 return true;
1848}
1849#define ptep_try_set ptep_try_set
1850
1851/*
1852 * arm64 mandates break-before-make: a cleared kernel PTE must have its TLB
1853 * invalidated before a different page is installed in its place. The broadcast
1854 * TLBI is an instruction, not an IPI, so this is safe with interrupts disabled.
1855 */
1856static inline void flush_tlb_before_set(unsigned long addr)
1857{
1858 flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
1859}
1860#define flush_tlb_before_set flush_tlb_before_set
1861
1862#define test_and_clear_young_ptes test_and_clear_young_ptes
1863static inline bool test_and_clear_young_ptes(struct vm_area_struct *vma,
1864 unsigned long addr, pte_t *ptep, unsigned int nr)
1865{
1866 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep))))
1867 return __ptep_test_and_clear_young(vma, addr, ptep);
1868
1869 return contpte_test_and_clear_young_ptes(vma, addr, ptep, nr);
1870}
1871
1872#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1873static inline bool ptep_test_and_clear_young(struct vm_area_struct *vma,
1874 unsigned long addr, pte_t *ptep)
1875{
1876 return test_and_clear_young_ptes(vma, addr, ptep, 1);
1877}
1878
1879#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1880static inline bool ptep_clear_flush_young(struct vm_area_struct *vma,
1881 unsigned long addr, pte_t *ptep)
1882{
1883 pte_t orig_pte = __ptep_get(ptep);
1884
1885 if (likely(!pte_valid_cont(orig_pte)))
1886 return __ptep_clear_flush_young(vma, addr, ptep);
1887
1888 return contpte_clear_flush_young_ptes(vma, addr, ptep, 1);
1889}
1890
1891#define clear_flush_young_ptes clear_flush_young_ptes
1892static inline bool clear_flush_young_ptes(struct vm_area_struct *vma,
1893 unsigned long addr, pte_t *ptep, unsigned int nr)
1894{
1895 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep))))
1896 return __ptep_clear_flush_young(vma, addr, ptep);
1897
1898 return contpte_clear_flush_young_ptes(vma, addr, ptep, nr);
1899}
1900
1901#define wrprotect_ptes wrprotect_ptes
1902static __always_inline void wrprotect_ptes(struct mm_struct *mm,
1903 unsigned long addr, pte_t *ptep, unsigned int nr)
1904{
1905 if (likely(nr == 1)) {
1906 /*
1907 * Optimization: wrprotect_ptes() can only be called for present
1908 * ptes so we only need to check contig bit as condition for
1909 * unfold, and we can remove the contig bit from the pte we read
1910 * to avoid re-reading. This speeds up fork() which is sensitive
1911 * for order-0 folios. Equivalent to contpte_try_unfold().
1912 */
1913 pte_t orig_pte = __ptep_get(ptep);
1914
1915 if (unlikely(pte_cont(orig_pte))) {
1916 __contpte_try_unfold(mm, addr, ptep, orig_pte);
1917 orig_pte = pte_mknoncont(orig_pte);
1918 }
1919 ___ptep_set_wrprotect(mm, addr, ptep, orig_pte);
1920 } else {
1921 contpte_wrprotect_ptes(mm, addr, ptep, nr);
1922 }
1923}
1924
1925#define __HAVE_ARCH_PTEP_SET_WRPROTECT
1926static inline void ptep_set_wrprotect(struct mm_struct *mm,
1927 unsigned long addr, pte_t *ptep)
1928{
1929 wrprotect_ptes(mm, addr, ptep, 1);
1930}
1931
1932#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1933static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1934 unsigned long addr, pte_t *ptep,
1935 pte_t entry, int dirty)
1936{
1937 pte_t orig_pte = __ptep_get(ptep);
1938
1939 entry = pte_mknoncont(entry);
1940
1941 if (likely(!pte_valid_cont(orig_pte)))
1942 return __ptep_set_access_flags(vma, addr, ptep, entry, dirty);
1943
1944 return contpte_ptep_set_access_flags(vma, addr, ptep, entry, dirty);
1945}
1946
1947#define clear_young_dirty_ptes clear_young_dirty_ptes
1948static inline void clear_young_dirty_ptes(struct vm_area_struct *vma,
1949 unsigned long addr, pte_t *ptep,
1950 unsigned int nr, cydp_t flags)
1951{
1952 if (likely(nr == 1 && !pte_cont(__ptep_get(ptep))))
1953 __clear_young_dirty_ptes(vma, addr, ptep, nr, flags);
1954 else
1955 contpte_clear_young_dirty_ptes(vma, addr, ptep, nr, flags);
1956}
1957
1958#else /* CONFIG_ARM64_CONTPTE */
1959
1960#define ptep_get __ptep_get
1961#define set_pte __set_pte
1962#define set_ptes __set_ptes
1963#define pte_clear __pte_clear
1964#define clear_full_ptes __clear_full_ptes
1965#define get_and_clear_full_ptes __get_and_clear_full_ptes
1966#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1967#define ptep_get_and_clear __ptep_get_and_clear
1968#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1969#define ptep_test_and_clear_young __ptep_test_and_clear_young
1970#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1971#define ptep_clear_flush_young __ptep_clear_flush_young
1972#define __HAVE_ARCH_PTEP_SET_WRPROTECT
1973#define ptep_set_wrprotect __ptep_set_wrprotect
1974#define wrprotect_ptes __wrprotect_ptes
1975#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1976#define ptep_set_access_flags __ptep_set_access_flags
1977#define clear_young_dirty_ptes __clear_young_dirty_ptes
1978
1979#endif /* CONFIG_ARM64_CONTPTE */
1980
1981#endif /* !__ASSEMBLER__ */
1982
1983#endif /* __ASM_PGTABLE_H */