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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/processor.h
4 *
5 * Copyright (C) 1995-1999 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8#ifndef __ASM_PROCESSOR_H
9#define __ASM_PROCESSOR_H
10
11/*
12 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
13 * no point in shifting all network buffers by 2 bytes just to make some IP
14 * header fields appear aligned in memory, potentially sacrificing some DMA
15 * performance on some platforms.
16 */
17#define NET_IP_ALIGN 0
18
19#define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
20#define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
21
22#define MTE_CTRL_TCF_SYNC (1UL << 16)
23#define MTE_CTRL_TCF_ASYNC (1UL << 17)
24#define MTE_CTRL_TCF_ASYMM (1UL << 18)
25
26#define MTE_CTRL_STORE_ONLY (1UL << 19)
27
28#ifndef __ASSEMBLER__
29
30#include <linux/build_bug.h>
31#include <linux/cache.h>
32#include <linux/init.h>
33#include <linux/stddef.h>
34#include <linux/string.h>
35#include <linux/thread_info.h>
36
37#include <vdso/processor.h>
38
39#include <asm/alternative.h>
40#include <asm/cpufeature.h>
41#include <asm/hw_breakpoint.h>
42#include <asm/kasan.h>
43#include <asm/lse.h>
44#include <asm/pgtable-hwdef.h>
45#include <asm/pointer_auth.h>
46#include <asm/ptrace.h>
47#include <asm/spectre.h>
48#include <asm/types.h>
49
50/*
51 * TASK_SIZE - the maximum size of a user space task.
52 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
53 */
54
55#define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
56#define TASK_SIZE_64 (UL(1) << vabits_actual)
57#define TASK_SIZE_MAX (UL(1) << VA_BITS)
58
59#ifdef CONFIG_COMPAT
60#if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
61/*
62 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
63 * by the compat vectors page.
64 */
65#define TASK_SIZE_32 UL(0x100000000)
66#else
67#define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
68#endif /* CONFIG_ARM64_64K_PAGES */
69#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
70 TASK_SIZE_32 : TASK_SIZE_64)
71#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
72 TASK_SIZE_32 : TASK_SIZE_64)
73#define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
74 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
75#else
76#define TASK_SIZE TASK_SIZE_64
77#define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
78#endif /* CONFIG_COMPAT */
79
80#ifdef CONFIG_ARM64_FORCE_52BIT
81#define STACK_TOP_MAX TASK_SIZE_64
82#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
83#else
84#define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
85#define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
86#endif /* CONFIG_ARM64_FORCE_52BIT */
87
88#ifdef CONFIG_COMPAT
89#define AARCH32_VECTORS_BASE 0xffff0000
90#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
91 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
92#else
93#define STACK_TOP STACK_TOP_MAX
94#endif /* CONFIG_COMPAT */
95
96#ifndef CONFIG_ARM64_FORCE_52BIT
97#define arch_get_mmap_end(addr, len, flags) \
98 (((addr) > DEFAULT_MAP_WINDOW) ? TASK_SIZE : DEFAULT_MAP_WINDOW)
99
100#define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
101 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
102 base)
103#endif /* CONFIG_ARM64_FORCE_52BIT */
104
105extern phys_addr_t arm64_dma_phys_limit;
106#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
107
108struct debug_info {
109#ifdef CONFIG_HAVE_HW_BREAKPOINT
110 /* Have we suspended stepping by a debugger? */
111 int suspended_step;
112 /* Allow breakpoints and watchpoints to be disabled for this thread. */
113 int bps_disabled;
114 int wps_disabled;
115 /* Hardware breakpoints pinned to this task. */
116 struct perf_event *hbp_break[ARM_MAX_BRP];
117 struct perf_event *hbp_watch[ARM_MAX_WRP];
118#endif
119};
120
121enum vec_type {
122 ARM64_VEC_SVE = 0,
123 ARM64_VEC_SME,
124 ARM64_VEC_MAX,
125};
126
127enum fp_type {
128 FP_STATE_CURRENT, /* Save based on current task state. */
129 FP_STATE_FPSIMD,
130 FP_STATE_SVE,
131};
132
133struct arm64_sve_state; /* Opaque type */
134struct arm64_sme_state; /* Opaque type */
135
136struct cpu_context {
137 unsigned long x19;
138 unsigned long x20;
139 unsigned long x21;
140 unsigned long x22;
141 unsigned long x23;
142 unsigned long x24;
143 unsigned long x25;
144 unsigned long x26;
145 unsigned long x27;
146 unsigned long x28;
147 unsigned long fp;
148 unsigned long sp;
149 unsigned long pc;
150};
151
152struct thread_struct {
153 struct cpu_context cpu_context; /* cpu context */
154
155 /*
156 * Whitelisted fields for hardened usercopy:
157 * Maintainers must ensure manually that this contains no
158 * implicit padding.
159 */
160 struct {
161 unsigned long tp_value; /* TLS register */
162 unsigned long tp2_value;
163 u64 fpmr;
164 unsigned long pad;
165 struct user_fpsimd_state fpsimd_state;
166 } uw;
167
168 enum fp_type fp_type; /* registers FPSIMD or SVE? */
169 unsigned int fpsimd_cpu;
170 struct arm64_sve_state *sve_state; /* SVE registers, if any */
171 struct arm64_sme_state *sme_state; /* ZA and ZT state, if any */
172 unsigned int vl[ARM64_VEC_MAX]; /* vector length */
173 unsigned int vl_onexec[ARM64_VEC_MAX]; /* vl after next exec */
174 unsigned long fault_address; /* fault info */
175 unsigned long fault_code; /* ESR_EL1 value */
176 struct debug_info debug; /* debugging */
177
178 /*
179 * Set [cleared] by kernel_neon_begin() [kernel_neon_end()] to the
180 * address of a caller provided buffer that will be used to preserve a
181 * task's kernel mode FPSIMD state while it is scheduled out.
182 */
183 struct user_fpsimd_state *kernel_fpsimd_state;
184 unsigned int kernel_fpsimd_cpu;
185#ifdef CONFIG_ARM64_PTR_AUTH
186 struct ptrauth_keys_user keys_user;
187#ifdef CONFIG_ARM64_PTR_AUTH_KERNEL
188 struct ptrauth_keys_kernel keys_kernel;
189#endif
190#endif
191#ifdef CONFIG_ARM64_MTE
192 u64 mte_ctrl;
193#endif
194 u64 sctlr_user;
195 u64 svcr;
196 u64 tpidr2_el0;
197 u64 por_el0;
198#ifdef CONFIG_ARM64_GCS
199 unsigned int gcs_el0_mode;
200 unsigned int gcs_el0_locked;
201 u64 gcspr_el0;
202 u64 gcs_base;
203 u64 gcs_size;
204#endif
205};
206
207static inline unsigned int thread_get_vl(struct thread_struct *thread,
208 enum vec_type type)
209{
210 return thread->vl[type];
211}
212
213static inline unsigned int thread_get_sve_vl(struct thread_struct *thread)
214{
215 return thread_get_vl(thread, ARM64_VEC_SVE);
216}
217
218static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
219{
220 return thread_get_vl(thread, ARM64_VEC_SME);
221}
222
223static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
224{
225 if (system_supports_sme() && (thread->svcr & SVCR_SM_MASK))
226 return thread_get_sme_vl(thread);
227 else
228 return thread_get_sve_vl(thread);
229}
230
231unsigned int task_get_vl(const struct task_struct *task, enum vec_type type);
232void task_set_vl(struct task_struct *task, enum vec_type type,
233 unsigned long vl);
234void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
235 unsigned long vl);
236unsigned int task_get_vl_onexec(const struct task_struct *task,
237 enum vec_type type);
238
239static inline unsigned int task_get_sve_vl(const struct task_struct *task)
240{
241 return task_get_vl(task, ARM64_VEC_SVE);
242}
243
244static inline unsigned int task_get_sme_vl(const struct task_struct *task)
245{
246 return task_get_vl(task, ARM64_VEC_SME);
247}
248
249static inline void task_set_sve_vl(struct task_struct *task, unsigned long vl)
250{
251 task_set_vl(task, ARM64_VEC_SVE, vl);
252}
253
254static inline unsigned int task_get_sve_vl_onexec(const struct task_struct *task)
255{
256 return task_get_vl_onexec(task, ARM64_VEC_SVE);
257}
258
259static inline void task_set_sve_vl_onexec(struct task_struct *task,
260 unsigned long vl)
261{
262 task_set_vl_onexec(task, ARM64_VEC_SVE, vl);
263}
264
265#define SCTLR_USER_MASK \
266 (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \
267 SCTLR_EL1_TCF0_MASK | SCTLR_EL1_TCSO0_MASK)
268
269static inline void arch_thread_struct_whitelist(unsigned long *offset,
270 unsigned long *size)
271{
272 /* Verify that there is no padding among the whitelisted fields: */
273 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
274 sizeof_field(struct thread_struct, uw.tp_value) +
275 sizeof_field(struct thread_struct, uw.tp2_value) +
276 sizeof_field(struct thread_struct, uw.fpmr) +
277 sizeof_field(struct thread_struct, uw.pad) +
278 sizeof_field(struct thread_struct, uw.fpsimd_state));
279
280 *offset = offsetof(struct thread_struct, uw);
281 *size = sizeof_field(struct thread_struct, uw);
282}
283
284#ifdef CONFIG_COMPAT
285#define task_user_tls(t) \
286({ \
287 unsigned long *__tls; \
288 if (is_compat_thread(task_thread_info(t))) \
289 __tls = &(t)->thread.uw.tp2_value; \
290 else \
291 __tls = &(t)->thread.uw.tp_value; \
292 __tls; \
293 })
294#else
295#define task_user_tls(t) (&(t)->thread.uw.tp_value)
296#endif
297
298/* Sync TPIDR_EL0 back to thread_struct for current */
299void tls_preserve_current_state(void);
300
301#define INIT_THREAD { \
302 .fpsimd_cpu = NR_CPUS, \
303}
304
305static inline void start_thread_common(struct pt_regs *regs, unsigned long pc,
306 unsigned long pstate)
307{
308 /*
309 * Ensure all GPRs are zeroed, and initialize PC + PSTATE.
310 * The SP (or compat SP) will be initialized later.
311 */
312 regs->user_regs = (struct user_pt_regs) {
313 .pc = pc,
314 .pstate = pstate,
315 };
316
317 /*
318 * To allow the syscalls:sys_exit_execve tracepoint we need to preserve
319 * syscallno, but do not need orig_x0 or the original GPRs.
320 */
321 regs->orig_x0 = 0;
322
323 /*
324 * An exec from a kernel thread won't have an existing PMR value.
325 */
326 if (system_uses_irq_prio_masking())
327 regs->pmr = GIC_PRIO_IRQON;
328
329 /*
330 * The pt_regs::stackframe field must remain valid throughout this
331 * function as a stacktrace can be taken at any time. Any user or
332 * kernel task should have a valid final frame.
333 */
334 WARN_ON_ONCE(regs->stackframe.record.fp != 0);
335 WARN_ON_ONCE(regs->stackframe.record.lr != 0);
336 WARN_ON_ONCE(regs->stackframe.type != FRAME_META_TYPE_FINAL);
337}
338
339static inline void start_thread(struct pt_regs *regs, unsigned long pc,
340 unsigned long sp)
341{
342 start_thread_common(regs, pc, PSR_MODE_EL0t);
343 spectre_v4_enable_task_mitigation(current);
344 regs->sp = sp;
345}
346
347#ifdef CONFIG_COMPAT
348static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
349 unsigned long sp)
350{
351 unsigned long pstate = PSR_AA32_MODE_USR;
352 if (pc & 1)
353 pstate |= PSR_AA32_T_BIT;
354
355 start_thread_common(regs, pc, pstate);
356 spectre_v4_enable_task_mitigation(current);
357 regs->compat_sp = sp;
358}
359#endif
360
361static __always_inline bool is_ttbr0_addr(unsigned long addr)
362{
363 /* entry assembly clears tags for TTBR0 addrs */
364 return addr < TASK_SIZE;
365}
366
367static __always_inline bool is_ttbr1_addr(unsigned long addr)
368{
369 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
370 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
371}
372
373/* Forward declaration, a strange C thing */
374struct task_struct;
375
376unsigned long __get_wchan(struct task_struct *p);
377
378void update_sctlr_el1(u64 sctlr);
379
380/* Thread switching */
381extern struct task_struct *cpu_switch_to(struct task_struct *prev,
382 struct task_struct *next);
383
384#define task_pt_regs(p) \
385 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
386
387#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
388#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
389
390/*
391 * Prefetching support
392 */
393#define ARCH_HAS_PREFETCH
394static inline void prefetch(const void *ptr)
395{
396 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
397}
398
399#define ARCH_HAS_PREFETCHW
400static inline void prefetchw(const void *ptr)
401{
402 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
403}
404
405extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
406extern void __init minsigstksz_setup(void);
407
408/*
409 * Not at the top of the file due to a direct #include cycle between
410 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
411 * ensures that contents of processor.h are visible to fpsimd.h even if
412 * processor.h is included first.
413 *
414 * These prctl helpers are the only things in this file that require
415 * fpsimd.h. The core code expects them to be in this header.
416 */
417#include <asm/fpsimd.h>
418
419/* Userspace interface for PR_S[MV]E_{SET,GET}_VL prctl()s: */
420#define SVE_SET_VL(arg) sve_set_current_vl(arg)
421#define SVE_GET_VL() sve_get_current_vl()
422#define SME_SET_VL(arg) sme_set_current_vl(arg)
423#define SME_GET_VL() sme_get_current_vl()
424
425/* PR_PAC_RESET_KEYS prctl */
426#define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg)
427
428/* PR_PAC_{SET,GET}_ENABLED_KEYS prctl */
429#define PAC_SET_ENABLED_KEYS(tsk, keys, enabled) \
430 ptrauth_set_enabled_keys(tsk, keys, enabled)
431#define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk)
432
433#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
434/* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
435long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg);
436long get_tagged_addr_ctrl(struct task_struct *task);
437#define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg)
438#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current)
439#endif
440
441int get_tsc_mode(unsigned long adr);
442int set_tsc_mode(unsigned int val);
443#define GET_TSC_CTL(adr) get_tsc_mode((adr))
444#define SET_TSC_CTL(val) set_tsc_mode((val))
445
446#endif /* __ASSEMBLER__ */
447#endif /* __ASM_PROCESSOR_H */