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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Macros for accessing system registers with older binutils.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 * Author: Catalin Marinas <[email protected]>
7 */
8
9#ifndef __ASM_SYSREG_H
10#define __ASM_SYSREG_H
11
12#include <linux/bits.h>
13#include <linux/stringify.h>
14#include <linux/kasan-tags.h>
15#include <linux/kconfig.h>
16
17#include <asm/gpr-num.h>
18
19/*
20 * ARMv8 ARM reserves the following encoding for system registers:
21 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
22 * C5.2, version:ARM DDI 0487A.f)
23 * [20-19] : Op0
24 * [18-16] : Op1
25 * [15-12] : CRn
26 * [11-8] : CRm
27 * [7-5] : Op2
28 */
29#define Op0_shift 19
30#define Op0_mask 0x3
31#define Op1_shift 16
32#define Op1_mask 0x7
33#define CRn_shift 12
34#define CRn_mask 0xf
35#define CRm_shift 8
36#define CRm_mask 0xf
37#define Op2_shift 5
38#define Op2_mask 0x7
39
40#define sys_reg(op0, op1, crn, crm, op2) \
41 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
42 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
43 ((op2) << Op2_shift))
44
45#define sys_insn sys_reg
46
47#define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
48#define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
49#define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
50#define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
51#define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
52
53#ifndef CONFIG_BROKEN_GAS_INST
54
55#ifdef __ASSEMBLER__
56// The space separator is omitted so that __emit_inst(x) can be parsed as
57// either an assembler directive or an assembler macro argument.
58#define __emit_inst(x) .inst(x)
59#else
60#define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
61#endif
62
63#else /* CONFIG_BROKEN_GAS_INST */
64
65#ifdef __ASSEMBLER__
66#define __emit_inst(x) .long (x)
67#else /* __ASSEMBLER__ */
68#define __emit_inst(x) ".long " __stringify(x) "\n\t"
69#endif /* __ASSEMBLER__ */
70
71#endif /* CONFIG_BROKEN_GAS_INST */
72
73/*
74 * Instructions for modifying PSTATE fields.
75 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
76 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
77 * for accessing PSTATE fields have the following encoding:
78 * Op0 = 0, CRn = 4
79 * Op1, Op2 encodes the PSTATE field modified and defines the constraints.
80 * CRm = Imm4 for the instruction.
81 * Rt = 0x1f
82 */
83#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift)
84#define PSTATE_Imm_shift CRm_shift
85#define ENCODE_PSTATE(x, r) (0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
86#define SET_PSTATE(x, r) __emit_inst(ENCODE_PSTATE(x, r))
87
88#define PSTATE_PAN pstate_field(0, 4)
89#define PSTATE_UAO pstate_field(0, 3)
90#define PSTATE_SSBS pstate_field(3, 1)
91#define PSTATE_DIT pstate_field(3, 2)
92#define PSTATE_TCO pstate_field(3, 4)
93
94#define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN)
95#define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO)
96#define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS)
97#define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT)
98#define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO)
99
100#define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x))
101#define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x))
102#define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x))
103#define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x))
104
105/* Register-based PAN access, for save/restore purposes */
106#define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
107
108#define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \
109 __emit_inst(0xd5000000 | \
110 sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \
111 ((Rt) & 0x1f))
112
113#define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31)
114#define GSB_SYS_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31)
115#define GSB_ACK_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31)
116
117/* Data cache zero operations */
118#define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
119#define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
120#define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
121#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
122#define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
123#define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
124#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
125#define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
126#define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
127
128#define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
129#define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
130#define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
131
132#define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
133#define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
134#define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
135
136#define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
137#define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
138#define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
139
140#define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
141
142#define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
143#define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
144#define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
145
146#define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
147#define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
148#define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
149
150#define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
151#define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
152#define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
153
154#define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
155#define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
156#define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
157
158#define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1)
159#define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5)
160
161/*
162 * Automatically generated definitions for system registers, the
163 * manual encodings below are in the process of being converted to
164 * come from here. The header relies on the definition of sys_reg()
165 * earlier in this file.
166 */
167#include <asm/sysreg-defs.h>
168
169/*
170 * System registers, organised loosely by encoding but grouped together
171 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
172 */
173#define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
174#define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
175#define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
176
177#define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
178#define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
179#define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
180#define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
181#define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
182
183#define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
184#define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
185#define OSLSR_EL1_OSLM_NI 0
186#define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
187#define OSLSR_EL1_OSLK BIT(1)
188
189#define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
190#define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
191#define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
192#define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
193#define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
194#define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
195#define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
196#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
197#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
198#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
199
200#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
201#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
202#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
203
204#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
205#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
206#define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
207#define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
208#define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
209#define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
210#define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
211#define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
212#define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
213#define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
214#define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
215#define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
216#define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
217#define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
218#define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
219#define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
220#define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
221#define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
222#define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
223#define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
224#define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
225#define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
226#define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
227#define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
228#define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
229#define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
230#define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
231#define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
232#define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
233#define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
234#define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
235#define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
236#define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
237#define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
238#define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
239#define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
240#define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
241#define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
242#define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
243#define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
244#define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
245#define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
246#define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
247#define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
248#define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
249#define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
250#define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
251#define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
252#define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
253#define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
254#define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
255#define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
256#define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
257#define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
258#define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
259#define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
260#define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
261#define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
262#define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
263#define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
264
265/* ETM */
266#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
267
268#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
269#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
270#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
271
272#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
273#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
274#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
275
276#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
277#define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
278#define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
279#define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
280
281#define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
282#define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
283#define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
284#define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
285
286#define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
287#define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
288
289#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
290#define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
291
292#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
293
294#define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
295#define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
296#define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
297
298#define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
299#define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
300#define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
301#define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
302#define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
303#define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
304#define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
305#define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
306#define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
307#define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
308#define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
309#define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
310#define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
311#define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
312#define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
313
314#define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
315
316#define SYS_PAR_EL1_F BIT(0)
317/* When PAR_EL1.F == 1 */
318#define SYS_PAR_EL1_FST GENMASK(6, 1)
319#define SYS_PAR_EL1_PTW BIT(8)
320#define SYS_PAR_EL1_S BIT(9)
321#define SYS_PAR_EL1_AssuredOnly BIT(12)
322#define SYS_PAR_EL1_TopLevel BIT(13)
323#define SYS_PAR_EL1_Overlay BIT(14)
324#define SYS_PAR_EL1_DirtyBit BIT(15)
325#define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48)
326#define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
327#define SYS_PAR_EL1_RES1 BIT(11)
328/* When PAR_EL1.F == 0 */
329#define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
330#define SYS_PAR_EL1_NS BIT(9)
331#define SYS_PAR_EL1_F0_IMPDEF BIT(10)
332#define SYS_PAR_EL1_NSE BIT(11)
333#define SYS_PAR_EL1_PA GENMASK_ULL(51, 12)
334#define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56)
335#define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52))
336
337/* Buffer error reporting */
338#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT
339#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK
340
341#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT
342#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK
343
344#define PMBSR_EL1_BUF_BSC_FULL 0x1UL
345
346/*** End of Statistical Profiling Extension ***/
347
348#define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
349#define TRBSR_EL1_BSC_SHIFT 0
350
351#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
352#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
353
354#define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
355
356#define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
357#define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
358
359#define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
360#define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
361
362#define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
363#define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
364#define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
365#define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
366#define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
367#define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
368#define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
369#define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
370#define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
371#define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
372#define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
373#define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
374#define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
375#define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
376#define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
377#define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
378#define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
379#define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
380#define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
381#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
382#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
383#define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
384#define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
385#define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
386#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
387#define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
388#define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
389
390#define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
391
392#define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
393
394#define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
395
396#define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
397#define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
398
399#define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
400#define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
401#define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
402#define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
403#define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
404#define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
405#define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
406#define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
407#define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
408#define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
409#define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
410#define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
411
412#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
413#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
414#define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
415
416#define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
417
418/* Definitions for system register interface to AMU for ARMv8.4 onwards */
419#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
420#define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
421#define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
422#define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2)
423#define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
424#define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
425#define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
426#define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
427#define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
428
429/*
430 * Group 0 of activity monitors (architected):
431 * op0 op1 CRn CRm op2
432 * Counter: 11 011 1101 010:n<3> n<2:0>
433 * Type: 11 011 1101 011:n<3> n<2:0>
434 * n: 0-15
435 *
436 * Group 1 of activity monitors (auxiliary):
437 * op0 op1 CRn CRm op2
438 * Counter: 11 011 1101 110:n<3> n<2:0>
439 * Type: 11 011 1101 111:n<3> n<2:0>
440 * n: 0-15
441 */
442
443#define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
444#define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
445#define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
446#define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
447
448/* AMU v1: Fixed (architecturally defined) activity monitors */
449#define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
450#define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
451#define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2)
452#define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
453
454#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
455
456#define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
457#define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2)
458#define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
459#define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
460
461#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
462#define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
463#define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
464
465#define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0)
466#define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
467#define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
468
469#define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
470#define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
471#define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0)
472#define SYS_AARCH32_CNTVCT sys_reg(0, 1, 0, 14, 0)
473#define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
474#define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
475#define SYS_AARCH32_CNTVCTSS sys_reg(0, 9, 0, 14, 0)
476
477#define __PMEV_op2(n) ((n) & 0x7)
478#define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
479#define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))
480#define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
481#define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
482#define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
483
484#define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
485
486#define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1))
487
488#define __SPMEV_op2(n) ((n) & 0x7)
489#define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1))
490#define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))
491#define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))
492#define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))
493#define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))
494
495#define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
496#define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
497
498#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
499#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
500#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
501#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
502#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
503#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
504#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
505
506#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
507#define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
508#define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
509#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
510
511#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
512#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
513#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
514#define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
515#define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
516#define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
517#define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
518#define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
519#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
520#define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
521#define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
522#define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
523#define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
524#define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
525#define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
526
527#define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
528#define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
529
530#define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
531#define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
532
533#define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
534#define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
535#define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
536#define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
537#define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
538#define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
539#define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
540#define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
541#define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
542
543#define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
544#define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
545#define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
546#define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
547#define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
548
549#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
550#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
551#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
552#define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
553
554#define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
555#define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
556#define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
557#define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
558#define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
559#define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
560#define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
561#define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
562#define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
563
564#define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
565#define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
566#define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
567#define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
568#define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
569#define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
570#define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
571#define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
572#define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
573
574#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
575#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
576#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
577
578#define __AMEV_op2(m) (m & 0x7)
579#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
580#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
581#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m)
582#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
583#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m)
584
585#define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
586#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
587#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
588#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
589#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
590#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
591#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
592#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
593
594/* VHE encodings for architectural EL0/1 system registers */
595#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
596#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
597#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
598#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
599#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
600#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
601#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
602#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
603#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
604#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
605#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
606#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
607#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
608#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
609#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
610#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
611#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
612#define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
613#define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
614#define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
615#define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
616
617#define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
618
619/* AT instructions */
620#define AT_Op0 1
621#define AT_CRn 7
622
623#define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
624#define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
625#define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
626#define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
627#define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
628#define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
629#define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
630#define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
631#define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
632#define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
633#define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
634#define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
635#define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
636#define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
637
638/* TLBI instructions */
639#define TLBI_Op0 1
640
641#define TLBI_Op1_EL1 0 /* Accessible from EL1 or higher */
642#define TLBI_Op1_EL2 4 /* Accessible from EL2 or higher */
643
644#define TLBI_CRn_XS 8 /* Extra Slow (the common one) */
645#define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/
646
647#define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
648#define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
649#define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
650#define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
651#define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
652#define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
653#define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
654#define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
655
656#define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
657#define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
658#define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
659#define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
660#define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
661#define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
662#define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
663#define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
664#define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
665#define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
666#define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
667#define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
668#define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
669#define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
670#define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
671#define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
672#define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
673#define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
674#define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
675#define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
676#define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
677#define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
678#define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
679#define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
680#define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
681#define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
682#define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
683#define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
684#define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
685#define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
686#define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
687#define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
688#define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
689#define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
690#define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
691#define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
692#define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
693#define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
694#define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
695#define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
696#define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
697#define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
698#define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
699#define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
700#define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
701#define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
702#define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
703#define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
704#define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
705#define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
706#define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
707#define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
708#define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
709#define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
710#define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
711#define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
712#define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
713#define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
714#define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
715#define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
716#define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
717#define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
718#define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
719#define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
720#define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
721#define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
722#define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
723#define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
724#define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
725#define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
726#define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
727#define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
728#define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
729#define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
730#define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
731#define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
732#define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
733#define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
734#define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
735#define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
736#define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
737#define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
738#define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
739#define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
740#define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
741#define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
742#define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
743#define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
744#define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
745#define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
746#define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
747#define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
748#define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
749#define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
750#define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
751#define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
752#define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
753#define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
754#define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
755#define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
756#define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
757#define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
758#define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
759#define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
760#define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
761#define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
762#define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
763#define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
764#define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
765#define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
766#define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
767#define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
768#define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
769#define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
770#define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
771#define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
772#define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
773#define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
774#define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
775#define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
776#define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
777#define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
778#define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
779#define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
780#define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
781#define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
782
783/* Misc instructions */
784#define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
785#define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
786#define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
787#define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
788
789#define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
790#define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
791#define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
792#define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
793#define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
794#define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
795
796/*
797 * BRBE Instructions
798 */
799#define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f))
800#define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f))
801
802/* Common SCTLR_ELx flags. */
803#define SCTLR_ELx_ENTP2 (BIT(60))
804#define SCTLR_ELx_DSSBS (BIT(44))
805#define SCTLR_ELx_ATA (BIT(43))
806
807#define SCTLR_ELx_EE_SHIFT 25
808#define SCTLR_ELx_ENIA_SHIFT 31
809
810#define SCTLR_ELx_ITFSB (BIT(37))
811#define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
812#define SCTLR_ELx_ENIB (BIT(30))
813#define SCTLR_ELx_LSMAOE (BIT(29))
814#define SCTLR_ELx_nTLSMD (BIT(28))
815#define SCTLR_ELx_ENDA (BIT(27))
816#define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT))
817#define SCTLR_ELx_EIS (BIT(22))
818#define SCTLR_ELx_IESB (BIT(21))
819#define SCTLR_ELx_TSCXT (BIT(20))
820#define SCTLR_ELx_WXN (BIT(19))
821#define SCTLR_ELx_ENDB (BIT(13))
822#define SCTLR_ELx_I (BIT(12))
823#define SCTLR_ELx_EOS (BIT(11))
824#define SCTLR_ELx_SA (BIT(3))
825#define SCTLR_ELx_C (BIT(2))
826#define SCTLR_ELx_A (BIT(1))
827#define SCTLR_ELx_M (BIT(0))
828
829#define INIT_SCTLR_EL2_MMU_ON \
830 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \
831 SCTLR_ELx_IESB | SCTLR_ELx_WXN | SCTLR_ELx_ITFSB | \
832 SCTLR_ELx_EIS | SCTLR_ELx_EOS | SCTLR_EL2_RES1)
833
834#define INIT_SCTLR_EL2_MMU_OFF (SCTLR_EL2_RES1)
835
836/* SCTLR_EL1 specific flags. */
837#define INIT_SCTLR_EL1_MMU_OFF \
838 (SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \
839 SCTLR_EL1_TSCXT | SCTLR_EL1_EOS)
840
841#define INIT_SCTLR_EL1_MMU_ON \
842 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \
843 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \
844 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \
845 SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
846 SCTLR_EL1_UCI | SCTLR_EL1_EPAN | SCTLR_EL1_LSMAOE | \
847 SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | \
848 SCTLR_EL1_EOS)
849
850/* MAIR_ELx memory attributes (used by Linux) */
851#define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
852#define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
853#define MAIR_ATTR_NORMAL_NC UL(0x44)
854#define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
855#define MAIR_ATTR_NORMAL UL(0xff)
856#define MAIR_ATTR_MASK UL(0xff)
857
858/* Position the attr at the correct index */
859#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
860
861/* id_aa64mmfr0 */
862#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
863#define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT
864#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
865#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
866#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
867#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
868#define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT
869#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
870
871#define ARM64_MIN_PARANGE_BITS 32
872
873#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0
874#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1
875#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2
876#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3
877#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
878
879#ifdef CONFIG_ARM64_PA_BITS_52
880#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52
881#else
882#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
883#endif
884
885#if defined(CONFIG_ARM64_4K_PAGES)
886#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
887#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT
888#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
889#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
890#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
891#elif defined(CONFIG_ARM64_16K_PAGES)
892#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT
893#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT
894#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
895#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
896#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
897#elif defined(CONFIG_ARM64_64K_PAGES)
898#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT
899#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
900#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
901#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
902#endif
903
904#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
905#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
906
907#define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */
908#define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */
909
910#define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
911#define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
912
913/* GCR_EL1 Definitions */
914#define SYS_GCR_EL1_RRND (BIT(16))
915#define SYS_GCR_EL1_EXCL_MASK 0xffffUL
916
917#ifdef CONFIG_KASAN_HW_TAGS
918/*
919 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
920 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
921 */
922#define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf)
923#define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf)
924#define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
925#define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
926#else
927#define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK
928#endif
929
930#define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
931
932/* RGSR_EL1 Definitions */
933#define SYS_RGSR_EL1_TAG_MASK 0xfUL
934#define SYS_RGSR_EL1_SEED_SHIFT 8
935#define SYS_RGSR_EL1_SEED_MASK 0xffffUL
936
937/* TFSR{,E0}_EL1 bit definitions */
938#define SYS_TFSR_EL1_TF0_SHIFT 0
939#define SYS_TFSR_EL1_TF1_SHIFT 1
940#define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
941#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
942
943/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
944#define SYS_MPIDR_SAFE_VAL (BIT(31))
945
946/* GIC Hypervisor interface registers */
947/* ICH_LR*_EL2 bit definitions */
948#define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
949
950#define ICH_LR_EOI (1ULL << 41)
951#define ICH_LR_GROUP (1ULL << 60)
952#define ICH_LR_HW (1ULL << 61)
953#define ICH_LR_STATE (3ULL << 62)
954#define ICH_LR_PENDING_BIT (1ULL << 62)
955#define ICH_LR_ACTIVE_BIT (1ULL << 63)
956#define ICH_LR_PHYS_ID_SHIFT 32
957#define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
958#define ICH_LR_PRIORITY_SHIFT 48
959#define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
960
961/*
962 * Permission Indirection Extension (PIE) permission encodings.
963 * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
964 */
965#define PIE_NONE_O UL(0x0)
966#define PIE_R_O UL(0x1)
967#define PIE_X_O UL(0x2)
968#define PIE_RX_O UL(0x3)
969#define PIE_RW_O UL(0x5)
970#define PIE_RWnX_O UL(0x6)
971#define PIE_RWX_O UL(0x7)
972#define PIE_R UL(0x8)
973#define PIE_GCS UL(0x9)
974#define PIE_RX UL(0xa)
975#define PIE_RW UL(0xc)
976#define PIE_RWX UL(0xe)
977#define PIE_MASK UL(0xf)
978
979#define PIRx_ELx_BITS_PER_IDX 4
980#define PIRx_ELx_PERM_SHIFT(idx) ((idx) * PIRx_ELx_BITS_PER_IDX)
981#define PIRx_ELx_PERM_PREP(idx, perm) (((perm) & PIE_MASK) << PIRx_ELx_PERM_SHIFT(idx))
982
983/*
984 * Permission Overlay Extension (POE) permission encodings.
985 */
986#define POE_NONE UL(0x0)
987#define POE_R UL(0x1)
988#define POE_X UL(0x2)
989#define POE_RX UL(0x3)
990#define POE_W UL(0x4)
991#define POE_RW UL(0x5)
992#define POE_WX UL(0x6)
993#define POE_RWX UL(0x7)
994#define POE_MASK UL(0xf)
995
996#define POR_ELx_BITS_PER_IDX 4
997#define POR_ELx_PERM_SHIFT(idx) ((idx) * POR_ELx_BITS_PER_IDX)
998#define POR_ELx_PERM_GET(idx, reg) (((reg) >> POR_ELx_PERM_SHIFT(idx)) & POE_MASK)
999#define POR_ELx_PERM_PREP(idx, perm) (((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx))
1000
1001/*
1002 * Definitions for Guarded Control Stack
1003 */
1004
1005#define GCS_CAP_ADDR_MASK GENMASK(63, 12)
1006#define GCS_CAP_ADDR_SHIFT 12
1007#define GCS_CAP_ADDR_WIDTH 52
1008#define GCS_CAP_ADDR(x) FIELD_GET(GCS_CAP_ADDR_MASK, x)
1009
1010#define GCS_CAP_TOKEN_MASK GENMASK(11, 0)
1011#define GCS_CAP_TOKEN_SHIFT 0
1012#define GCS_CAP_TOKEN_WIDTH 12
1013#define GCS_CAP_TOKEN(x) FIELD_GET(GCS_CAP_TOKEN_MASK, x)
1014
1015#define GCS_CAP_VALID_TOKEN 0x1
1016#define GCS_CAP_IN_PROGRESS_TOKEN 0x5
1017
1018#define GCS_CAP(x) ((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \
1019 GCS_CAP_VALID_TOKEN)
1020/*
1021 * Definitions for GICv5 instructions
1022 */
1023#define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3)
1024#define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0)
1025#define GICV5_OP_GIC_CDDIS sys_insn(1, 0, 12, 1, 0)
1026#define GICV5_OP_GIC_CDHM sys_insn(1, 0, 12, 2, 1)
1027#define GICV5_OP_GIC_CDEN sys_insn(1, 0, 12, 1, 1)
1028#define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7)
1029#define GICV5_OP_GIC_CDPEND sys_insn(1, 0, 12, 1, 4)
1030#define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2)
1031#define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5)
1032#define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0)
1033#define GICV5_OP_GICR_CDNMIA sys_insn(1, 0, 12, 3, 1)
1034
1035/* Definitions for GIC CDAFF */
1036#define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32)
1037#define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29)
1038#define GICV5_GIC_CDAFF_IRM_MASK BIT_ULL(28)
1039#define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0)
1040
1041/* Definitions for GIC CDDI */
1042#define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29)
1043#define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0)
1044
1045/* Definitions for GIC CDDIS */
1046#define GICV5_GIC_CDDIS_TYPE_MASK GENMASK_ULL(31, 29)
1047#define GICV5_GIC_CDDIS_TYPE(r) FIELD_GET(GICV5_GIC_CDDIS_TYPE_MASK, r)
1048#define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0)
1049#define GICV5_GIC_CDDIS_ID(r) FIELD_GET(GICV5_GIC_CDDIS_ID_MASK, r)
1050
1051/* Definitions for GIC CDEN */
1052#define GICV5_GIC_CDEN_TYPE_MASK GENMASK_ULL(31, 29)
1053#define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0)
1054
1055/* Definitions for GIC CDHM */
1056#define GICV5_GIC_CDHM_HM_MASK BIT_ULL(32)
1057#define GICV5_GIC_CDHM_TYPE_MASK GENMASK_ULL(31, 29)
1058#define GICV5_GIC_CDHM_ID_MASK GENMASK_ULL(23, 0)
1059
1060/* Definitions for GIC CDPEND */
1061#define GICV5_GIC_CDPEND_PENDING_MASK BIT_ULL(32)
1062#define GICV5_GIC_CDPEND_TYPE_MASK GENMASK_ULL(31, 29)
1063#define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0)
1064
1065/* Definitions for GIC CDPRI */
1066#define GICV5_GIC_CDPRI_PRIORITY_MASK GENMASK_ULL(39, 35)
1067#define GICV5_GIC_CDPRI_TYPE_MASK GENMASK_ULL(31, 29)
1068#define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0)
1069
1070/* Definitions for GIC CDRCFG */
1071#define GICV5_GIC_CDRCFG_TYPE_MASK GENMASK_ULL(31, 29)
1072#define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0)
1073
1074/* Definitions for GICR CDIA */
1075#define GICV5_GIC_CDIA_VALID_MASK BIT_ULL(32)
1076#define GICV5_GICR_CDIA_VALID(r) FIELD_GET(GICV5_GIC_CDIA_VALID_MASK, r)
1077#define GICV5_GIC_CDIA_TYPE_MASK GENMASK_ULL(31, 29)
1078#define GICV5_GIC_CDIA_ID_MASK GENMASK_ULL(23, 0)
1079
1080/* Definitions for GICR CDNMIA */
1081#define GICV5_GICR_CDNMIA_VALID_MASK BIT_ULL(32)
1082#define GICV5_GICR_CDNMIA_VALID(r) FIELD_GET(GICV5_GICR_CDNMIA_VALID_MASK, r)
1083#define GICV5_GICR_CDNMIA_TYPE_MASK GENMASK_ULL(31, 29)
1084#define GICV5_GICR_CDNMIA_ID_MASK GENMASK_ULL(23, 0)
1085
1086#define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn)
1087#define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn)
1088
1089#ifdef __ASSEMBLER__
1090
1091 .macro mrs_s, rt, sreg
1092 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
1093 .endm
1094
1095 .macro msr_s, sreg, rt
1096 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
1097 .endm
1098
1099 .macro msr_hcr_el2, reg
1100#if IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23)
1101 dsb nsh
1102#endif
1103 msr hcr_el2, \reg
1104 isb // Required by AMPERE_ERRATUM_AC04_CPU_23
1105 .endm
1106#else
1107
1108#include <linux/bitfield.h>
1109#include <linux/build_bug.h>
1110#include <linux/types.h>
1111#include <asm/alternative.h>
1112
1113#define DEFINE_MRS_S \
1114 __DEFINE_ASM_GPR_NUMS \
1115" .macro mrs_s, rt, sreg\n" \
1116 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \
1117" .endm\n"
1118
1119#define DEFINE_MSR_S \
1120 __DEFINE_ASM_GPR_NUMS \
1121" .macro msr_s, sreg, rt\n" \
1122 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \
1123" .endm\n"
1124
1125#define UNDEFINE_MRS_S \
1126" .purgem mrs_s\n"
1127
1128#define UNDEFINE_MSR_S \
1129" .purgem msr_s\n"
1130
1131#define __mrs_s(v, r) \
1132 DEFINE_MRS_S \
1133" mrs_s " v ", " __stringify(r) "\n" \
1134 UNDEFINE_MRS_S
1135
1136#define __msr_s(r, v) \
1137 DEFINE_MSR_S \
1138" msr_s " __stringify(r) ", " v "\n" \
1139 UNDEFINE_MSR_S
1140
1141/*
1142 * Unlike read_cpuid, calls to read_sysreg are never expected to be
1143 * optimized away or replaced with synthetic values.
1144 */
1145#define read_sysreg(r) ({ \
1146 u64 __val; \
1147 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
1148 __val; \
1149})
1150
1151/*
1152 * The "Z" constraint normally means a zero immediate, but when combined with
1153 * the "%x0" template means XZR.
1154 */
1155#define write_sysreg(v, r) do { \
1156 u64 __val = (u64)(v); \
1157 asm volatile("msr " __stringify(r) ", %x0" \
1158 : : "rZ" (__val)); \
1159} while (0)
1160
1161/*
1162 * For registers without architectural names, or simply unsupported by
1163 * GAS.
1164 *
1165 * __check_r forces warnings to be generated by the compiler when
1166 * evaluating r which wouldn't normally happen due to being passed to
1167 * the assembler via __stringify(r).
1168 */
1169#define read_sysreg_s(r) ({ \
1170 u64 __val; \
1171 u32 __maybe_unused __check_r = (u32)(r); \
1172 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
1173 __val; \
1174})
1175
1176/*
1177 * The "Z" constraint combined with the "%x0" template should be enough
1178 * to force XZR generation if (v) is a constant 0 value but LLVM does not
1179 * yet understand that modifier/constraint combo so a conditional is required
1180 * to nudge the compiler into using XZR as a source for a 0 constant value.
1181 */
1182#define write_sysreg_s(v, r) do { \
1183 u64 __val = (u64)(v); \
1184 u32 __maybe_unused __check_r = (u32)(r); \
1185 if (__builtin_constant_p(__val) && __val == 0) \
1186 asm volatile(__msr_s(r, "xzr")); \
1187 else \
1188 asm volatile(__msr_s(r, "%x0") : : "r" (__val)); \
1189} while (0)
1190
1191/*
1192 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
1193 * set mask are set. Other bits are left as-is.
1194 */
1195#define sysreg_clear_set(sysreg, clear, set) do { \
1196 u64 __scs_val = read_sysreg(sysreg); \
1197 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
1198 if (__scs_new != __scs_val) \
1199 write_sysreg(__scs_new, sysreg); \
1200} while (0)
1201
1202#define sysreg_clear_set_hcr(clear, set) do { \
1203 u64 __scs_val = read_sysreg(hcr_el2); \
1204 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
1205 if (__scs_new != __scs_val) \
1206 write_sysreg_hcr(__scs_new); \
1207} while (0)
1208
1209#define sysreg_clear_set_s(sysreg, clear, set) do { \
1210 u64 __scs_val = read_sysreg_s(sysreg); \
1211 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
1212 if (__scs_new != __scs_val) \
1213 write_sysreg_s(__scs_new, sysreg); \
1214} while (0)
1215
1216#define write_sysreg_hcr(__val) do { \
1217 if (IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) && \
1218 (!system_capabilities_finalized() || \
1219 alternative_has_cap_unlikely(ARM64_WORKAROUND_AMPERE_AC04_CPU_23))) \
1220 asm volatile("dsb nsh; msr hcr_el2, %x0; isb" \
1221 : : "rZ" (__val)); \
1222 else \
1223 asm volatile("msr hcr_el2, %x0" \
1224 : : "rZ" (__val)); \
1225} while (0)
1226
1227#define read_sysreg_par() ({ \
1228 u64 par; \
1229 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
1230 par = read_sysreg(par_el1); \
1231 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
1232 par; \
1233})
1234
1235#define SYS_FIELD_VALUE(reg, field, val) reg##_##field##_##val
1236
1237#define SYS_FIELD_GET(reg, field, val) \
1238 FIELD_GET(reg##_##field##_MASK, val)
1239
1240#define SYS_FIELD_PREP(reg, field, val) \
1241 FIELD_PREP(reg##_##field##_MASK, val)
1242
1243#define SYS_FIELD_PREP_ENUM(reg, field, val) \
1244 FIELD_PREP(reg##_##field##_MASK, \
1245 SYS_FIELD_VALUE(reg, field, val))
1246
1247#endif
1248
1249#endif /* __ASM_SYSREG_H */