| 1 | /* SPDX-License-Identifier: GPL-2.0-only */
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| 2 | /*
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| 3 | * kexec for arm64
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| 4 | *
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| 5 | * Copyright (C) Linaro.
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| 6 | * Copyright (C) Huawei Futurewei Technologies.
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| 7 | * Copyright (C) 2021, Microsoft Corporation.
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| 8 | * Pasha Tatashin <pasha.tatashin@soleen.com>
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| 9 | */
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| 10 |
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| 11 | |
| 12 | |
| 13 |
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| 14 | |
| 15 | |
| 16 | |
| 17 | |
| 18 | |
| 19 |
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| 20 | .macro turn_off_mmu tmp1, tmp2
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| 21 | mov_q \tmp1, INIT_SCTLR_EL1_MMU_OFF
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| 22 | pre_disable_mmu_workaround
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| 23 | msr sctlr_el1, \tmp1
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| 24 | isb
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| 25 | .endm
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| 26 |
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| 27 | .section ".kexec_relocate.text", "ax"
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| 28 | /*
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| 29 | * arm64_relocate_new_kernel - Put a 2nd stage image in place and boot it.
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| 30 | *
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| 31 | * The memory that the old kernel occupies may be overwritten when copying the
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| 32 | * new image to its final location. To assure that the
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| 33 | * arm64_relocate_new_kernel routine which does that copy is not overwritten,
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| 34 | * all code and data needed by arm64_relocate_new_kernel must be between the
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| 35 | * symbols arm64_relocate_new_kernel and arm64_relocate_new_kernel_end. The
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| 36 | * machine_kexec() routine will copy arm64_relocate_new_kernel to the kexec
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| 37 | * safe memory that has been set up to be preserved during the copy operation.
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| 38 | */
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| 39 | SYM_CODE_START(arm64_relocate_new_kernel)
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| 40 | /*
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| 41 | * The kimage structure isn't allocated specially and may be clobbered
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| 42 | * during relocation. We must load any values we need from it prior to
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| 43 | * any relocation occurring.
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| 44 | */
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| 45 | ldr x28, [x0, #KIMAGE_START]
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| 46 | ldr x27, [x0, #KIMAGE_ARCH_EL2_VECTORS]
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| 47 | ldr x26, [x0, #KIMAGE_ARCH_DTB_MEM]
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| 48 |
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| 49 | /* Setup the list loop variables. */
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| 50 | ldr x18, [x0, #KIMAGE_ARCH_ZERO_PAGE] /* x18 = zero page for BBM */
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| 51 | ldr x17, [x0, #KIMAGE_ARCH_TTBR1] /* x17 = linear map copy */
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| 52 | ldr x16, [x0, #KIMAGE_HEAD] /* x16 = kimage_head */
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| 53 | ldr x22, [x0, #KIMAGE_ARCH_PHYS_OFFSET] /* x22 phys_offset */
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| 54 | raw_dcache_line_size x15, x1 /* x15 = dcache line size */
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| 55 | break_before_make_ttbr_switch x18, x17, x1, x2 /* set linear map */
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| 56 | .Lloop:
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| 57 | and x12, x16, PAGE_MASK /* x12 = addr */
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| 58 | sub x12, x12, x22 /* Convert x12 to virt */
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| 59 | /* Test the entry flags. */
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| 60 | .Ltest_source:
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| 61 | tbz x16, IND_SOURCE_BIT, .Ltest_indirection
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| 62 |
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| 63 | /* Invalidate dest page to PoC. */
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| 64 | mov x19, x13
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| 65 | copy_page x13, x12, x1, x2, x3, x4, x5, x6, x7, x8
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| 66 | add x1, x19, #PAGE_SIZE
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| 67 | dcache_by_myline_op_nosync civac, x19, x1, x15, x20
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| 68 | dsb sy
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| 69 | b .Lnext
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| 70 | .Ltest_indirection:
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| 71 | tbz x16, IND_INDIRECTION_BIT, .Ltest_destination
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| 72 | mov x14, x12 /* ptr = addr */
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| 73 | b .Lnext
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| 74 | .Ltest_destination:
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| 75 | tbz x16, IND_DESTINATION_BIT, .Lnext
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| 76 | mov x13, x12 /* dest = addr */
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| 77 | .Lnext:
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| 78 | ldr x16, [x14], #8 /* entry = *ptr++ */
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| 79 | tbz x16, IND_DONE_BIT, .Lloop /* while (!(entry & DONE)) */
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| 80 | /* wait for writes from copy_page to finish */
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| 81 | dsb nsh
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| 82 | ic iallu
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| 83 | dsb nsh
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| 84 | isb
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| 85 | turn_off_mmu x12, x13
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| 86 |
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| 87 | /* Start new image. */
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| 88 | cbz x27, .Lel1
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| 89 | mov x1, x28 /* kernel entry point */
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| 90 | mov x2, x26 /* dtb address */
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| 91 | mov x3, xzr
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| 92 | mov x4, xzr
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| 93 | mov x0, #HVC_SOFT_RESTART
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| 94 | hvc #0 /* Jumps from el2 */
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| 95 | .Lel1:
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| 96 | mov x0, x26 /* dtb address */
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| 97 | mov x1, xzr
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| 98 | mov x2, xzr
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| 99 | mov x3, xzr
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| 100 | br x28 /* Jumps from el1 */
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| 101 | SYM_CODE_END(arm64_relocate_new_kernel)
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