| 1 |
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| 2 | |
| 3 | * Atomic operations for the Hexagon architecture
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| 4 | *
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| 5 | * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
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| 6 |
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| 7 |
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| 8 | #ifndef _ASM_ATOMIC_H
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| 9 | #define _ASM_ATOMIC_H
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| 10 |
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| 11 | #include <linux/types.h>
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| 12 | #include <asm/cmpxchg.h>
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| 13 | #include <asm/barrier.h>
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| 14 |
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| 15 |
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| 16 |
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| 17 | static inline void arch_atomic_set(atomic_t *v, int new)
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| 18 | {
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| 19 | asm volatile(
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| 20 | "1: r6 = memw_locked(%0);\n"
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| 21 | " memw_locked(%0,p0) = %1;\n"
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| 22 | " if (!P0) jump 1b;\n"
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| 23 | :
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| 24 | : "r" (&v->counter), "r" (new)
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| 25 | : "memory", "p0", "r6"
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| 26 | );
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| 27 | }
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| 28 |
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| 29 | #define arch_atomic_set_release(v, i) arch_atomic_set((v), (i))
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| 30 |
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| 31 | #define arch_atomic_read(v) READ_ONCE((v)->counter)
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| 32 |
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| 33 | #define ATOMIC_OP(op) \
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| 34 | static inline void arch_atomic_##op(int i, atomic_t *v) \
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| 35 | { \
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| 36 | int output; \
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| 37 | \
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| 38 | __asm__ __volatile__ ( \
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| 39 | "1: %0 = memw_locked(%1);\n" \
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| 40 | " %0 = "#op "(%0,%2);\n" \
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| 41 | " memw_locked(%1,P3)=%0;\n" \
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| 42 | " if (!P3) jump 1b;\n" \
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| 43 | : "=&r" (output) \
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| 44 | : "r" (&v->counter), "r" (i) \
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| 45 | : "memory", "p3" \
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| 46 | ); \
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| 47 | } \
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| 48 |
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| 49 | #define ATOMIC_OP_RETURN(op) \
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| 50 | static inline int arch_atomic_##op##_return(int i, atomic_t *v) \
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| 51 | { \
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| 52 | int output; \
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| 53 | \
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| 54 | __asm__ __volatile__ ( \
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| 55 | "1: %0 = memw_locked(%1);\n" \
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| 56 | " %0 = "#op "(%0,%2);\n" \
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| 57 | " memw_locked(%1,P3)=%0;\n" \
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| 58 | " if (!P3) jump 1b;\n" \
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| 59 | : "=&r" (output) \
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| 60 | : "r" (&v->counter), "r" (i) \
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| 61 | : "memory", "p3" \
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| 62 | ); \
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| 63 | return output; \
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| 64 | }
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| 65 |
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| 66 | #define ATOMIC_FETCH_OP(op) \
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| 67 | static inline int arch_atomic_fetch_##op(int i, atomic_t *v) \
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| 68 | { \
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| 69 | int output, val; \
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| 70 | \
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| 71 | __asm__ __volatile__ ( \
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| 72 | "1: %0 = memw_locked(%2);\n" \
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| 73 | " %1 = "#op "(%0,%3);\n" \
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| 74 | " memw_locked(%2,P3)=%1;\n" \
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| 75 | " if (!P3) jump 1b;\n" \
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| 76 | : "=&r" (output), "=&r" (val) \
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| 77 | : "r" (&v->counter), "r" (i) \
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| 78 | : "memory", "p3" \
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| 79 | ); \
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| 80 | return output; \
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| 81 | }
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| 82 |
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| 83 | #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op)
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| 84 |
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| 85 | ATOMIC_OPS(add)
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| 86 | ATOMIC_OPS(sub)
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| 87 |
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| 88 | #define arch_atomic_add_return arch_atomic_add_return
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| 89 | #define arch_atomic_sub_return arch_atomic_sub_return
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| 90 | #define arch_atomic_fetch_add arch_atomic_fetch_add
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| 91 | #define arch_atomic_fetch_sub arch_atomic_fetch_sub
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| 92 |
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| 93 | #undef ATOMIC_OPS
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| 94 | #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
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| 95 |
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| 96 | ATOMIC_OPS(and)
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| 97 | ATOMIC_OPS(or)
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| 98 | ATOMIC_OPS(xor)
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| 99 |
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| 100 | #define arch_atomic_fetch_and arch_atomic_fetch_and
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| 101 | #define arch_atomic_fetch_or arch_atomic_fetch_or
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| 102 | #define arch_atomic_fetch_xor arch_atomic_fetch_xor
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| 103 |
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| 104 | #undef ATOMIC_OPS
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| 105 | #undef ATOMIC_FETCH_OP
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| 106 | #undef ATOMIC_OP_RETURN
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| 107 | #undef ATOMIC_OP
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| 108 |
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| 109 | static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
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| 110 | {
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| 111 | int __oldval;
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| 112 | register int tmp;
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| 113 |
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| 114 | asm volatile(
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| 115 | "1: %0 = memw_locked(%2);"
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| 116 | " {"
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| 117 | " p3 = cmp.eq(%0, %4);"
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| 118 | " if (p3.new) jump:nt 2f;"
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| 119 | " %1 = add(%0, %3);"
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| 120 | " }"
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| 121 | " memw_locked(%2, p3) = %1;"
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| 122 | " {"
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| 123 | " if (!p3) jump 1b;"
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| 124 | " }"
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| 125 | "2:"
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| 126 | : "=&r" (__oldval), "=&r" (tmp)
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| 127 | : "r" (v), "r" (a), "r" (u)
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| 128 | : "memory", "p3"
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| 129 | );
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| 130 | return __oldval;
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| 131 | }
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| 132 | #define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless
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| 133 |
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| 134 | #endif
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