| 1 |
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| 2 | |
| 3 | * Cache flush operations for the Hexagon architecture
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| 4 | *
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| 5 | * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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| 6 |
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| 7 |
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| 8 | #ifndef _ASM_CACHEFLUSH_H
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| 9 | #define _ASM_CACHEFLUSH_H
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| 10 |
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| 11 | #include <linux/mm_types.h>
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| 12 |
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| 13 | |
| 14 | *
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| 15 | * - flush_cache_all() flushes entire cache
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| 16 | * - flush_cache_mm(mm) flushes the specified mm context's cache lines
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| 17 | * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
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| 18 | * - flush_cache_range(vma, start, end) flushes a range of pages
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| 19 | * - flush_icache_range(start, end) flush a range of instructions
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| 20 | * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
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| 21 | * - flush_icache_pages(vma, pg, nr) flushes(invalidates) nr pages for icache
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| 22 | *
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| 23 | * Need to doublecheck which one is really needed for ptrace stuff to work.
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| 24 |
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| 25 | #define LINESIZE 32
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| 26 | #define LINEBITS 5
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| 27 |
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| 28 | |
| 29 | * Flush Dcache range through current map.
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| 30 |
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| 31 | extern void flush_dcache_range(unsigned long start, unsigned long end);
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| 32 | #define flush_dcache_range flush_dcache_range
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| 33 |
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| 34 | |
| 35 | * Flush Icache range through current map.
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| 36 |
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| 37 | extern void flush_icache_range(unsigned long start, unsigned long end);
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| 38 | #define flush_icache_range flush_icache_range
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| 39 |
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| 40 | |
| 41 | * Memory-management related flushes are there to ensure in non-physically
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| 42 | * indexed cache schemes that stale lines belonging to a given ASID aren't
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| 43 | * in the cache to confuse things. The prototype Hexagon Virtual Machine
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| 44 | * only uses a single ASID for all user-mode maps, which should
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| 45 | * mean that they aren't necessary. A brute-force, flush-everything
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| 46 | * implementation, with the name xxxxx_hexagon() is present in
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| 47 | * arch/hexagon/mm/cache.c, but let's not wire it up until we know
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| 48 | * it is needed.
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| 49 |
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| 50 | extern void flush_cache_all_hexagon(void);
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| 51 |
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| 52 | |
| 53 | * This may or may not ever have to be non-null, depending on the
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| 54 | * virtual machine MMU. For a native kernel, it's definitiely a no-op
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| 55 | *
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| 56 | * This is also the place where deferred cache coherency stuff seems
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| 57 | * to happen, classically... but instead we do it like ia64 and
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| 58 | * clean the cache when the PTE is set.
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| 59 | *
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| 60 |
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| 61 | static inline void update_mmu_cache_range(struct vm_fault *vmf,
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| 62 | struct vm_area_struct *vma, unsigned long address,
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| 63 | pte_t *ptep, unsigned int nr)
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| 64 | {
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| 65 |
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| 66 | }
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| 67 |
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| 68 | #define update_mmu_cache(vma, addr, ptep) \
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| 69 | update_mmu_cache_range(NULL, vma, addr, ptep, 1)
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| 70 |
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| 71 | void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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| 72 | unsigned long vaddr, void *dst, void *src, int len);
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| 73 | #define copy_to_user_page copy_to_user_page
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| 74 |
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| 75 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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| 76 | memcpy(dst, src, len)
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| 77 |
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| 78 | extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
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| 79 | extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);
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| 80 |
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| 81 | #include <asm-generic/cacheflush.h>
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| 82 |
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| 83 | #endif
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