| 1 | |
| 2 | |
| 3 | * Time related functions for Hexagon architecture
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| 4 | *
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| 5 | * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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| 6 |
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| 7 |
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| 8 | #include <linux/init.h>
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| 9 | #include <linux/delay.h>
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| 10 | #include <linux/clockchips.h>
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| 11 | #include <linux/clocksource.h>
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| 12 | #include <linux/interrupt.h>
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| 13 | #include <linux/err.h>
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| 14 | #include <linux/platform_device.h>
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| 15 | #include <linux/ioport.h>
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| 16 | #include <linux/of.h>
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| 17 | #include <linux/of_address.h>
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| 18 | #include <linux/of_irq.h>
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| 19 | #include <linux/module.h>
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| 20 |
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| 21 | #include <asm/hexagon_vm.h>
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| 22 | #include <asm/time.h>
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| 23 |
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| 24 | #define TIMER_ENABLE BIT(0)
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| 25 |
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| 26 | |
| 27 | * For the clocksource we need:
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| 28 | * pcycle frequency (600MHz)
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| 29 | * For the loops_per_jiffy we need:
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| 30 | * thread/cpu frequency (100MHz)
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| 31 | * And for the timer, we need:
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| 32 | * sleep clock rate
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| 33 |
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| 34 |
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| 35 | cycles_t pcycle_freq_mhz;
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| 36 | cycles_t thread_freq_mhz;
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| 37 | cycles_t sleep_clk_freq;
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| 38 |
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| 39 | |
| 40 | * 8x50 HDD Specs 5-8. Simulator co-sim not fixed until
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| 41 | * release 1.1, and then it's "adjustable" and probably not defaulted.
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| 42 |
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| 43 | #define RTOS_TIMER_INT 3
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| 44 | #define RTOS_TIMER_REGS_ADDR 0xAB000000UL
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| 45 |
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| 46 | static struct resource rtos_timer_resources[] = {
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| 47 | {
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| 48 | .start = RTOS_TIMER_REGS_ADDR,
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| 49 | .end = RTOS_TIMER_REGS_ADDR+PAGE_SIZE-1,
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| 50 | .flags = IORESOURCE_MEM,
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| 51 | },
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| 52 | };
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| 53 |
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| 54 | static struct platform_device rtos_timer_device = {
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| 55 | .name = "rtos_timer",
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| 56 | .id = -1,
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| 57 | .num_resources = ARRAY_SIZE(rtos_timer_resources),
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| 58 | .resource = rtos_timer_resources,
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| 59 | };
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| 60 |
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| 61 |
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| 62 | struct adsp_hw_timer_struct {
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| 63 | u32 match;
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| 64 | u32 count;
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| 65 | u32 enable;
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| 66 | u32 clear;
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| 67 | };
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| 68 |
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| 69 |
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| 70 | static __iomem struct adsp_hw_timer_struct *rtos_timer;
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| 71 |
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| 72 | static u64 timer_get_cycles(struct clocksource *cs)
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| 73 | {
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| 74 | return (u64) __vmgettime();
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| 75 | }
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| 76 |
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| 77 | static struct clocksource hexagon_clocksource = {
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| 78 | .name = "pcycles",
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| 79 | .rating = 250,
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| 80 | .read = timer_get_cycles,
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| 81 | .mask = CLOCKSOURCE_MASK(64),
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| 82 | .flags = CLOCK_SOURCE_IS_CONTINUOUS,
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| 83 | };
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| 84 |
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| 85 | static int set_next_event(unsigned long delta, struct clock_event_device *evt)
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| 86 | {
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| 87 |
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| 88 |
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| 89 | iowrite32(1, &rtos_timer->clear);
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| 90 | iowrite32(0, &rtos_timer->clear);
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| 91 |
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| 92 | iowrite32(delta, &rtos_timer->match);
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| 93 | iowrite32(TIMER_ENABLE, &rtos_timer->enable);
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| 94 | return 0;
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| 95 | }
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| 96 |
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| 97 | #ifdef CONFIG_SMP
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| 98 |
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| 99 | static void broadcast(const struct cpumask *mask)
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| 100 | {
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| 101 | send_ipi(mask, IPI_TIMER);
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| 102 | }
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| 103 | #endif
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| 104 |
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| 105 |
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| 106 | static struct clock_event_device hexagon_clockevent_dev = {
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| 107 | .name = "clockevent",
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| 108 | .features = CLOCK_EVT_FEAT_ONESHOT,
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| 109 | .rating = 400,
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| 110 | .irq = RTOS_TIMER_INT,
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| 111 | .set_next_event = set_next_event,
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| 112 | #ifdef CONFIG_SMP
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| 113 | .broadcast = broadcast,
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| 114 | #endif
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| 115 | };
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| 116 |
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| 117 | #ifdef CONFIG_SMP
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| 118 | static DEFINE_PER_CPU(struct clock_event_device, clock_events);
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| 119 |
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| 120 | void setup_percpu_clockdev(void)
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| 121 | {
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| 122 | int cpu = smp_processor_id();
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| 123 | struct clock_event_device *ce_dev = &hexagon_clockevent_dev;
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| 124 | struct clock_event_device *dummy_clock_dev =
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| 125 | &per_cpu(clock_events, cpu);
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| 126 |
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| 127 | memcpy(dummy_clock_dev, ce_dev, sizeof(*dummy_clock_dev));
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| 128 | INIT_LIST_HEAD(&dummy_clock_dev->list);
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| 129 |
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| 130 | dummy_clock_dev->features = CLOCK_EVT_FEAT_DUMMY;
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| 131 | dummy_clock_dev->cpumask = cpumask_of(cpu);
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| 132 |
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| 133 | clockevents_register_device(dummy_clock_dev);
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| 134 | }
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| 135 |
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| 136 |
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| 137 | void ipi_timer(void)
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| 138 | {
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| 139 | int cpu = smp_processor_id();
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| 140 | struct clock_event_device *ce_dev = &per_cpu(clock_events, cpu);
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| 141 |
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| 142 | ce_dev->event_handler(ce_dev);
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| 143 | }
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| 144 | #endif
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| 145 |
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| 146 | static irqreturn_t timer_interrupt(int irq, void *devid)
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| 147 | {
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| 148 | struct clock_event_device *ce_dev = &hexagon_clockevent_dev;
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| 149 |
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| 150 | iowrite32(0, &rtos_timer->enable);
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| 151 | ce_dev->event_handler(ce_dev);
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| 152 |
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| 153 | return IRQ_HANDLED;
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| 154 | }
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| 155 |
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| 156 | |
| 157 | * time_init_deferred - called by start_kernel to set up timer/clock source
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| 158 | *
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| 159 | * Install the IRQ handler for the clock, setup timers.
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| 160 | * This is done late, as that way, we can use ioremap().
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| 161 | *
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| 162 | * This runs just before the delay loop is calibrated, and
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| 163 | * is used for delay calibration.
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| 164 |
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| 165 | static void __init time_init_deferred(void)
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| 166 | {
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| 167 | struct resource *resource = NULL;
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| 168 | struct clock_event_device *ce_dev = &hexagon_clockevent_dev;
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| 169 | unsigned long flag = IRQF_TIMER | IRQF_TRIGGER_RISING;
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| 170 |
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| 171 | ce_dev->cpumask = cpu_all_mask;
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| 172 |
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| 173 | resource = rtos_timer_device.resource;
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| 174 |
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| 175 |
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| 176 | rtos_timer = ioremap(resource->start, resource_size(resource));
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| 177 |
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| 178 | if (!rtos_timer) {
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| 179 | release_mem_region(resource->start, resource_size(resource));
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| 180 | }
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| 181 | clocksource_register_khz(&hexagon_clocksource, pcycle_freq_mhz * 1000);
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| 182 |
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| 183 |
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| 184 |
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| 185 | |
| 186 | * Last arg is some guaranteed seconds for which the conversion will
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| 187 | * work without overflow.
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| 188 |
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| 189 | clockevents_calc_mult_shift(ce_dev, sleep_clk_freq, 4);
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| 190 |
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| 191 | ce_dev->max_delta_ns = clockevent_delta2ns(0x7fffffff, ce_dev);
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| 192 | ce_dev->max_delta_ticks = 0x7fffffff;
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| 193 | ce_dev->min_delta_ns = clockevent_delta2ns(0xf, ce_dev);
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| 194 | ce_dev->min_delta_ticks = 0xf;
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| 195 |
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| 196 | #ifdef CONFIG_SMP
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| 197 | setup_percpu_clockdev();
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| 198 | #endif
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| 199 |
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| 200 | clockevents_register_device(ce_dev);
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| 201 | if (request_irq(ce_dev->irq, timer_interrupt, flag, "rtos_timer", NULL))
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| 202 | pr_err("Failed to register rtos_timer interrupt\n");
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| 203 | }
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| 204 |
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| 205 | void __init time_init(void)
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| 206 | {
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| 207 | late_time_init = time_init_deferred;
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| 208 | }
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| 209 |
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| 210 | void __delay(unsigned long cycles)
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| 211 | {
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| 212 | unsigned long long start = __vmgettime();
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| 213 |
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| 214 | while ((__vmgettime() - start) < cycles)
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| 215 | cpu_relax();
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| 216 | }
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| 217 | EXPORT_SYMBOL(__delay);
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| 218 |
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| 219 | |
| 220 | * This could become parametric or perhaps even computed at run-time,
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| 221 | * but for now we take the observed simulator jitter.
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| 222 |
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| 223 | static long long fudgefactor = 350;
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| 224 |
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| 225 | void __udelay(unsigned long usecs)
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| 226 | {
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| 227 | unsigned long long start = __vmgettime();
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| 228 | unsigned long long finish = (pcycle_freq_mhz * usecs) - fudgefactor;
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| 229 |
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| 230 | while ((__vmgettime() - start) < finish)
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| 231 | cpu_relax();
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| 232 | }
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| 233 | EXPORT_SYMBOL(__udelay);
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| 234 |
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| 235 | bool delay_read_timer(unsigned long *timer_val)
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| 236 | {
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| 237 | *timer_val = __vmgettime();
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| 238 | return true;
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| 239 | }
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