| 1 |
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| 2 | |
| 3 | * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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| 4 |
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| 5 | #ifndef _ASM_CACHEFLUSH_H
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| 6 | #define _ASM_CACHEFLUSH_H
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| 7 |
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| 8 | #include <linux/mm.h>
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| 9 | #include <asm/cpu-info.h>
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| 10 | #include <asm/cacheops.h>
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| 11 |
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| 12 | static inline bool cache_present(struct cache_desc *cdesc)
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| 13 | {
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| 14 | return cdesc->flags & CACHE_PRESENT;
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| 15 | }
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| 16 |
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| 17 | static inline bool cache_private(struct cache_desc *cdesc)
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| 18 | {
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| 19 | return cdesc->flags & CACHE_PRIVATE;
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| 20 | }
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| 21 |
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| 22 | static inline bool cache_inclusive(struct cache_desc *cdesc)
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| 23 | {
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| 24 | return cdesc->flags & CACHE_INCLUSIVE;
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| 25 | }
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| 26 |
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| 27 | static inline unsigned int cpu_last_level_cache_line_size(void)
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| 28 | {
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| 29 | int cache_present = boot_cpu_data.cache_leaves_present;
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| 30 |
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| 31 | return boot_cpu_data.cache_leaves[cache_present - 1].linesz;
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| 32 | }
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| 33 |
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| 34 | asmlinkage void __flush_cache_all(void);
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| 35 |
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| 36 | |
| 37 | * LoongArch maintains ICache/DCache coherency by hardware,
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| 38 | * we just need "ibar" to avoid instruction hazard here.
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| 39 |
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| 40 | static inline void local_flush_icache_all(void)
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| 41 | {
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| 42 | asm volatile ("ibar\t0\n"::);
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| 43 | }
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| 44 |
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| 45 | static inline void local_flush_icache_range(unsigned long start, unsigned long end)
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| 46 | {
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| 47 | asm volatile ("ibar\t0\n"::);
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| 48 | }
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| 49 |
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| 50 | #define flush_icache_all local_flush_icache_all
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| 51 | #define flush_icache_range local_flush_icache_range
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| 52 | #define flush_icache_user_range local_flush_icache_range
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| 53 |
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| 54 | #define flush_cache_all() do { } while (0)
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| 55 | #define flush_cache_mm(mm) do { } while (0)
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| 56 | #define flush_cache_dup_mm(mm) do { } while (0)
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| 57 | #define flush_cache_range(vma, start, end) do { } while (0)
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| 58 | #define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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| 59 | #define flush_cache_vmap(start, end) do { } while (0)
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| 60 | #define flush_cache_vunmap(start, end) do { } while (0)
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| 61 | #define flush_icache_user_page(vma, page, addr, len) do { } while (0)
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| 62 | #define flush_dcache_mmap_lock(mapping) do { } while (0)
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| 63 | #define flush_dcache_mmap_unlock(mapping) do { } while (0)
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| 64 |
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| 65 | #define cache_op(op, addr) \
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| 66 | __asm__ __volatile__( \
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| 67 | " cacop %0, %1 \n" \
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| 68 | : \
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| 69 | : "i" (op), "ZC" (*(unsigned char *)(addr)))
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| 70 |
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| 71 | static inline void flush_cache_line(int leaf, unsigned long addr)
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| 72 | {
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| 73 | switch (leaf) {
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| 74 | case Cache_LEAF0:
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| 75 | cache_op(Index_Writeback_Inv_LEAF0, addr);
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| 76 | break;
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| 77 | case Cache_LEAF1:
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| 78 | cache_op(Index_Writeback_Inv_LEAF1, addr);
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| 79 | break;
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| 80 | case Cache_LEAF2:
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| 81 | cache_op(Index_Writeback_Inv_LEAF2, addr);
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| 82 | break;
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| 83 | case Cache_LEAF3:
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| 84 | cache_op(Index_Writeback_Inv_LEAF3, addr);
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| 85 | break;
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| 86 | case Cache_LEAF4:
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| 87 | cache_op(Index_Writeback_Inv_LEAF4, addr);
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| 88 | break;
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| 89 | case Cache_LEAF5:
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| 90 | cache_op(Index_Writeback_Inv_LEAF5, addr);
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| 91 | break;
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| 92 | default:
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| 93 | break;
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| 94 | }
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| 95 | }
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| 96 |
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| 97 | #include <asm-generic/cacheflush.h>
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| 98 |
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| 99 | #endif
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