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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2008-2009 Michal Simek <[email protected]>
4 * Copyright (C) 2008-2009 PetaLogix
5 * Copyright (C) 2006 Atmark Techno, Inc.
6 */
7
8#ifndef _ASM_MICROBLAZE_PGTABLE_H
9#define _ASM_MICROBLAZE_PGTABLE_H
10
11#include <asm/setup.h>
12
13#ifndef __ASSEMBLER__
14extern int mem_init_done;
15#endif
16
17#include <asm-generic/pgtable-nopmd.h>
18
19#ifdef __KERNEL__
20#ifndef __ASSEMBLER__
21
22#include <linux/sched.h>
23#include <linux/threads.h>
24#include <asm/processor.h> /* For TASK_SIZE */
25#include <asm/mmu.h>
26#include <asm/page.h>
27
28extern unsigned long va_to_phys(unsigned long address);
29extern pte_t *va_to_pte(unsigned long address);
30
31/*
32 * The following only work if pte_present() is true.
33 * Undefined behaviour if not..
34 */
35
36/* Start and end of the vmalloc area. */
37/* Make sure to map the vmalloc area above the pinned kernel memory area
38 of 32Mb. */
39#define VMALLOC_START (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE)
40#define VMALLOC_END ioremap_bot
41
42#endif /* __ASSEMBLER__ */
43
44/*
45 * Macro to mark a page protection value as "uncacheable".
46 */
47
48#define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \
49 _PAGE_WRITETHRU)
50
51#define pgprot_noncached(prot) \
52 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
53 _PAGE_NO_CACHE | _PAGE_GUARDED))
54
55#define pgprot_noncached_wc(prot) \
56 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
57 _PAGE_NO_CACHE))
58
59/*
60 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
61 * table containing PTEs, together with a set of 16 segment registers, to
62 * define the virtual to physical address mapping.
63 *
64 * We use the hash table as an extended TLB, i.e. a cache of currently
65 * active mappings. We maintain a two-level page table tree, much
66 * like that used by the i386, for the sake of the Linux memory
67 * management code. Low-level assembler code in hashtable.S
68 * (procedure hash_page) is responsible for extracting ptes from the
69 * tree and putting them into the hash table when necessary, and
70 * updating the accessed and modified bits in the page table tree.
71 */
72
73/*
74 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
75 * instruction and data sides share a unified, 64-entry, semi-associative
76 * TLB which is maintained totally under software control. In addition, the
77 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
78 * TLB which serves as a first level to the shared TLB. These two TLBs are
79 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions).
80 */
81
82/*
83 * The normal case is that PTEs are 32-bits and we have a 1-page
84 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
85 *
86 */
87
88/* PGDIR_SHIFT determines what a top-level page table entry can map */
89#define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
90#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
91#define PGDIR_MASK (~(PGDIR_SIZE-1))
92
93/*
94 * entries per page directory level: our page-table tree is two-level, so
95 * we don't really have any PMD directory.
96 */
97#define PTRS_PER_PTE (1 << PTE_SHIFT)
98#define PTRS_PER_PMD 1
99#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
100
101#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
102
103#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
104#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
105
106#define pte_ERROR(e) \
107 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \
108 __FILE__, __LINE__, pte_val(e))
109#define pgd_ERROR(e) \
110 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
111 __FILE__, __LINE__, pgd_val(e))
112
113/*
114 * Bits in a linux-style PTE. These match the bits in the
115 * (hardware-defined) PTE as closely as possible.
116 */
117
118/* There are several potential gotchas here. The hardware TLBLO
119 * field looks like this:
120 *
121 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
122 * RPN..................... 0 0 EX WR ZSEL....... W I M G
123 *
124 * Where possible we make the Linux PTE bits match up with this
125 *
126 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can
127 * support down to 1k pages), this is done in the TLBMiss exception
128 * handler.
129 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
130 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
131 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
132 * zone.
133 * - PRESENT *must* be in the bottom two bits because swap PTEs use the top
134 * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we
135 * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler
136 * before the TLB entry is loaded.
137 * - All other bits of the PTE are loaded into TLBLO without
138 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
139 * software PTE bits. We actually use bits 21, 24, 25, and
140 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
141 * PRESENT.
142 */
143
144/* Definitions for MicroBlaze. */
145#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
146#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
147#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
148#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
149#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
150#define _PAGE_RW 0x040 /* software: Writes permitted */
151#define _PAGE_DIRTY 0x080 /* software: dirty page */
152#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
153#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
154#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
155#define _PMD_PRESENT PAGE_MASK
156
157/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
158#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
159
160/*
161 * Some bits are unused...
162 */
163#ifndef _PAGE_HASHPTE
164#define _PAGE_HASHPTE 0
165#endif
166#ifndef _PTE_NONE_MASK
167#define _PTE_NONE_MASK 0
168#endif
169#ifndef _PAGE_SHARED
170#define _PAGE_SHARED 0
171#endif
172#ifndef _PAGE_EXEC
173#define _PAGE_EXEC 0
174#endif
175
176#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
177
178/*
179 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
180 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
181 * to have it in the Linux PTE, and in fact the bit could be reused for
182 * another purpose. -- paulus.
183 */
184#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
185#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
186
187#define _PAGE_KERNEL \
188 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC)
189
190#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
191
192#define PAGE_NONE __pgprot(_PAGE_BASE)
193#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
194#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
195#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
196#define PAGE_SHARED_X \
197 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
198#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
199#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
200
201#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
202#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED)
203#define PAGE_KERNEL_CI __pgprot(_PAGE_IO)
204
205/*
206 * We consider execute permission the same as read.
207 * Also, write permissions imply read permissions.
208 */
209
210#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
211#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
212#define pte_clear(mm, addr, ptep) \
213 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
214
215#define pmd_none(pmd) (!pmd_val(pmd))
216#define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0)
217#define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0)
218#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
219
220#define pte_page(x) (mem_map + (unsigned long) \
221 ((pte_val(x) - memory_start) >> PAGE_SHIFT))
222#define PFN_PTE_SHIFT PAGE_SHIFT
223
224#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
225
226#define pfn_pte(pfn, prot) \
227 __pte(((pte_basic_t)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot))
228
229#ifndef __ASSEMBLER__
230/*
231 * The following only work if pte_present() is true.
232 * Undefined behaviour if not..
233 */
234static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
235static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
236static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
237static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
238static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
239
240static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
241static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
242
243static inline pte_t pte_rdprotect(pte_t pte) \
244 { pte_val(pte) &= ~_PAGE_USER; return pte; }
245static inline pte_t pte_wrprotect(pte_t pte) \
246 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
247static inline pte_t pte_exprotect(pte_t pte) \
248 { pte_val(pte) &= ~_PAGE_EXEC; return pte; }
249static inline pte_t pte_mkclean(pte_t pte) \
250 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
251static inline pte_t pte_mkold(pte_t pte) \
252 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
253
254static inline pte_t pte_mkread(pte_t pte) \
255 { pte_val(pte) |= _PAGE_USER; return pte; }
256static inline pte_t pte_mkexec(pte_t pte) \
257 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
258static inline pte_t pte_mkwrite_novma(pte_t pte) \
259 { pte_val(pte) |= _PAGE_RW; return pte; }
260static inline pte_t pte_mkdirty(pte_t pte) \
261 { pte_val(pte) |= _PAGE_DIRTY; return pte; }
262static inline pte_t pte_mkyoung(pte_t pte) \
263 { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
264
265/*
266 * Conversion functions: convert a page and protection to a page entry,
267 * and a page entry and page directory to the page they refer to.
268 */
269
270static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot)
271{
272 pte_t pte;
273 pte_val(pte) = physpage | pgprot_val(pgprot);
274 return pte;
275}
276
277static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
278{
279 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
280 return pte;
281}
282
283/*
284 * Atomic PTE updates.
285 *
286 * pte_update clears and sets bit atomically, and returns
287 * the old pte value.
288 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
289 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
290 */
291static inline unsigned long pte_update(pte_t *p, unsigned long clr,
292 unsigned long set)
293{
294 unsigned long flags, old, tmp;
295
296 raw_local_irq_save(flags);
297
298 __asm__ __volatile__( "lw %0, %2, r0 \n"
299 "andn %1, %0, %3 \n"
300 "or %1, %1, %4 \n"
301 "sw %1, %2, r0 \n"
302 : "=&r" (old), "=&r" (tmp)
303 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
304 : "cc");
305
306 raw_local_irq_restore(flags);
307
308 return old;
309}
310
311/*
312 * set_pte stores a linux PTE into the linux page table.
313 */
314static inline void set_pte(pte_t *ptep, pte_t pte)
315{
316 *ptep = pte;
317}
318
319#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
320struct vm_area_struct;
321static inline bool ptep_test_and_clear_young(struct vm_area_struct *vma,
322 unsigned long address, pte_t *ptep)
323{
324 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0;
325}
326
327static inline int ptep_test_and_clear_dirty(struct mm_struct *mm,
328 unsigned long addr, pte_t *ptep)
329{
330 return (pte_update(ptep, \
331 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
332}
333
334#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
335static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
336 unsigned long addr, pte_t *ptep)
337{
338 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
339}
340
341/*static inline void ptep_set_wrprotect(struct mm_struct *mm,
342 unsigned long addr, pte_t *ptep)
343{
344 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
345}*/
346
347static inline void ptep_mkdirty(struct mm_struct *mm,
348 unsigned long addr, pte_t *ptep)
349{
350 pte_update(ptep, 0, _PAGE_DIRTY);
351}
352
353/*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/
354
355/* Convert pmd entry to page */
356/* our pmd entry is an effective address of pte table*/
357/* returns effective address of the pmd entry*/
358static inline unsigned long pmd_page_vaddr(pmd_t pmd)
359{
360 return ((unsigned long) (pmd_val(pmd) & PAGE_MASK));
361}
362
363/* returns pfn of the pmd entry*/
364#define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT)
365
366/* returns struct *page of the pmd entry*/
367#define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT))
368
369/* Find an entry in the third-level page table.. */
370
371extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
372
373/*
374 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
375 * are !pte_none() && !pte_present().
376 *
377 * 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
378 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
379 * <------------------ offset -------------------> E < type -> 0 0
380 *
381 * E is the exclusive marker that is not stored in swap entries.
382 */
383#define __swp_type(entry) ((entry).val & 0x1f)
384#define __swp_offset(entry) ((entry).val >> 6)
385#define __swp_entry(type, offset) \
386 ((swp_entry_t) { ((type) & 0x1f) | ((offset) << 6) })
387#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
388#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 })
389
390static inline bool pte_swp_exclusive(pte_t pte)
391{
392 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
393}
394
395static inline pte_t pte_swp_mkexclusive(pte_t pte)
396{
397 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
398 return pte;
399}
400
401static inline pte_t pte_swp_clear_exclusive(pte_t pte)
402{
403 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
404 return pte;
405}
406
407extern unsigned long iopa(unsigned long addr);
408
409/* Values for nocacheflag and cmode */
410/* These are not used by the APUS kernel_map, but prevents
411 * compilation errors.
412 */
413#define IOMAP_FULL_CACHING 0
414#define IOMAP_NOCACHE_SER 1
415#define IOMAP_NOCACHE_NONSER 2
416#define IOMAP_NO_COPYBACK 3
417
418void do_page_fault(struct pt_regs *regs, unsigned long address,
419 unsigned long error_code);
420
421void mapin_ram(void);
422int map_page(unsigned long va, phys_addr_t pa, int flags);
423
424extern int mem_init_done;
425
426asmlinkage void __init mmu_init(void);
427
428#endif /* __ASSEMBLER__ */
429#endif /* __KERNEL__ */
430
431#ifndef __ASSEMBLER__
432extern unsigned long ioremap_bot, ioremap_base;
433
434void setup_memory(void);
435#endif /* __ASSEMBLER__ */
436
437#endif /* _ASM_MICROBLAZE_PGTABLE_H */