| 1 | /* SPDX-License-Identifier: GPL-2.0 */
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| 2 | |
| 3 |
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| 4 | /*
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| 5 | * Divide operation for 32 bit integers.
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| 6 | * Input : Dividend in Reg r5
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| 7 | * Divisor in Reg r6
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| 8 | * Output: Result in Reg r3
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| 9 | */
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| 10 | .text
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| 11 | .globl __divsi3
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| 12 | .type __divsi3, @function
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| 13 | .ent __divsi3
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| 14 | __divsi3:
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| 15 | .frame r1, 0, r15
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| 16 |
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| 17 | addik r1, r1, -16
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| 18 | swi r28, r1, 0
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| 19 | swi r29, r1, 4
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| 20 | swi r30, r1, 8
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| 21 | swi r31, r1, 12
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| 22 |
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| 23 | beqi r6, div_by_zero /* div_by_zero - division error */
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| 24 | beqi r5, result_is_zero /* result is zero */
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| 25 | bgeid r5, r5_pos
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| 26 | xor r28, r5, r6 /* get the sign of the result */
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| 27 | rsubi r5, r5, 0 /* make r5 positive */
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| 28 | r5_pos:
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| 29 | bgei r6, r6_pos
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| 30 | rsubi r6, r6, 0 /* make r6 positive */
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| 31 | r6_pos:
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| 32 | addik r30, r0, 0 /* clear mod */
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| 33 | addik r3, r0, 0 /* clear div */
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| 34 | addik r29, r0, 32 /* initialize the loop count */
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| 35 |
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| 36 | /* first part try to find the first '1' in the r5 */
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| 37 | div0:
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| 38 | blti r5, div2 /* this traps r5 == 0x80000000 */
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| 39 | div1:
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| 40 | add r5, r5, r5 /* left shift logical r5 */
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| 41 | bgtid r5, div1
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| 42 | addik r29, r29, -1
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| 43 | div2:
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| 44 | /* left shift logical r5 get the '1' into the carry */
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| 45 | add r5, r5, r5
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| 46 | addc r30, r30, r30 /* move that bit into the mod register */
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| 47 | rsub r31, r6, r30 /* try to subtract (r30 a r6) */
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| 48 | blti r31, mod_too_small
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| 49 | /* move the r31 to mod since the result was positive */
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| 50 | or r30, r0, r31
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| 51 | addik r3, r3, 1
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| 52 | mod_too_small:
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| 53 | addik r29, r29, -1
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| 54 | beqi r29, loop_end
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| 55 | add r3, r3, r3 /* shift in the '1' into div */
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| 56 | bri div2 /* div2 */
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| 57 | loop_end:
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| 58 | bgei r28, return_here
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| 59 | brid return_here
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| 60 | rsubi r3, r3, 0 /* negate the result */
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| 61 | div_by_zero:
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| 62 | result_is_zero:
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| 63 | or r3, r0, r0 /* set result to 0 */
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| 64 | return_here:
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| 65 | /* restore values of csrs and that of r3 and the divisor and the dividend */
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| 66 | lwi r28, r1, 0
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| 67 | lwi r29, r1, 4
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| 68 | lwi r30, r1, 8
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| 69 | lwi r31, r1, 12
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| 70 | rtsd r15, 8
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| 71 | addik r1, r1, 16
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| 72 |
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| 73 | .size __divsi3, . - __divsi3
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| 74 | .end __divsi3
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