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1/*
2 * Copyright 2000, 2007-2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. <[email protected]
4 *
5 * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/ioport.h>
30#include <linux/mm.h>
31#include <linux/dma-map-ops.h> /* for dma_default_coherent */
32
33#include <asm/bootinfo.h>
34#include <asm/mipsregs.h>
35
36#include <au1000.h>
37
38static bool alchemy_dma_coherent(void)
39{
40 switch (alchemy_get_cputype()) {
41 case ALCHEMY_CPU_AU1000:
42 case ALCHEMY_CPU_AU1500:
43 case ALCHEMY_CPU_AU1100:
44 return false;
45 case ALCHEMY_CPU_AU1200:
46 /* Au1200 AB USB does not support coherent memory */
47 if ((read_c0_prid() & PRID_REV_MASK) == 0)
48 return false;
49 return true;
50 default:
51 return true;
52 }
53}
54
55void __init plat_mem_setup(void)
56{
57 alchemy_set_lpj();
58
59 if (au1xxx_cpu_needs_config_od())
60 /* Various early Au1xx0 errata corrected by this */
61 set_c0_config(1 << 19); /* Set Config[OD] */
62 else
63 /* Clear to obtain best system bus performance */
64 clear_c0_config(1 << 19); /* Clear Config[OD] */
65
66 dma_default_coherent = alchemy_dma_coherent();
67
68 board_setup(); /* board specific setup */
69
70 /* IO/MEM resources. */
71 set_io_port_base(0);
72 ioport_resource.start = IOPORT_RESOURCE_START;
73 ioport_resource.end = IOPORT_RESOURCE_END;
74 iomem_resource.start = IOMEM_RESOURCE_START;
75 iomem_resource.end = IOMEM_RESOURCE_END;
76}
77
78#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
79/* This routine should be valid for all Au1x based boards */
80phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
81{
82 unsigned long start = ALCHEMY_PCI_MEMWIN_START;
83 unsigned long end = ALCHEMY_PCI_MEMWIN_END;
84
85 /* Don't fixup 36-bit addresses */
86 if ((phys_addr >> 32) != 0)
87 return phys_addr;
88
89 /* Check for PCI memory window */
90 if (phys_addr >= start && (phys_addr + size - 1) <= end)
91 return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
92
93 /* default nop */
94 return phys_addr;
95}
96
97unsigned long io_remap_pfn_range_pfn(unsigned long pfn, unsigned long size)
98{
99 phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
100
101 return phys_addr >> PAGE_SHIFT;
102}
103EXPORT_SYMBOL(io_remap_pfn_range_pfn);
104
105#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */