| 1 | |
| 2 | * This file is subject to the terms and conditions of the GNU General Public
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| 3 | * License. See the file "COPYING" in the main directory of this archive
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| 4 | * for more details.
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| 5 | *
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| 6 | * Copyright (C) 2008 Maxime Bizon <[email protected]>
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| 7 |
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| 8 |
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| 9 | #include <linux/init.h>
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| 10 | #include <linux/kernel.h>
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| 11 | #include <linux/delay.h>
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| 12 | #include <linux/memblock.h>
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| 13 | #include <linux/ioport.h>
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| 14 | #include <linux/pm.h>
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| 15 | #include <asm/bmips.h>
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| 16 | #include <asm/bootinfo.h>
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| 17 | #include <asm/time.h>
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| 18 | #include <asm/reboot.h>
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| 19 | #include <asm/cacheflush.h>
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| 20 | #include <bcm63xx_board.h>
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| 21 | #include <bcm63xx_cpu.h>
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| 22 | #include <bcm63xx_regs.h>
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| 23 | #include <bcm63xx_io.h>
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| 24 | #include <bcm63xx_gpio.h>
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| 25 |
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| 26 | |
| 27 | * CBR addr doesn't change and we can cache it.
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| 28 | * For broken SoC/Bootloader CBR addr might also be provided via DT
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| 29 | * with "brcm,bmips-cbr-reg" in the "cpus" node.
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| 30 |
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| 31 | void __iomem *bmips_cbr_addr __read_mostly;
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| 32 |
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| 33 | void bcm63xx_machine_halt(void)
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| 34 | {
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| 35 | pr_info("System halted\n");
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| 36 | while (1)
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| 37 | ;
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| 38 | }
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| 39 |
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| 40 | static void bcm6348_a1_reboot(void)
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| 41 | {
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| 42 | u32 reg;
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| 43 |
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| 44 |
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| 45 | pr_info("soft-resetting all blocks ...\n");
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| 46 | reg = bcm_perf_readl(PERF_SOFTRESET_REG);
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| 47 | reg &= ~SOFTRESET_6348_ALL;
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| 48 | bcm_perf_writel(reg, PERF_SOFTRESET_REG);
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| 49 | mdelay(10);
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| 50 |
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| 51 | reg = bcm_perf_readl(PERF_SOFTRESET_REG);
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| 52 | reg |= SOFTRESET_6348_ALL;
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| 53 | bcm_perf_writel(reg, PERF_SOFTRESET_REG);
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| 54 | mdelay(10);
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| 55 |
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| 56 |
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| 57 | pr_info("jumping to reset vector.\n");
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| 58 |
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| 59 | set_c0_status(ST0_BEV | ST0_ERL);
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| 60 |
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| 61 | change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
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| 62 | __flush_cache_all();
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| 63 |
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| 64 | write_c0_wired(0);
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| 65 | __asm__ __volatile__(
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| 66 | "jr\t%0"
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| 67 | :
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| 68 | : "r" (0xbfc00000));
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| 69 | while (1)
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| 70 | ;
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| 71 | }
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| 72 |
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| 73 | void bcm63xx_machine_reboot(void)
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| 74 | {
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| 75 | u32 reg, perf_regs[2] = { 0, 0 };
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| 76 | unsigned int i;
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| 77 |
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| 78 |
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| 79 | switch (bcm63xx_get_cpu_id()) {
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| 80 | case BCM3368_CPU_ID:
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| 81 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
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| 82 | break;
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| 83 | case BCM6328_CPU_ID:
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| 84 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
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| 85 | break;
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| 86 | case BCM6338_CPU_ID:
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| 87 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
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| 88 | break;
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| 89 | case BCM6345_CPU_ID:
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| 90 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_6345;
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| 91 | break;
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| 92 | case BCM6348_CPU_ID:
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| 93 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
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| 94 | break;
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| 95 | case BCM6358_CPU_ID:
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| 96 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
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| 97 | break;
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| 98 | case BCM6362_CPU_ID:
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| 99 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
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| 100 | break;
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| 101 | }
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| 102 |
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| 103 | for (i = 0; i < 2; i++) {
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| 104 | if (!perf_regs[i])
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| 105 | break;
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| 106 |
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| 107 | reg = bcm_perf_readl(perf_regs[i]);
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| 108 | if (BCMCPU_IS_6348()) {
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| 109 | reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
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| 110 | reg |= EXTIRQ_CFG_CLEAR_ALL_6348;
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| 111 | } else {
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| 112 | reg &= ~EXTIRQ_CFG_MASK_ALL;
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| 113 | reg |= EXTIRQ_CFG_CLEAR_ALL;
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| 114 | }
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| 115 | bcm_perf_writel(reg, perf_regs[i]);
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| 116 | }
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| 117 |
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| 118 | if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
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| 119 | bcm6348_a1_reboot();
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| 120 |
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| 121 | pr_info("triggering watchdog soft-reset...\n");
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| 122 | if (BCMCPU_IS_6328()) {
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| 123 | bcm_wdt_writel(1, WDT_SOFTRESET_REG);
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| 124 | } else {
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| 125 | reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
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| 126 | reg |= SYS_PLL_SOFT_RESET;
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| 127 | bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
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| 128 | }
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| 129 | while (1)
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| 130 | ;
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| 131 | }
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| 132 |
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| 133 | static void __bcm63xx_machine_reboot(char *p)
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| 134 | {
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| 135 | bcm63xx_machine_reboot();
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| 136 | }
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| 137 |
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| 138 | |
| 139 | * return system type in /proc/cpuinfo
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| 140 |
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| 141 | const char *get_system_type(void)
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| 142 | {
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| 143 | static char buf[128];
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| 144 | snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%02X)",
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| 145 | board_get_name(),
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| 146 | bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
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| 147 | return buf;
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| 148 | }
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| 149 |
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| 150 | void __init plat_time_init(void)
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| 151 | {
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| 152 | mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
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| 153 | }
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| 154 |
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| 155 | void __init plat_mem_setup(void)
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| 156 | {
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| 157 | memblock_add(0, bcm63xx_get_memory_size());
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| 158 |
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| 159 | _machine_halt = bcm63xx_machine_halt;
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| 160 | _machine_restart = __bcm63xx_machine_reboot;
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| 161 | pm_power_off = bcm63xx_machine_halt;
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| 162 |
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| 163 | set_io_port_base(0);
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| 164 | ioport_resource.start = 0;
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| 165 | ioport_resource.end = ~0;
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| 166 |
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| 167 | board_setup();
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| 168 | }
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| 169 |
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| 170 | static int __init bcm63xx_register_devices(void)
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| 171 | {
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| 172 |
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| 173 | bcm63xx_gpio_init();
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| 174 |
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| 175 | return board_register_devices();
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| 176 | }
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| 177 |
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| 178 | arch_initcall(bcm63xx_register_devices);
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