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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee ([email protected])
7 *
8 * Definitions for BMIPS processors
9 */
10#ifndef _ASM_BMIPS_H
11#define _ASM_BMIPS_H
12
13#include <linux/compiler.h>
14#include <linux/linkage.h>
15#include <asm/addrspace.h>
16#include <asm/mipsregs.h>
17#include <asm/hazards.h>
18
19/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
20#define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \
21 (unsigned long) \
22 ((read_c0_brcm_cbr() >> 18) << 18)))
23
24#define BMIPS_RAC_CONFIG 0x00000000
25#define BMIPS_RAC_ADDRESS_RANGE 0x00000004
26#define BMIPS_RAC_CONFIG_1 0x00000008
27#define BMIPS_L2_CONFIG 0x0000000c
28#define BMIPS_LMB_CONTROL 0x0000001c
29#define BMIPS_SYSTEM_BASE 0x00000020
30#define BMIPS_PERF_GLOBAL_CONTROL 0x00020000
31#define BMIPS_PERF_CONTROL_0 0x00020004
32#define BMIPS_PERF_CONTROL_1 0x00020008
33#define BMIPS_PERF_COUNTER_0 0x00020010
34#define BMIPS_PERF_COUNTER_1 0x00020014
35#define BMIPS_PERF_COUNTER_2 0x00020018
36#define BMIPS_PERF_COUNTER_3 0x0002001c
37#define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000
38#define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000
39
40#define BMIPS_NMI_RESET_VEC 0x80000000
41#define BMIPS_WARM_RESTART_VEC 0x80000380
42
43#define ZSCM_REG_BASE 0x97000000
44
45#if !defined(__ASSEMBLER__)
46
47#include <linux/cpumask.h>
48#include <asm/r4kcache.h>
49#include <asm/smp-ops.h>
50
51extern const struct plat_smp_ops bmips43xx_smp_ops;
52extern const struct plat_smp_ops bmips5000_smp_ops;
53
54static inline int register_bmips_smp_ops(void)
55{
56#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
57 switch (current_cpu_type()) {
58 case CPU_BMIPS32:
59 case CPU_BMIPS3300:
60 return register_up_smp_ops();
61 case CPU_BMIPS4350:
62 case CPU_BMIPS4380:
63 register_smp_ops(&bmips43xx_smp_ops);
64 break;
65 case CPU_BMIPS5000:
66 register_smp_ops(&bmips5000_smp_ops);
67 break;
68 default:
69 return -ENODEV;
70 }
71
72 return 0;
73#else
74 return -ENODEV;
75#endif
76}
77
78extern char bmips_reset_nmi_vec[];
79extern char bmips_reset_nmi_vec_end[];
80extern char bmips_smp_movevec[];
81extern char bmips_smp_int_vec[];
82extern char bmips_smp_int_vec_end[];
83
84extern void __iomem *bmips_cbr_addr;
85extern int bmips_smp_enabled;
86extern int bmips_cpu_offset;
87extern cpumask_t bmips_booted_mask;
88extern unsigned long bmips_tp1_irqs;
89
90extern void bmips_ebase_setup(void);
91extern asmlinkage void plat_wired_tlb_setup(void);
92extern void bmips_cpu_setup(void);
93
94static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
95{
96 unsigned long ret;
97
98 barrier();
99 cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);
100 __sync();
101 _ssnop();
102 _ssnop();
103 _ssnop();
104 _ssnop();
105 _ssnop();
106 _ssnop();
107 _ssnop();
108 ret = read_c0_ddatalo();
109 _ssnop();
110
111 return ret;
112}
113
114static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
115{
116 write_c0_ddatalo(data);
117 _ssnop();
118 _ssnop();
119 _ssnop();
120 cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);
121 _ssnop();
122 _ssnop();
123 _ssnop();
124 barrier();
125}
126
127#endif /* !defined(__ASSEMBLER__) */
128
129#endif /* _ASM_BMIPS_H */