| 1 | |
| 2 | * Cache operations for the cache instruction.
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| 3 | *
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| 4 | * This file is subject to the terms and conditions of the GNU General Public
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| 5 | * License. See the file "COPYING" in the main directory of this archive
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| 6 | * for more details.
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| 7 | *
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| 8 | * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
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| 9 | * (C) Copyright 1999 Silicon Graphics, Inc.
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| 10 |
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| 11 | #ifndef __ASM_CACHEOPS_H
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| 12 | #define __ASM_CACHEOPS_H
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| 13 |
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| 14 | |
| 15 | * Most cache ops are split into a 2 bit field identifying the cache, and a 3
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| 16 | * bit field identifying the cache operation.
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| 17 |
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| 18 | #define CacheOp_Cache 0x03
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| 19 | #define CacheOp_Op 0x1c
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| 20 |
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| 21 | #define Cache_I 0x00
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| 22 | #define Cache_D 0x01
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| 23 | #define Cache_T 0x02
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| 24 | #define Cache_V 0x02
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| 25 | #define Cache_S 0x03
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| 26 |
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| 27 | #define Index_Writeback_Inv 0x00
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| 28 | #define Index_Load_Tag 0x04
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| 29 | #define Index_Store_Tag 0x08
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| 30 | #define Hit_Invalidate 0x10
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| 31 | #define Hit_Writeback_Inv 0x14
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| 32 | #define Hit_Writeback 0x18
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| 33 |
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| 34 | |
| 35 | * Cache Operations available on all MIPS processors with R4000-style caches
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| 36 |
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| 37 | #define Index_Invalidate_I (Cache_I | Index_Writeback_Inv)
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| 38 | #define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv)
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| 39 | #define Index_Load_Tag_I (Cache_I | Index_Load_Tag)
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| 40 | #define Index_Load_Tag_D (Cache_D | Index_Load_Tag)
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| 41 | #define Index_Store_Tag_I (Cache_I | Index_Store_Tag)
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| 42 | #define Index_Store_Tag_D (Cache_D | Index_Store_Tag)
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| 43 | #define Hit_Invalidate_I (Cache_I | Hit_Invalidate)
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| 44 | #define Hit_Invalidate_D (Cache_D | Hit_Invalidate)
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| 45 | #define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv)
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| 46 |
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| 47 | |
| 48 | * R4000-specific cacheops
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| 49 |
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| 50 | #define Create_Dirty_Excl_D (Cache_D | 0x0c)
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| 51 | #define Fill_I (Cache_I | 0x14)
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| 52 | #define Hit_Writeback_I (Cache_I | Hit_Writeback)
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| 53 | #define Hit_Writeback_D (Cache_D | Hit_Writeback)
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| 54 |
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| 55 | |
| 56 | * R4000SC and R4400SC-specific cacheops
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| 57 |
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| 58 | #define Cache_SI 0x02
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| 59 | #define Cache_SD 0x03
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| 60 |
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| 61 | #define Index_Invalidate_SI (Cache_SI | Index_Writeback_Inv)
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| 62 | #define Index_Writeback_Inv_SD (Cache_SD | Index_Writeback_Inv)
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| 63 | #define Index_Load_Tag_SI (Cache_SI | Index_Load_Tag)
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| 64 | #define Index_Load_Tag_SD (Cache_SD | Index_Load_Tag)
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| 65 | #define Index_Store_Tag_SI (Cache_SI | Index_Store_Tag)
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| 66 | #define Index_Store_Tag_SD (Cache_SD | Index_Store_Tag)
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| 67 | #define Create_Dirty_Excl_SD (Cache_SD | 0x0c)
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| 68 | #define Hit_Invalidate_SI (Cache_SI | Hit_Invalidate)
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| 69 | #define Hit_Invalidate_SD (Cache_SD | Hit_Invalidate)
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| 70 | #define Hit_Writeback_Inv_SD (Cache_SD | Hit_Writeback_Inv)
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| 71 | #define Hit_Writeback_SD (Cache_SD | Hit_Writeback)
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| 72 | #define Hit_Set_Virtual_SI (Cache_SI | 0x1c)
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| 73 | #define Hit_Set_Virtual_SD (Cache_SD | 0x1c)
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| 74 |
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| 75 | |
| 76 | * R5000-specific cacheops
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| 77 |
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| 78 | #define R5K_Page_Invalidate_S (Cache_S | 0x14)
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| 79 |
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| 80 | |
| 81 | * RM7000-specific cacheops
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| 82 |
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| 83 | #define Page_Invalidate_T (Cache_T | 0x14)
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| 84 | #define Index_Store_Tag_T (Cache_T | Index_Store_Tag)
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| 85 | #define Index_Load_Tag_T (Cache_T | Index_Load_Tag)
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| 86 |
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| 87 | |
| 88 | * R10000-specific cacheops
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| 89 | *
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| 90 | * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
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| 91 | * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
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| 92 |
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| 93 | #define Index_Writeback_Inv_S (Cache_S | Index_Writeback_Inv)
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| 94 | #define Index_Load_Tag_S (Cache_S | Index_Load_Tag)
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| 95 | #define Index_Store_Tag_S (Cache_S | Index_Store_Tag)
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| 96 | #define Hit_Invalidate_S (Cache_S | Hit_Invalidate)
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| 97 | #define Cache_Barrier 0x14
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| 98 | #define Hit_Writeback_Inv_S (Cache_S | Hit_Writeback_Inv)
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| 99 | #define Index_Load_Data_I (Cache_I | 0x18)
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| 100 | #define Index_Load_Data_D (Cache_D | 0x18)
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| 101 | #define Index_Load_Data_S (Cache_S | 0x18)
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| 102 | #define Index_Store_Data_I (Cache_I | 0x1c)
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| 103 | #define Index_Store_Data_D (Cache_D | 0x1c)
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| 104 | #define Index_Store_Data_S (Cache_S | 0x1c)
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| 105 |
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| 106 | |
| 107 | * Loongson2-specific cacheops
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| 108 |
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| 109 | #define Hit_Invalidate_I_Loongson2 (Cache_I | 0x00)
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| 110 |
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| 111 | |
| 112 | * Loongson3-specific cacheops
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| 113 |
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| 114 | #define Index_Writeback_Inv_V (Cache_V | Index_Writeback_Inv)
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| 115 |
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| 116 | #endif
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