| 1 | |
| 2 | * This file is subject to the terms and conditions of the GNU General Public
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| 3 | * License. See the file "COPYING" in the main directory of this archive
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| 4 | * for more details.
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| 5 | *
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| 6 | * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
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| 7 | * Copyright (C) 1996 by Paul M. Antoine
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| 8 | * Copyright (C) 1999 Silicon Graphics
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| 9 | * Kevin D. Kissell, [email protected] and Carsten Langgaard, [email protected]
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| 10 | * Copyright (C) 2000 MIPS Technologies, Inc.
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| 11 |
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| 12 | #ifndef _ASM_SWITCH_TO_H
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| 13 | #define _ASM_SWITCH_TO_H
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| 14 |
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| 15 | #include <asm/cpu-features.h>
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| 16 | #include <asm/watch.h>
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| 17 | #include <asm/dsp.h>
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| 18 | #include <asm/cop2.h>
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| 19 | #include <asm/fpu.h>
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| 20 |
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| 21 | struct task_struct;
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| 22 |
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| 23 | |
| 24 | * resume - resume execution of a task
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| 25 | * @prev: The task previously executed.
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| 26 | * @next: The task to begin executing.
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| 27 | * @next_ti: task_thread_info(next).
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| 28 | *
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| 29 | * This function is used whilst scheduling to save the context of prev & load
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| 30 | * the context of next. Returns prev.
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| 31 |
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| 32 | extern asmlinkage struct task_struct *resume(struct task_struct *prev,
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| 33 | struct task_struct *next, struct thread_info *next_ti);
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| 34 |
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| 35 | extern unsigned int ll_bit;
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| 36 | extern struct task_struct *ll_task;
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| 37 |
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| 38 | #ifdef CONFIG_MIPS_MT_FPAFF
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| 39 |
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| 40 | |
| 41 | * Handle the scheduler resume end of FPU affinity management. We do this
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| 42 | * inline to try to keep the overhead down. If we have been forced to run on
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| 43 | * a "CPU" with an FPU because of a previous high level of FP computation,
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| 44 | * but did not actually use the FPU during the most recent time-slice (CU1
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| 45 | * isn't set), we undo the restriction on cpus_mask.
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| 46 | *
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| 47 | * We're not calling set_cpus_allowed() here, because we have no need to
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| 48 | * force prompt migration - we're already switching the current CPU to a
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| 49 | * different thread.
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| 50 |
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| 51 |
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| 52 | #define __mips_mt_fpaff_switch_to(prev) \
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| 53 | do { \
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| 54 | struct thread_info *__prev_ti = task_thread_info(prev); \
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| 55 | \
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| 56 | if (cpu_has_fpu && \
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| 57 | test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
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| 58 | (!(KSTK_STATUS(prev) & ST0_CU1))) { \
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| 59 | clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
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| 60 | prev->cpus_mask = prev->thread.user_cpus_allowed; \
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| 61 | } \
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| 62 | next->thread.emulated_fp = 0; \
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| 63 | } while(0)
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| 64 |
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| 65 | #else
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| 66 | #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
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| 67 | #endif
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| 68 |
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| 69 | |
| 70 | * Clear LLBit during context switches on MIPSr5+ such that eretnc can be used
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| 71 | * unconditionally when returning to userland in entry.S.
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| 72 |
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| 73 | #define __clear_r5_hw_ll_bit() do { \
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| 74 | if (cpu_has_mips_r5 || cpu_has_mips_r6) \
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| 75 | write_c0_lladdr(0); \
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| 76 | } while (0)
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| 77 |
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| 78 | #define __clear_software_ll_bit() do { \
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| 79 | if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
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| 80 | ll_bit = 0; \
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| 81 | } while (0)
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| 82 |
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| 83 | |
| 84 | * Check FCSR for any unmasked exceptions pending set with `ptrace',
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| 85 | * clear them and send a signal.
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| 86 |
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| 87 | #ifdef CONFIG_MIPS_FP_SUPPORT
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| 88 | # define __sanitize_fcr31(next) \
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| 89 | do { \
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| 90 | unsigned long fcr31 = mask_fcr31_x(next->thread.fpu.fcr31); \
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| 91 | void __user *pc; \
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| 92 | \
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| 93 | if (unlikely(fcr31)) { \
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| 94 | pc = (void __user *)task_pt_regs(next)->cp0_epc; \
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| 95 | next->thread.fpu.fcr31 &= ~fcr31; \
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| 96 | force_fcr31_sig(fcr31, pc, next); \
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| 97 | } \
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| 98 | } while (0)
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| 99 | #else
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| 100 | # define __sanitize_fcr31(next) do { (void) (next); } while (0)
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| 101 | #endif
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| 102 |
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| 103 | |
| 104 | * For newly created kernel threads switch_to() will return to
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| 105 | * ret_from_kernel_thread, newly created user threads to ret_from_fork.
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| 106 | * That is, everything following resume() will be skipped for new threads.
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| 107 | * So everything that matters to new threads should be placed before resume().
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| 108 |
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| 109 | #define switch_to(prev, next, last) \
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| 110 | do { \
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| 111 | __mips_mt_fpaff_switch_to(prev); \
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| 112 | lose_fpu_inatomic(1, prev); \
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| 113 | if (tsk_used_math(next)) \
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| 114 | __sanitize_fcr31(next); \
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| 115 | if (cpu_has_dsp) { \
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| 116 | __save_dsp(prev); \
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| 117 | __restore_dsp(next); \
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| 118 | } \
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| 119 | if (cop2_present) { \
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| 120 | u32 status = read_c0_status(); \
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| 121 | \
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| 122 | set_c0_status(ST0_CU2); \
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| 123 | if ((KSTK_STATUS(prev) & ST0_CU2)) { \
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| 124 | if (cop2_lazy_restore) \
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| 125 | KSTK_STATUS(prev) &= ~ST0_CU2; \
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| 126 | cop2_save(prev); \
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| 127 | } \
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| 128 | if (KSTK_STATUS(next) & ST0_CU2 && \
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| 129 | !cop2_lazy_restore) { \
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| 130 | cop2_restore(next); \
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| 131 | } \
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| 132 | write_c0_status(status); \
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| 133 | } \
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| 134 | __clear_r5_hw_ll_bit(); \
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| 135 | __clear_software_ll_bit(); \
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| 136 | if (cpu_has_userlocal) \
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| 137 | write_c0_userlocal(task_thread_info(next)->tp_value); \
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| 138 | __restore_watch(next); \
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| 139 | (last) = resume(prev, next, task_thread_info(next)); \
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| 140 | } while (0)
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| 141 |
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| 142 | #endif
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