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| 3 | * Linux performance counter support for MIPS.
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| 4 | *
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| 5 | * Copyright (C) 2010 MIPS Technologies, Inc.
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| 6 | * Author: Deng-Cheng Zhu
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| 7 | *
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| 8 | * This code is based on the implementation for ARM, which is in turn
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| 9 | * based on the sparc64 perf event code and the x86 code. Performance
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| 10 | * counter access is based on the MIPS Oprofile code. And the callchain
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| 11 | * support references the code of MIPS stacktrace.c.
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| 12 |
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| 13 |
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| 14 | #include <linux/perf_event.h>
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| 15 | #include <linux/sched/task_stack.h>
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| 16 |
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| 17 | #include <asm/stacktrace.h>
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| 18 |
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| 19 |
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| 20 |
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| 21 | |
| 22 | * Leave userspace callchain empty for now. When we find a way to trace
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| 23 | * the user stack callchains, we will add it here.
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| 24 |
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| 25 |
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| 26 | static void save_raw_perf_callchain(struct perf_callchain_entry_ctx *entry,
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| 27 | unsigned long reg29)
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| 28 | {
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| 29 | unsigned long *sp = (unsigned long *)reg29;
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| 30 | unsigned long addr;
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| 31 |
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| 32 | while (!kstack_end(sp)) {
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| 33 | addr = *sp++;
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| 34 | if (__kernel_text_address(addr)) {
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| 35 | perf_callchain_store(entry, addr);
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| 36 | if (entry->nr >= entry->max_stack)
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| 37 | break;
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| 38 | }
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| 39 | }
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| 40 | }
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| 41 |
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| 42 | void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
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| 43 | struct pt_regs *regs)
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| 44 | {
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| 45 | unsigned long sp = regs->regs[29];
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| 46 | #ifdef CONFIG_KALLSYMS
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| 47 | unsigned long ra = regs->regs[31];
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| 48 | unsigned long pc = regs->cp0_epc;
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| 49 |
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| 50 | if (raw_show_trace || !__kernel_text_address(pc)) {
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| 51 | unsigned long stack_page =
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| 52 | (unsigned long)task_stack_page(current);
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| 53 | if (stack_page && sp >= stack_page &&
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| 54 | sp <= stack_page + THREAD_SIZE - 32)
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| 55 | save_raw_perf_callchain(entry, sp);
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| 56 | return;
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| 57 | }
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| 58 | do {
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| 59 | perf_callchain_store(entry, pc);
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| 60 | if (entry->nr >= entry->max_stack)
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| 61 | break;
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| 62 | pc = unwind_stack(current, &sp, pc, &ra);
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| 63 | } while (pc);
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| 64 | #else
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| 65 | save_raw_perf_callchain(entry, sp);
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| 66 | #endif
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| 67 | }
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