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| 2 | |
| 3 | * include/asm-parisc/cache.h
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| 4 |
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| 5 |
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| 6 | #ifndef __ARCH_PARISC_CACHE_H
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| 7 | #define __ARCH_PARISC_CACHE_H
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| 8 |
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| 9 | #include <asm/alternative.h>
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| 10 |
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| 11 | |
| 12 | * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
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| 13 | * have 32-byte cachelines. The L1 length appears to be 16 bytes but this
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| 14 | * is not clearly documented.
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| 15 |
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| 16 | #define L1_CACHE_BYTES 16
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| 17 | #define L1_CACHE_SHIFT 4
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| 18 |
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| 19 | #ifndef __ASSEMBLER__
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| 20 |
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| 21 | #define SMP_CACHE_BYTES L1_CACHE_BYTES
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| 22 |
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| 23 | #ifdef CONFIG_PA20
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| 24 | #define ARCH_DMA_MINALIGN 128
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| 25 | #else
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| 26 | #define ARCH_DMA_MINALIGN 32
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| 27 | #endif
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| 28 | #define ARCH_KMALLOC_MINALIGN 16
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| 29 |
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| 30 | #define arch_slab_minalign() ((unsigned)dcache_stride)
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| 31 | #define cache_line_size() dcache_stride
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| 32 | #define dma_get_cache_alignment cache_line_size
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| 33 |
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| 34 | #define __read_mostly __section(".data..read_mostly")
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| 35 |
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| 36 | void parisc_cache_init(void);
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| 37 | void disable_sr_hashing_asm(int);
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| 38 | void disable_sr_hashing(void);
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| 39 | void free_sid(unsigned long);
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| 40 | unsigned long alloc_sid(void);
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| 41 |
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| 42 | struct seq_file;
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| 43 | extern void show_cache_info(struct seq_file *m);
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| 44 |
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| 45 | extern int split_tlb;
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| 46 | extern int dcache_stride;
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| 47 | extern int icache_stride;
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| 48 | extern struct pdc_cache_info cache_info;
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| 49 | extern struct pdc_btlb_info btlb_info;
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| 50 | void parisc_setup_cache_timing(void);
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| 51 |
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| 52 | #define pdtlb(sr, addr) asm volatile("pdtlb 0(%%sr%0,%1)" \
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| 53 | ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
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| 54 | : : "i"(sr), "r" (addr) : "memory")
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| 55 | #define pitlb(sr, addr) asm volatile("pitlb 0(%%sr%0,%1)" \
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| 56 | ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
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| 57 | ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
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| 58 | : : "i"(sr), "r" (addr) : "memory")
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| 59 |
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| 60 | #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
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| 61 | ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
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| 62 | ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
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| 63 | : : "r" (addr) : "memory")
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| 64 | #define asm_io_sync() asm volatile("sync" \
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| 65 | ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
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| 66 | ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
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| 67 | #define asm_syncdma() asm volatile("syncdma" :::"memory")
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| 68 |
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| 69 | #endif
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| 70 |
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| 71 |
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| 72 |
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| 73 | #define SRHASH_PCXST 0
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| 74 | #define SRHASH_PCXL 1
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| 75 | #define SRHASH_PA20 2
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| 76 |
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| 77 | #endif
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