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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1997, 1998 Ralf Baechle
7 * Copyright (C) 1999 SuSE GmbH
8 * Copyright (C) 1999-2001 Hewlett-Packard Company
9 * Copyright (C) 1999-2001 Grant Grundler
10 */
11#include <linux/align.h>
12#include <linux/eisa.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/types.h>
18
19#include <asm/io.h>
20#include <asm/superio.h>
21
22#define DEBUG_RESOURCES 0
23#define DEBUG_CONFIG 0
24
25#if DEBUG_CONFIG
26# define DBGC(x...) printk(KERN_DEBUG x)
27#else
28# define DBGC(x...)
29#endif
30
31
32#if DEBUG_RESOURCES
33#define DBG_RES(x...) printk(KERN_DEBUG x)
34#else
35#define DBG_RES(x...)
36#endif
37
38struct pci_port_ops *pci_port __ro_after_init;
39struct pci_bios_ops *pci_bios __ro_after_init;
40
41static int pci_hba_count __ro_after_init;
42
43/* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */
44#define PCI_HBA_MAX 32
45static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __ro_after_init;
46
47
48/********************************************************************
49**
50** I/O port space support
51**
52*********************************************************************/
53
54/* EISA port numbers and PCI port numbers share the same interface. Some
55 * machines have both EISA and PCI adapters installed. Rather than turn
56 * pci_port into an array, we reserve bus 0 for EISA and call the EISA
57 * routines if the access is to a port on bus 0. We don't want to fix
58 * EISA and ISA drivers which assume port space is <= 0xffff.
59 */
60
61#ifdef CONFIG_EISA
62#define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
63#define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
64#else
65#define EISA_IN(size)
66#define EISA_OUT(size)
67#endif
68
69#define PCI_PORT_IN(type, size) \
70u##size in##type (int addr) \
71{ \
72 int b = PCI_PORT_HBA(addr); \
73 EISA_IN(size); \
74 if (!parisc_pci_hba[b]) return (u##size) -1; \
75 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
76} \
77EXPORT_SYMBOL(in##type);
78
79PCI_PORT_IN(b, 8)
80PCI_PORT_IN(w, 16)
81PCI_PORT_IN(l, 32)
82
83
84#define PCI_PORT_OUT(type, size) \
85void out##type (u##size d, int addr) \
86{ \
87 int b = PCI_PORT_HBA(addr); \
88 EISA_OUT(size); \
89 if (!parisc_pci_hba[b]) return; \
90 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
91} \
92EXPORT_SYMBOL(out##type);
93
94PCI_PORT_OUT(b, 8)
95PCI_PORT_OUT(w, 16)
96PCI_PORT_OUT(l, 32)
97
98
99
100/*
101 * BIOS32 replacement.
102 */
103static int __init pcibios_init(void)
104{
105 if (!pci_bios)
106 return -1;
107
108 if (pci_bios->init) {
109 pci_bios->init();
110 } else {
111 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
112 }
113
114 /* Set the CLS for PCI as early as possible. */
115 pci_cache_line_size = pci_dfl_cache_line_size;
116
117 return 0;
118}
119
120
121/* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
122void pcibios_fixup_bus(struct pci_bus *bus)
123{
124 if (pci_bios->fixup_bus) {
125 pci_bios->fixup_bus(bus);
126 } else {
127 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
128 }
129}
130
131
132/*
133 * Called by pci_set_master() - a driver interface.
134 *
135 * Legacy PDC guarantees to set:
136 * Map Memory BAR's into PA IO space.
137 * Map Expansion ROM BAR into one common PA IO space per bus.
138 * Map IO BAR's into PCI IO space.
139 * Command (see below)
140 * Cache Line Size
141 * Latency Timer
142 * Interrupt Line
143 * PPB: secondary latency timer, io/mmio base/limit,
144 * bus numbers, bridge control
145 *
146 */
147void pcibios_set_master(struct pci_dev *dev)
148{
149 u8 lat;
150
151 /* If someone already mucked with this, don't touch it. */
152 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
153 if (lat >= 16) return;
154
155 /*
156 ** HP generally has fewer devices on the bus than other architectures.
157 ** upper byte is PCI_LATENCY_TIMER.
158 */
159 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
160 (0x80 << 8) | pci_cache_line_size);
161}
162
163/*
164 * pcibios_init_bridge() initializes cache line and default latency
165 * for pci controllers and pci-pci bridges
166 */
167void __ref pcibios_init_bridge(struct pci_dev *dev)
168{
169 unsigned short bridge_ctl, bridge_ctl_new;
170
171 /* We deal only with pci controllers and pci-pci bridges. */
172 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
173 return;
174
175 /* PCI-PCI bridge - set the cache line and default latency
176 * (32) for primary and secondary buses.
177 */
178 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
179
180 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
181
182 bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY |
183 PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT;
184 dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n",
185 bridge_ctl, bridge_ctl_new);
186
187 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new);
188}
189
190/*
191 * pcibios align resources() is called every time generic PCI code
192 * wants to generate a new address. The process of looking for
193 * an available address, each candidate is first "aligned" and
194 * then checked if the resource is available until a match is found.
195 *
196 * Since we are just checking candidates, don't use any fields other
197 * than res->start.
198 */
199resource_size_t pcibios_align_resource(void *data, const struct resource *res,
200 const struct resource *empty_res,
201 resource_size_t size,
202 resource_size_t alignment)
203{
204 struct pci_dev *dev = data;
205 resource_size_t align, start = res->start;
206
207 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
208 pci_name(((struct pci_dev *) data)),
209 res->parent, res->start, res->end,
210 (int) res->flags, size, alignment);
211
212 /* If it's not IO, then it's gotta be MEM */
213 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
214 if (align > alignment)
215 start = ALIGN(start, align);
216 else
217 start = pci_align_resource(dev, res, empty_res, size, alignment);
218
219 return start;
220}
221
222/*
223 * A driver is enabling the device. We make sure that all the appropriate
224 * bits are set to allow the device to operate as the driver is expecting.
225 * We enable the port IO and memory IO bits if the device has any BARs of
226 * that type, and we enable the PERR and SERR bits unconditionally.
227 * Drivers that do not need parity (eg graphics and possibly networking)
228 * can clear these bits if they want.
229 */
230int pcibios_enable_device(struct pci_dev *dev, int mask)
231{
232 int err;
233 u16 cmd, old_cmd;
234
235 err = pci_enable_resources(dev, mask);
236 if (err < 0)
237 return err;
238
239 pci_read_config_word(dev, PCI_COMMAND, &cmd);
240 old_cmd = cmd;
241
242 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
243
244#if 0
245 /* If bridge/bus controller has FBB enabled, child must too. */
246 if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
247 cmd |= PCI_COMMAND_FAST_BACK;
248#endif
249
250 if (cmd != old_cmd) {
251 dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
252 old_cmd, cmd);
253 pci_write_config_word(dev, PCI_COMMAND, cmd);
254 }
255 return 0;
256}
257
258
259/* PA-RISC specific */
260void pcibios_register_hba(struct pci_hba_data *hba)
261{
262 if (pci_hba_count >= PCI_HBA_MAX) {
263 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
264 return;
265 }
266
267 parisc_pci_hba[pci_hba_count] = hba;
268 hba->hba_num = pci_hba_count++;
269}
270
271subsys_initcall(pcibios_init);