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1/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2/*
3 * ELF register definitions..
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10#ifndef _UAPI_ASM_POWERPC_ELF_H
11#define _UAPI_ASM_POWERPC_ELF_H
12
13
14#include <linux/types.h>
15
16#include <asm/ptrace.h>
17#include <asm/cputable.h>
18#include <asm/auxvec.h>
19
20/* PowerPC relocations defined by the ABIs */
21#define R_PPC_NONE 0
22#define R_PPC_ADDR32 1 /* 32bit absolute address */
23#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
24#define R_PPC_ADDR16 3 /* 16bit absolute address */
25#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
26#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
27#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
28#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
29#define R_PPC_ADDR14_BRTAKEN 8
30#define R_PPC_ADDR14_BRNTAKEN 9
31#define R_PPC_REL24 10 /* PC relative 26 bit */
32#define R_PPC_REL14 11 /* PC relative 16 bit */
33#define R_PPC_REL14_BRTAKEN 12
34#define R_PPC_REL14_BRNTAKEN 13
35#define R_PPC_GOT16 14
36#define R_PPC_GOT16_LO 15
37#define R_PPC_GOT16_HI 16
38#define R_PPC_GOT16_HA 17
39#define R_PPC_PLTREL24 18
40#define R_PPC_COPY 19
41#define R_PPC_GLOB_DAT 20
42#define R_PPC_JMP_SLOT 21
43#define R_PPC_RELATIVE 22
44#define R_PPC_LOCAL24PC 23
45#define R_PPC_UADDR32 24
46#define R_PPC_UADDR16 25
47#define R_PPC_REL32 26
48#define R_PPC_PLT32 27
49#define R_PPC_PLTREL32 28
50#define R_PPC_PLT16_LO 29
51#define R_PPC_PLT16_HI 30
52#define R_PPC_PLT16_HA 31
53#define R_PPC_SDAREL16 32
54#define R_PPC_SECTOFF 33
55#define R_PPC_SECTOFF_LO 34
56#define R_PPC_SECTOFF_HI 35
57#define R_PPC_SECTOFF_HA 36
58
59/* PowerPC relocations defined for the TLS access ABI. */
60#define R_PPC_TLS 67 /* none (sym+add)@tls */
61#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
62#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
63#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
64#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
65#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
66#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
67#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
68#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
69#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
70#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
71#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
72#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
73#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
74#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
75#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
76#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
77#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
78#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
79#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
80#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
81#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
82#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
83#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
84#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
85#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
86#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
87#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
88
89/* keep this the last entry. */
90#define R_PPC_NUM 95
91
92
93#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
94#define ELF_NFPREG 33 /* includes fpscr */
95#define ELF_NVMX 34 /* includes all vector registers */
96#define ELF_NVSX 32 /* includes all VSX registers */
97#define ELF_NTMSPRREG 3 /* include tfhar, tfiar, texasr */
98#define ELF_NEBB 3 /* includes ebbrr, ebbhr, bescr */
99#define ELF_NPMU 5 /* includes siar, sdar, sier, mmcr2, mmcr0 */
100#define ELF_NPKEY 3 /* includes amr, iamr, uamor */
101#define ELF_NDEXCR 2 /* includes dexcr, hdexcr */
102#define ELF_NHASHKEYR 1 /* includes hashkeyr */
103
104typedef unsigned long elf_greg_t64;
105typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
106
107typedef unsigned int elf_greg_t32;
108typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
109typedef elf_gregset_t32 compat_elf_gregset_t;
110
111/*
112 * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
113 */
114#ifdef __powerpc64__
115# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
116# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
117# define ELF_NVSRHALFREG 32 /* Half the vsx registers */
118# define ELF_GREG_TYPE elf_greg_t64
119# define ELF_ARCH EM_PPC64
120# define ELF_CLASS ELFCLASS64
121typedef elf_greg_t64 elf_greg_t;
122typedef elf_gregset_t64 elf_gregset_t;
123#else
124# define ELF_NEVRREG 34 /* includes acc (as 2) */
125# define ELF_NVRREG 33 /* includes vscr */
126# define ELF_GREG_TYPE elf_greg_t32
127# define ELF_ARCH EM_PPC
128# define ELF_CLASS ELFCLASS32
129typedef elf_greg_t32 elf_greg_t;
130typedef elf_gregset_t32 elf_gregset_t;
131#endif /* __powerpc64__ */
132
133#ifdef __BIG_ENDIAN__
134#define ELF_DATA ELFDATA2MSB
135#else
136#define ELF_DATA ELFDATA2LSB
137#endif
138
139/* Floating point registers */
140typedef double elf_fpreg_t;
141typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
142
143/* Altivec registers */
144/*
145 * The entries with indexes 0-31 contain the corresponding vector registers.
146 * The entry with index 32 contains the vscr as the last word (offset 12)
147 * within the quadword. This allows the vscr to be stored as either a
148 * quadword (since it must be copied via a vector register to/from storage)
149 * or as a word.
150 *
151 * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
152 * word (offset 0) within the quadword.
153 *
154 * This definition of the VMX state is compatible with the current PPC32
155 * ptrace interface. This allows signal handling and ptrace to use the same
156 * structures. This also simplifies the implementation of a bi-arch
157 * (combined (32- and 64-bit) gdb.
158 *
159 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
160 * vrsave along with vscr and so only uses 33 vectors for the register set
161 */
162typedef __vector128 elf_vrreg_t;
163typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
164#ifdef __powerpc64__
165typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
166typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
167#endif
168
169/* PowerPC64 relocations defined by the ABIs */
170#define R_PPC64_NONE R_PPC_NONE
171#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
172#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
173#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
174#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
175#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
176#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
177#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
178#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
179#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
180#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
181#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
182#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
183#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
184#define R_PPC64_GOT16 R_PPC_GOT16
185#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
186#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
187#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
188
189#define R_PPC64_COPY R_PPC_COPY
190#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
191#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
192#define R_PPC64_RELATIVE R_PPC_RELATIVE
193
194#define R_PPC64_UADDR32 R_PPC_UADDR32
195#define R_PPC64_UADDR16 R_PPC_UADDR16
196#define R_PPC64_REL32 R_PPC_REL32
197#define R_PPC64_PLT32 R_PPC_PLT32
198#define R_PPC64_PLTREL32 R_PPC_PLTREL32
199#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
200#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
201#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
202
203#define R_PPC64_SECTOFF R_PPC_SECTOFF
204#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
205#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
206#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
207#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
208#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
209#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
210#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
211#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
212#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
213#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
214#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
215#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
216#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
217#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
218#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
219#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
220#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
221#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
222#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
223#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
224#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
225#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
226
227#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
228#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
229#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
230#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
231#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
232#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
233#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
234#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
235#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
236#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
237#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
238
239/* PowerPC64 relocations defined for the TLS access ABI. */
240#define R_PPC64_TLS 67 /* none (sym+add)@tls */
241#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
242#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
243#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
244#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
245#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
246#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
247#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
248#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
249#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
250#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
251#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
252#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
253#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
254#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
255#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
256#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
257#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
258#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
259#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
260#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
261#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
262#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
263#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
264#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
265#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
266#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
267#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
268#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
269#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
270#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
271#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
272#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
273#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
274#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
275#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
276#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
277#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
278#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
279#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
280#define R_PPC64_TLSGD 107
281#define R_PPC64_TLSLD 108
282#define R_PPC64_TOCSAVE 109
283
284#define R_PPC64_REL24_NOTOC 116
285#define R_PPC64_ENTRY 118
286
287#define R_PPC64_PCREL34 132
288#define R_PPC64_GOT_PCREL34 133
289
290#define R_PPC64_REL16 249
291#define R_PPC64_REL16_LO 250
292#define R_PPC64_REL16_HI 251
293#define R_PPC64_REL16_HA 252
294
295/* Keep this the last entry. */
296#define R_PPC64_NUM 253
297
298#endif /* _UAPI_ASM_POWERPC_ELF_H */