| 1 |
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| 2 | #ifndef _ASM_POWERPC_SIGCONTEXT_H
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| 3 | #define _ASM_POWERPC_SIGCONTEXT_H
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| 4 |
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| 5 | |
| 6 | * This program is free software; you can redistribute it and/or
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| 7 | * modify it under the terms of the GNU General Public License
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| 8 | * as published by the Free Software Foundation; either version
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| 9 | * 2 of the License, or (at your option) any later version.
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| 10 |
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| 11 | #include <linux/compiler.h>
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| 12 | #include <asm/ptrace.h>
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| 13 | #ifdef __powerpc64__
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| 14 | #include <asm/elf.h>
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| 15 | #endif
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| 16 |
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| 17 | struct sigcontext {
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| 18 | unsigned long _unused[4];
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| 19 | int signal;
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| 20 | #ifdef __powerpc64__
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| 21 | int _pad0;
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| 22 | #endif
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| 23 | unsigned long handler;
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| 24 | unsigned long oldmask;
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| 25 | #ifdef __KERNEL__
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| 26 | struct user_pt_regs __user *regs;
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| 27 | #else
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| 28 | struct pt_regs *regs;
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| 29 | #endif
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| 30 | #ifdef __powerpc64__
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| 31 | elf_gregset_t gp_regs;
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| 32 | elf_fpregset_t fp_regs;
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| 33 | |
| 34 | * To maintain compatibility with current implementations the sigcontext is
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| 35 | * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
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| 36 | * followed by an unstructured (vmx_reserve) field of 101 doublewords. This
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| 37 | * allows the array of vector registers to be quadword aligned independent of
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| 38 | * the alignment of the containing sigcontext or ucontext. It is the
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| 39 | * responsibility of the code setting the sigcontext to set this pointer to
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| 40 | * either NULL (if this processor does not support the VMX feature) or the
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| 41 | * address of the first quadword within the allocated (vmx_reserve) area.
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| 42 | *
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| 43 | * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
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| 44 | * an array of 34 quadword entries (elf_vrregset_t). The entries with
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| 45 | * indexes 0-31 contain the corresponding vector registers. The entry with
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| 46 | * index 32 contains the vscr as the last word (offset 12) within the
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| 47 | * quadword. This allows the vscr to be stored as either a quadword (since
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| 48 | * it must be copied via a vector register to/from storage) or as a word.
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| 49 | * The entry with index 33 contains the vrsave as the first word (offset 0)
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| 50 | * within the quadword.
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| 51 | *
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| 52 | * Part of the VSX data is stored here also by extending vmx_restore
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| 53 | * by an additional 32 double words. Architecturally the layout of
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| 54 | * the VSR registers and how they overlap on top of the legacy FPR and
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| 55 | * VR registers is shown below:
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| 56 | *
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| 57 | * VSR doubleword 0 VSR doubleword 1
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| 58 | * ----------------------------------------------------------------
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| 59 | * VSR[0] | FPR[0] | |
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| 60 | * ----------------------------------------------------------------
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| 61 | * VSR[1] | FPR[1] | |
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| 62 | * ----------------------------------------------------------------
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| 63 | * | ... | |
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| 64 | * | ... | |
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| 65 | * ----------------------------------------------------------------
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| 66 | * VSR[30] | FPR[30] | |
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| 67 | * ----------------------------------------------------------------
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| 68 | * VSR[31] | FPR[31] | |
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| 69 | * ----------------------------------------------------------------
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| 70 | * VSR[32] | VR[0] |
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| 71 | * ----------------------------------------------------------------
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| 72 | * VSR[33] | VR[1] |
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| 73 | * ----------------------------------------------------------------
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| 74 | * | ... |
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| 75 | * | ... |
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| 76 | * ----------------------------------------------------------------
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| 77 | * VSR[62] | VR[30] |
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| 78 | * ----------------------------------------------------------------
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| 79 | * VSR[63] | VR[31] |
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| 80 | * ----------------------------------------------------------------
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| 81 | *
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| 82 | * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
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| 83 | * is stored at the start of vmx_reserve. vmx_reserve is extended for
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| 84 | * backwards compatility to store VSR 0-31 doubleword 1 after the VMX
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| 85 | * registers and vscr/vrsave.
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| 86 |
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| 87 | elf_vrreg_t __user *v_regs;
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| 88 | long vmx_reserve[ELF_NVRREG + ELF_NVRREG + 1 + 32];
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| 89 | #endif
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| 90 | };
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| 91 |
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| 92 | #endif
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