| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */
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| 2 | /*
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| 3 | * This file contains low level CPU setup functions.
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| 4 | * Kumar Gala <galak@kernel.crashing.org>
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| 5 | * Copyright 2009 Freescale Semiconductor, Inc.
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| 6 | *
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| 7 | * Based on cpu_setup_6xx code by
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| 8 | * Benjamin Herrenschmidt <benh@kernel.crashing.org>
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| 9 | */
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| 10 |
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| 11 | |
| 12 |
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| 13 | |
| 14 | |
| 15 | |
| 16 | |
| 17 | |
| 18 | |
| 19 | |
| 20 |
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| 21 | _GLOBAL(__e500_icache_setup)
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| 22 | mfspr r0, SPRN_L1CSR1
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| 23 | andi. r3, r0, L1CSR1_ICE
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| 24 | bnelr /* Already enabled */
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| 25 | oris r0, r0, L1CSR1_CPE@h
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| 26 | ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
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| 27 | mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
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| 28 | isync
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| 29 | blr
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| 30 |
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| 31 | _GLOBAL(__e500_dcache_setup)
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| 32 | mfspr r0, SPRN_L1CSR0
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| 33 | andi. r3, r0, L1CSR0_DCE
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| 34 | bnelr /* Already enabled */
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| 35 | msync
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| 36 | isync
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| 37 | li r0, 0
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| 38 | mtspr SPRN_L1CSR0, r0 /* Disable */
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| 39 | msync
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| 40 | isync
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| 41 | li r0, (L1CSR0_DCFI | L1CSR0_CLFC)
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| 42 | mtspr SPRN_L1CSR0, r0 /* Invalidate */
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| 43 | isync
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| 44 | 1: mfspr r0, SPRN_L1CSR0
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| 45 | andi. r3, r0, L1CSR0_CLFC
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| 46 | bne+ 1b /* Wait for lock bits reset */
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| 47 | oris r0, r0, L1CSR0_CPE@h
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| 48 | ori r0, r0, L1CSR0_DCE
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| 49 | msync
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| 50 | isync
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| 51 | mtspr SPRN_L1CSR0, r0 /* Enable */
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| 52 | isync
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| 53 | blr
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| 54 |
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| 55 | /*
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| 56 | * FIXME - we haven't yet done testing to determine a reasonable default
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| 57 | * value for PW20_WAIT_IDLE_BIT.
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| 58 | */
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| 59 | #define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
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| 60 | _GLOBAL(setup_pw20_idle)
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| 61 | mfspr r3, SPRN_PWRMGTCR0
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| 62 |
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| 63 | /* Set PW20_WAIT bit, enable pw20 state*/
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| 64 | ori r3, r3, PWRMGTCR0_PW20_WAIT
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| 65 | li r11, PW20_WAIT_IDLE_BIT
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| 66 |
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| 67 | /* Set Automatic PW20 Core Idle Count */
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| 68 | rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
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| 69 |
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| 70 | mtspr SPRN_PWRMGTCR0, r3
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| 71 |
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| 72 | blr
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| 73 |
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| 74 | /*
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| 75 | * FIXME - we haven't yet done testing to determine a reasonable default
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| 76 | * value for AV_WAIT_IDLE_BIT.
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| 77 | */
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| 78 | |
| 79 | _GLOBAL(setup_altivec_idle)
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| 80 | mfspr r3, SPRN_PWRMGTCR0
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| 81 |
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| 82 | /* Enable Altivec Idle */
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| 83 | oris r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
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| 84 | li r11, AV_WAIT_IDLE_BIT
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| 85 |
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| 86 | /* Set Automatic AltiVec Idle Count */
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| 87 | rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
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| 88 |
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| 89 | mtspr SPRN_PWRMGTCR0, r3
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| 90 |
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| 91 | blr
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| 92 |
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| 93 | |
| 94 | _GLOBAL(__setup_cpu_e6500)
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| 95 | mflr r6
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| 96 | |
| 97 | bl setup_altivec_ivors
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| 98 | /* Touch IVOR42 only if the CPU supports E.HV category */
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| 99 | mfspr r10,SPRN_MMUCFG
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| 100 | rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
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| 101 | beq 1f
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| 102 | bl setup_lrat_ivor
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| 103 | 1:
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| 104 | |
| 105 | bl setup_pw20_idle
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| 106 | bl setup_altivec_idle
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| 107 | bl __setup_cpu_e5500
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| 108 | mtlr r6
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| 109 | blr
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| 110 | |
| 111 |
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| 112 | |
| 113 | |
| 114 | |
| 115 | _GLOBAL(__setup_cpu_e500v1)
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| 116 | _GLOBAL(__setup_cpu_e500v2)
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| 117 | mflr r4
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| 118 | bl __e500_icache_setup
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| 119 | bl __e500_dcache_setup
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| 120 | bl __setup_e500_ivors
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| 121 | |
| 122 | /* Ensure that RFXE is set */
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| 123 | mfspr r3,SPRN_HID1
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| 124 | oris r3,r3,HID1_RFXE@h
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| 125 | mtspr SPRN_HID1,r3
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| 126 | |
| 127 | mtlr r4
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| 128 | blr
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| 129 | |
| 130 | _GLOBAL(__setup_cpu_e500mc)
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| 131 | _GLOBAL(__setup_cpu_e5500)
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| 132 | mflr r5
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| 133 | bl __e500_icache_setup
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| 134 | bl __e500_dcache_setup
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| 135 | bl __setup_e500mc_ivors
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| 136 | /*
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| 137 | * We only want to touch IVOR38-41 if we're running on hardware
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| 138 | * that supports category E.HV. The architectural way to determine
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| 139 | * this is MMUCFG[LPIDSIZE].
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| 140 | */
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| 141 | mfspr r3, SPRN_MMUCFG
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| 142 | rlwinm. r3, r3, 0, MMUCFG_LPIDSIZE
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| 143 | beq 1f
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| 144 | bl __setup_ehv_ivors
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| 145 | b 2f
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| 146 | 1:
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| 147 | lwz r3, CPU_SPEC_FEATURES(r4)
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| 148 | /* We need this check as cpu_setup is also called for
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| 149 | * the secondary cores. So, if we have already cleared
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| 150 | * the feature on the primary core, avoid doing it on the
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| 151 | * secondary core.
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| 152 | */
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| 153 | andi. r6, r3, CPU_FTR_EMB_HV
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| 154 | beq 2f
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| 155 | rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV
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| 156 | stw r3, CPU_SPEC_FEATURES(r4)
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| 157 | 2:
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| 158 | mtlr r5
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| 159 | blr
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| 160 | #endif /* CONFIG_PPC_E500MC */
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| 161 | #endif /* CONFIG_PPC_E500 */
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| 162 | #endif /* CONFIG_PPC32 */
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| 163 |
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| 164 | #ifdef CONFIG_PPC_BOOK3E_64
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| 165 | _GLOBAL(__restore_cpu_e6500)
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| 166 | mflr r5
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| 167 | bl setup_altivec_ivors
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| 168 | /* Touch IVOR42 only if the CPU supports E.HV category */
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| 169 | mfspr r10,SPRN_MMUCFG
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| 170 | rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
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| 171 | beq 1f
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| 172 | bl setup_lrat_ivor
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| 173 | 1:
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| 174 | bl setup_pw20_idle
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| 175 | bl setup_altivec_idle
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| 176 | bl __restore_cpu_e5500
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| 177 | mtlr r5
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| 178 | blr
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| 179 |
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| 180 | _GLOBAL(__restore_cpu_e5500)
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| 181 | mflr r4
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| 182 | bl __e500_icache_setup
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| 183 | bl __e500_dcache_setup
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| 184 | bl __setup_base_ivors
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| 185 | bl setup_perfmon_ivor
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| 186 | bl setup_doorbell_ivors
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| 187 | /*
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| 188 | * We only want to touch IVOR38-41 if we're running on hardware
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| 189 | * that supports category E.HV. The architectural way to determine
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| 190 | * this is MMUCFG[LPIDSIZE].
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| 191 | */
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| 192 | mfspr r10,SPRN_MMUCFG
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| 193 | rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
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| 194 | beq 1f
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| 195 | bl setup_ehv_ivors
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| 196 | 1:
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| 197 | mtlr r4
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| 198 | blr
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| 199 |
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| 200 | _GLOBAL(__setup_cpu_e5500)
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| 201 | mflr r5
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| 202 | bl __e500_icache_setup
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| 203 | bl __e500_dcache_setup
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| 204 | bl __setup_base_ivors
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| 205 | bl setup_perfmon_ivor
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| 206 | bl setup_doorbell_ivors
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| 207 | /*
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| 208 | * We only want to touch IVOR38-41 if we're running on hardware
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| 209 | * that supports category E.HV. The architectural way to determine
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| 210 | * this is MMUCFG[LPIDSIZE].
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| 211 | */
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| 212 | mfspr r10,SPRN_MMUCFG
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| 213 | rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
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| 214 | beq 1f
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| 215 | bl setup_ehv_ivors
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| 216 | b 2f
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| 217 | 1:
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| 218 | ld r10,CPU_SPEC_FEATURES(r4)
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| 219 | LOAD_REG_IMMEDIATE(r9,CPU_FTR_EMB_HV)
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| 220 | andc r10,r10,r9
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| 221 | std r10,CPU_SPEC_FEATURES(r4)
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| 222 | 2:
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| 223 | mtlr r5
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| 224 | blr
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| 225 | #endif
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| 226 |
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| 227 | /* flush L1 data cache, it can apply to e500v2, e500mc and e5500 */
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| 228 | _GLOBAL(flush_dcache_L1)
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| 229 | mfmsr r10
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| 230 | wrteei 0
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| 231 |
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| 232 | mfspr r3,SPRN_L1CFG0
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| 233 | rlwinm r5,r3,9,3 /* Extract cache block size */
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| 234 | twlgti r5,1 /* Only 32 and 64 byte cache blocks
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| 235 | * are currently defined.
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| 236 | */
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| 237 | li r4,32
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| 238 | subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
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| 239 | * log2(number of ways)
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| 240 | */
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| 241 | slw r5,r4,r5 /* r5 = cache block size */
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| 242 |
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| 243 | rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
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| 244 | mulli r7,r7,13 /* An 8-way cache will require 13
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| 245 | * loads per set.
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| 246 | */
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| 247 | slw r7,r7,r6
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| 248 |
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| 249 | /* save off HID0 and set DCFA */
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| 250 | mfspr r8,SPRN_HID0
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| 251 | ori r9,r8,HID0_DCFA@l
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| 252 | mtspr SPRN_HID0,r9
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| 253 | isync
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| 254 |
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| 255 | LOAD_REG_IMMEDIATE(r6, KERNELBASE)
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| 256 | mr r4, r6
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| 257 | mtctr r7
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| 258 |
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| 259 | 1: lwz r3,0(r4) /* Load... */
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| 260 | add r4,r4,r5
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| 261 | bdnz 1b
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| 262 |
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| 263 | msync
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| 264 | mr r4, r6
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| 265 | mtctr r7
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| 266 |
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| 267 | 1: dcbf 0,r4 /* ...and flush. */
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| 268 | add r4,r4,r5
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| 269 | bdnz 1b
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| 270 |
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| 271 | /* restore HID0 */
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| 272 | mtspr SPRN_HID0,r8
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| 273 | isync
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| 274 |
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| 275 | wrtee r10
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| 276 |
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| 277 | blr
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| 278 |
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| 279 | SYM_FUNC_START_LOCAL(has_L2_cache)
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| 280 | /* skip L2 cache on P2040/P2040E as they have no L2 cache */
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| 281 | mfspr r3, SPRN_SVR
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| 282 | /* shift right by 8 bits and clear E bit of SVR */
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| 283 | rlwinm r4, r3, 24, ~0x800
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| 284 |
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| 285 | lis r3, SVR_P2040@h
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| 286 | ori r3, r3, SVR_P2040@l
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| 287 | cmpw r4, r3
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| 288 | beq 1f
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| 289 |
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| 290 | li r3, 1
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| 291 | blr
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| 292 | 1:
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| 293 | li r3, 0
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| 294 | blr
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| 295 | SYM_FUNC_END(has_L2_cache)
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| 296 |
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| 297 | /* flush backside L2 cache */
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| 298 | SYM_FUNC_START_LOCAL(flush_backside_L2_cache)
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| 299 | mflr r10
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| 300 | bl has_L2_cache
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| 301 | mtlr r10
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| 302 | cmpwi r3, 0
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| 303 | beq 2f
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| 304 |
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| 305 | /* Flush the L2 cache */
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| 306 | mfspr r3, SPRN_L2CSR0
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| 307 | ori r3, r3, L2CSR0_L2FL@l
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| 308 | msync
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| 309 | isync
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| 310 | mtspr SPRN_L2CSR0,r3
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| 311 | isync
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| 312 |
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| 313 | /* check if it is complete */
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| 314 | 1: mfspr r3,SPRN_L2CSR0
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| 315 | andi. r3, r3, L2CSR0_L2FL@l
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| 316 | bne 1b
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| 317 | 2:
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| 318 | blr
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| 319 | SYM_FUNC_END(flush_backside_L2_cache)
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| 320 |
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| 321 | _GLOBAL(cpu_down_flush_e500v2)
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| 322 | mflr r0
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| 323 | bl flush_dcache_L1
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| 324 | mtlr r0
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| 325 | blr
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| 326 |
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| 327 | _GLOBAL(cpu_down_flush_e500mc)
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| 328 | _GLOBAL(cpu_down_flush_e5500)
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| 329 | mflr r0
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| 330 | bl flush_dcache_L1
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| 331 | bl flush_backside_L2_cache
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| 332 | mtlr r0
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| 333 | blr
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| 334 |
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| 335 | /* L1 Data Cache of e6500 contains no modified data, no flush is required */
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| 336 | _GLOBAL(cpu_down_flush_e6500)
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| 337 | blr
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