| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */
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| 2 | /*
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| 3 | * PowerPC version
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| 4 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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| 5 | *
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| 6 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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| 7 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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| 8 | * Adapted for Power Macintosh by Paul Mackerras.
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| 9 | * Low-level exception handlers and MMU support
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| 10 | * rewritten by Paul Mackerras.
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| 11 | * Copyright (C) 1996 Paul Mackerras.
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| 12 | *
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| 13 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
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| 14 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
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| 15 | *
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| 16 | * This file contains the entry point for the 64-bit kernel along
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| 17 | * with some early initialization code common to all 64-bit powerpc
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| 18 | * variants.
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| 19 | */
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| 20 |
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| 21 | |
| 22 | |
| 23 | |
| 24 | |
| 25 | |
| 26 | |
| 27 | |
| 28 | |
| 29 | |
| 30 | |
| 31 | |
| 32 | |
| 33 | |
| 34 | |
| 35 | |
| 36 | |
| 37 | |
| 38 | |
| 39 | |
| 40 | |
| 41 | |
| 42 | |
| 43 | |
| 44 | |
| 45 | |
| 46 | |
| 47 | |
| 48 | |
| 49 |
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| 50 | /* The physical memory is laid out such that the secondary processor
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| 51 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow
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| 52 | * using the layout described in exceptions-64s.S
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| 53 | */
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| 54 |
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| 55 | /*
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| 56 | * Entering into this code we make the following assumptions:
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| 57 | *
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| 58 | * For pSeries or server processors:
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| 59 | * 1. The MMU is off & open firmware is running in real mode.
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| 60 | * 2. The primary CPU enters at __start.
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| 61 | * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
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| 62 | * CPUs will enter as directed by "start-cpu" RTAS call, which is
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| 63 | * generic_secondary_smp_init, with PIR in r3.
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| 64 | * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
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| 65 | * directed by the "start-cpu" RTS call, with PIR in r3.
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| 66 | * -or- For OPAL entry:
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| 67 | * 1. The MMU is off, processor in HV mode.
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| 68 | * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
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| 69 | * in r8, and entry in r9 for debugging purposes.
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| 70 | * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
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| 71 | * is at generic_secondary_smp_init, with PIR in r3.
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| 72 | *
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| 73 | * For Book3E processors:
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| 74 | * 1. The MMU is on running in AS0 in a state defined in ePAPR
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| 75 | * 2. The kernel is entered at __start
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| 76 | */
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| 77 |
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| 78 | /*
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| 79 | * boot_from_prom and prom_init run at the physical address. Everything
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| 80 | * after prom and kexec entry run at the virtual address (PAGE_OFFSET).
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| 81 | * Secondaries run at the virtual address from generic_secondary_common_init
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| 82 | * onward.
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| 83 | */
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| 84 |
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| 85 | OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
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| 86 | USE_FIXED_SECTION(first_256B)
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| 87 | /*
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| 88 | * Offsets are relative from the start of fixed section, and
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| 89 | * first_256B starts at 0. Offsets are a bit easier to use here
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| 90 | * than the fixed section entry macros.
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| 91 | */
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| 92 | . = 0x0
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| 93 | _GLOBAL(__start)
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| 94 | /* NOP this out unconditionally */
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| 95 | BEGIN_FTR_SECTION
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| 96 | FIXUP_ENDIAN
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| 97 | b __start_initialization_multiplatform
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| 98 | END_FTR_SECTION(0, 1)
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| 99 |
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| 100 | /* Catch branch to 0 in real mode */
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| 101 | trap
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| 102 |
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| 103 | /* Secondary processors spin on this value until it becomes non-zero.
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| 104 | * When non-zero, it contains the real address of the function the cpu
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| 105 | * should jump to.
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| 106 | */
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| 107 | .balign 8
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| 108 | .globl __secondary_hold_spinloop
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| 109 | __secondary_hold_spinloop:
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| 110 | .8byte 0x0
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| 111 |
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| 112 | /* Secondary processors write this value with their cpu |
| 113 | /* after they enter the spin loop immediately below. */
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| 114 | .globl __secondary_hold_acknowledge
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| 115 | __secondary_hold_acknowledge:
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| 116 | .8byte 0x0
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| 117 |
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| 118 | |
| 119 | /* This flag is set to 1 by a loader if the kernel should run
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| 120 | * at the loaded address instead of the linked address. This
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| 121 | * is used by kexec-tools to keep the kdump kernel in the
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| 122 | * crash_kernel region. The loader is responsible for
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| 123 | * observing the alignment requirement.
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| 124 | */
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| 125 |
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| 126 | |
| 127 | |
| 128 | |
| 129 | |
| 130 | |
| 131 |
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| 132 | /* Do not move this variable as kexec-tools knows about it. */
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| 133 | . = 0x5c
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| 134 | .globl __run_at_load
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| 135 | __run_at_load:
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| 136 | DEFINE_FIXED_SYMBOL(__run_at_load, first_256B)
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| 137 | .long RUN_AT_LOAD_DEFAULT
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| 138 | |
| 139 |
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| 140 | . = 0x60
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| 141 | /*
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| 142 | * The following code is used to hold secondary processors
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| 143 | * in a spin loop after they have entered the kernel, but
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| 144 | * before the bulk of the kernel has been relocated. This code
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| 145 | * is relocated to physical address 0x60 before prom_init is run.
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| 146 | * All of it must fit below the first exception vector at 0x100.
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| 147 | * Use .globl here not _GLOBAL because we want __secondary_hold
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| 148 | * to be the actual text address, not a descriptor.
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| 149 | */
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| 150 | .globl __secondary_hold
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| 151 | __secondary_hold:
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| 152 | FIXUP_ENDIAN
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| 153 | |
| 154 | mfmsr r24
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| 155 | ori r24,r24,MSR_RI
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| 156 | mtmsrd r24 /* RI on */
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| 157 | |
| 158 | /* Grab our physical cpu number */
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| 159 | mr r24,r3
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| 160 | /* stash r4 for book3e */
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| 161 | mr r25,r4
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| 162 |
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| 163 | /* Tell the master cpu we're here */
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| 164 | /* Relocation is off & we are located at an address less */
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| 165 | /* than 0x100, so only need to grab low order offset. */
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| 166 | std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0)
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| 167 | sync
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| 168 |
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| 169 | /* All secondary cpus wait here until told to start. */
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| 170 | 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(0)
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| 171 | cmpdi 0,r12,0
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| 172 | beq 100b
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| 173 |
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| 174 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
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| 175 | #ifdef CONFIG_PPC_BOOK3E_64
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| 176 | tovirt(r12,r12)
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| 177 | #endif
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| 178 | mtctr r12
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| 179 | mr r3,r24
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| 180 | /*
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| 181 | * it may be the case that other platforms have r4 right to
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| 182 | * begin with, this gives us some safety in case it is not
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| 183 | */
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| 184 | #ifdef CONFIG_PPC_BOOK3E_64
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| 185 | mr r4,r25
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| 186 | #else
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| 187 | li r4,0
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| 188 | #endif
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| 189 | /* Make sure that patched code is visible */
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| 190 | isync
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| 191 | bctr
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| 192 | #else
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| 193 | 0: trap
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| 194 | EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
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| 195 | #endif
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| 196 | CLOSE_FIXED_SECTION(first_256B)
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| 197 |
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| 198 | /*
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| 199 | * On server, we include the exception vectors code here as it
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| 200 | * relies on absolute addressing which is only possible within
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| 201 | * this compilation unit
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| 202 | */
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| 203 | #ifdef CONFIG_PPC_BOOK3S
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| 204 | #include "exceptions-64s.S"
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| 205 | #else
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| 206 | OPEN_TEXT_SECTION(0x100)
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| 207 | #endif
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| 208 |
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| 209 | USE_TEXT_SECTION()
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| 210 |
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| 211 | #include "interrupt_64.S"
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| 212 |
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| 213 | #ifdef CONFIG_PPC_BOOK3E_64
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| 214 | /*
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| 215 | * The booting_thread_hwid holds the thread id we want to boot in cpu
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| 216 | * hotplug case. It is set by cpu hotplug code, and is invalid by default.
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| 217 | * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
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| 218 | * bit field.
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| 219 | */
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| 220 | .globl booting_thread_hwid
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| 221 | booting_thread_hwid:
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| 222 | .long INVALID_THREAD_HWID
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| 223 | .align 3
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| 224 | /*
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| 225 | * start a thread in the same core
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| 226 | * input parameters:
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| 227 | * r3 = the thread physical id
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| 228 | * r4 = the entry point where thread starts
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| 229 | */
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| 230 | _GLOBAL(book3e_start_thread)
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| 231 | LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
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| 232 | cmpwi r3, 0
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| 233 | beq 10f
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| 234 | cmpwi r3, 1
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| 235 | beq 11f
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| 236 | /* If the thread id is invalid, just exit. */
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| 237 | b 13f
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| 238 | 10:
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| 239 | MTTMR(TMRN_IMSR0, 5)
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| 240 | MTTMR(TMRN_INIA0, 4)
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| 241 | b 12f
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| 242 | 11:
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| 243 | MTTMR(TMRN_IMSR1, 5)
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| 244 | MTTMR(TMRN_INIA1, 4)
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| 245 | 12:
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| 246 | isync
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| 247 | li r6, 1
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| 248 | sld r6, r6, r3
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| 249 | mtspr SPRN_TENS, r6
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| 250 | 13:
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| 251 | blr
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| 252 |
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| 253 | /*
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| 254 | * stop a thread in the same core
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| 255 | * input parameter:
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| 256 | * r3 = the thread physical id
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| 257 | */
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| 258 | _GLOBAL(book3e_stop_thread)
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| 259 | cmpwi r3, 0
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| 260 | beq 10f
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| 261 | cmpwi r3, 1
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| 262 | beq 10f
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| 263 | /* If the thread id is invalid, just exit. */
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| 264 | b 13f
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| 265 | 10:
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| 266 | li r4, 1
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| 267 | sld r4, r4, r3
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| 268 | mtspr SPRN_TENC, r4
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| 269 | 13:
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| 270 | blr
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| 271 |
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| 272 | _GLOBAL(fsl_secondary_thread_init)
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| 273 | mfspr r4,SPRN_BUCSR
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| 274 |
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| 275 | /* Enable branch prediction */
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| 276 | lis r3,BUCSR_INIT@h
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| 277 | ori r3,r3,BUCSR_INIT@l
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| 278 | mtspr SPRN_BUCSR,r3
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| 279 | isync
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| 280 |
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| 281 | /*
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| 282 | * Fix PIR to match the linear numbering in the device tree.
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| 283 | *
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| 284 | * On e6500, the reset value of PIR uses the low three bits for
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| 285 | * the thread within a core, and the upper bits for the core
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| 286 | * number. There are two threads per core, so shift everything
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| 287 | * but the low bit right by two bits so that the cpu numbering is
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| 288 | * continuous.
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| 289 | *
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| 290 | * If the old value of BUCSR is non-zero, this thread has run
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| 291 | * before. Thus, we assume we are coming from kexec or a similar
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| 292 | * scenario, and PIR is already set to the correct value. This
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| 293 | * is a bit of a hack, but there are limited opportunities for
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| 294 | * getting information into the thread and the alternatives
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| 295 | * seemed like they'd be overkill. We can't tell just by looking
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| 296 | * at the old PIR value which state it's in, since the same value
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| 297 | * could be valid for one thread out of reset and for a different
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| 298 | * thread in Linux.
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| 299 | */
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| 300 |
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| 301 | mfspr r3, SPRN_PIR
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| 302 | cmpwi r4,0
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| 303 | bne 1f
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| 304 | rlwimi r3, r3, 30, 2, 30
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| 305 | mtspr SPRN_PIR, r3
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| 306 | 1:
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| 307 | mr r24,r3
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| 308 |
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| 309 | /* turn on 64-bit mode */
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| 310 | bl enable_64b_mode
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| 311 |
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| 312 | /* Book3E initialization */
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| 313 | mr r3,r24
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| 314 | bl book3e_secondary_thread_init
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| 315 | bl relative_toc
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| 316 |
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| 317 | b generic_secondary_common_init
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| 318 |
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| 319 | |
| 320 |
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| 321 | /*
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| 322 | * On pSeries and most other platforms, secondary processors spin
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| 323 | * in the following code.
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| 324 | * At entry, r3 = this processor's number (physical cpu id)
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| 325 | *
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| 326 | * On Book3E, r4 = 1 to indicate that the initial TLB entry for
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| 327 | * this core already exists (setup via some other mechanism such
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| 328 | * as SCOM before entry).
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| 329 | */
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| 330 | _GLOBAL(generic_secondary_smp_init)
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| 331 | FIXUP_ENDIAN
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| 332 |
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| 333 | li r13,0
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| 334 |
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| 335 | /* Poison TOC */
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| 336 | li r2,-1
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| 337 |
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| 338 | mr r24,r3
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| 339 | mr r25,r4
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| 340 |
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| 341 | /* turn on 64-bit mode */
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| 342 | bl enable_64b_mode
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| 343 |
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| 344 | #ifdef CONFIG_PPC_BOOK3E_64
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| 345 | /* Book3E initialization */
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| 346 | mr r3,r24
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| 347 | mr r4,r25
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| 348 | bl book3e_secondary_core_init
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| 349 | /* Now NIA and r2 are relocated to PAGE_OFFSET if not already */
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| 350 | /*
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| 351 | * After common core init has finished, check if the current thread is the
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| 352 | * one we wanted to boot. If not, start the specified thread and stop the
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| 353 | * current thread.
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| 354 | */
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| 355 | LOAD_REG_ADDR(r4, booting_thread_hwid)
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| 356 | lwz r3, 0(r4)
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| 357 | li r5, INVALID_THREAD_HWID
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| 358 | cmpw r3, r5
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| 359 | beq 20f
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| 360 |
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| 361 | /*
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| 362 | * The value of booting_thread_hwid has been stored in r3,
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| 363 | * so make it invalid.
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| 364 | */
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| 365 | stw r5, 0(r4)
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| 366 |
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| 367 | /*
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| 368 | * Get the current thread id and check if it is the one we wanted.
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| 369 | * If not, start the one specified in booting_thread_hwid and stop
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| 370 | * the current thread.
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| 371 | */
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| 372 | mfspr r8, SPRN_TIR
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| 373 | cmpw r3, r8
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| 374 | beq 20f
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| 375 |
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| 376 | /* start the specified thread */
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| 377 | LOAD_REG_ADDR(r5, DOTSYM(fsl_secondary_thread_init))
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| 378 | bl book3e_start_thread
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| 379 |
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| 380 | /* stop the current thread */
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| 381 | mr r3, r8
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| 382 | bl book3e_stop_thread
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| 383 | 10:
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| 384 | b 10b
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| 385 | 20:
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| 386 | #else
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| 387 | /* Now the MMU is off, can branch to our PAGE_OFFSET address */
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| 388 | bcl 20,31,$+4
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| 389 | 1: mflr r11
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| 390 | addi r11,r11,(2f - 1b)
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| 391 | tovirt(r11, r11)
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| 392 | mtctr r11
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| 393 | bctr
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| 394 | 2:
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| 395 | bl relative_toc
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| 396 | #endif
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| 397 |
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| 398 | generic_secondary_common_init:
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| 399 | /* Set up a paca value for this processor. Since we have the
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| 400 | * physical cpu id in r24, we need to search the pacas to find
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| 401 | * which logical id maps to our physical one.
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| 402 | */
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| 403 | #ifndef CONFIG_SMP
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| 404 | b kexec_wait /* wait for next kernel if !SMP */
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| 405 | #else
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| 406 | LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
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| 407 | ld r8,0(r8) /* Get base vaddr of array */
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| 408 | #if (NR_CPUS == 1) || defined(CONFIG_FORCE_NR_CPUS)
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| 409 | LOAD_REG_IMMEDIATE(r7, NR_CPUS)
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| 410 | #else
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| 411 | LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
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| 412 | lwz r7,0(r7) /* also the max paca allocated */
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| 413 | #endif
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| 414 | li r5,0 /* logical cpu id */
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| 415 | 1:
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| 416 | sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
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| 417 | ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
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| 418 | lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
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| 419 | cmpw r6,r24 /* Compare to our id */
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| 420 | beq 2f
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| 421 | addi r5,r5,1
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| 422 | cmpw r5,r7 /* Check if more pacas exist */
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| 423 | blt 1b
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| 424 |
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| 425 | mr r3,r24 /* not found, copy phys to r3 */
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| 426 | b kexec_wait /* next kernel might do better */
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| 427 |
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| 428 | 2: SET_PACA(r13)
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| 429 | #ifdef CONFIG_PPC_BOOK3E_64
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| 430 | addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
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| 431 | mtspr SPRN_SPRG_TLB_EXFRAME,r12
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| 432 | #endif
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| 433 |
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| 434 | /* From now on, r24 is expected to be logical cpuid */
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| 435 | mr r24,r5
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| 436 |
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| 437 | /* Create a temp kernel stack for use before relocation is on. */
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| 438 | ld r1,PACAEMERGSP(r13)
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| 439 | subi r1,r1,STACK_FRAME_MIN_SIZE
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| 440 |
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| 441 | /* See if we need to call a cpu state restore handler */
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| 442 | LOAD_REG_ADDR(r23, cur_cpu_spec)
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| 443 | ld r23,0(r23)
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| 444 | ld r12,CPU_SPEC_RESTORE(r23)
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| 445 | cmpdi 0,r12,0
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| 446 | beq 3f
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| 447 | #ifdef CONFIG_PPC64_ELF_ABI_V1
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| 448 | ld r12,0(r12)
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| 449 | #endif
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| 450 | mtctr r12
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| 451 | bctrl
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| 452 |
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| 453 | 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
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| 454 | lwarx r4,0,r3
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| 455 | subi r4,r4,1
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| 456 | stwcx. r4,0,r3
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| 457 | bne 3b
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| 458 | isync
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| 459 |
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| 460 | 4: HMT_LOW
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| 461 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
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| 462 | /* start. */
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| 463 | cmpwi 0,r23,0
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| 464 | beq 4b /* Loop until told to go */
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| 465 |
|
| 466 | sync /* order paca.run and cur_cpu_spec */
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| 467 | isync /* In case code patching happened */
|
| 468 |
|
| 469 | b __secondary_start
|
| 470 | #endif /* SMP */
|
| 471 |
|
| 472 | /*
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| 473 | * Turn the MMU off.
|
| 474 | * Assumes we're mapped EA == RA if the MMU is on.
|
| 475 | */
|
| 476 | |
| 477 | SYM_FUNC_START_LOCAL(__mmu_off)
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| 478 | mfmsr r3
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| 479 | andi. r0,r3,MSR_IR|MSR_DR
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| 480 | beqlr
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| 481 | mflr r4
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| 482 | andc r3,r3,r0
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| 483 | mtspr SPRN_SRR0,r4
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| 484 | mtspr SPRN_SRR1,r3
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| 485 | sync
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| 486 | rfid
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| 487 | b . /* prevent speculative execution */
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| 488 | SYM_FUNC_END(__mmu_off)
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| 489 |
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| 490 | SYM_FUNC_START_LOCAL(start_initialization_book3s)
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| 491 | mflr r25
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| 492 |
|
| 493 | /* Setup some critical 970 SPRs before switching MMU off */
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| 494 | mfspr r0,SPRN_PVR
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| 495 | srwi r0,r0,16
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| 496 | cmpwi r0,0x39 /* 970 */
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| 497 | beq 1f
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| 498 | cmpwi r0,0x3c /* 970FX */
|
| 499 | beq 1f
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| 500 | cmpwi r0,0x44 /* 970MP */
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| 501 | beq 1f
|
| 502 | cmpwi r0,0x45 /* 970GX */
|
| 503 | bne 2f
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| 504 | 1: bl __cpu_preinit_ppc970
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| 505 | 2:
|
| 506 |
|
| 507 | /* Switch off MMU if not already off */
|
| 508 | bl __mmu_off
|
| 509 |
|
| 510 | /* Now the MMU is off, can return to our PAGE_OFFSET address */
|
| 511 | tovirt(r25,r25)
|
| 512 | mtlr r25
|
| 513 | blr
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| 514 | SYM_FUNC_END(start_initialization_book3s)
|
| 515 | |
| 516 |
|
| 517 | /*
|
| 518 | * Here is our main kernel entry point. We support currently 2 kind of entries
|
| 519 | * depending on the value of r5.
|
| 520 | *
|
| 521 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
|
| 522 | * in r3...r7
|
| 523 | *
|
| 524 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
|
| 525 | * DT block, r4 is a physical pointer to the kernel itself
|
| 526 | *
|
| 527 | */
|
| 528 | __start_initialization_multiplatform:
|
| 529 | /* Make sure we are running in 64 bits mode */
|
| 530 | bl enable_64b_mode
|
| 531 |
|
| 532 | /* Zero r13 (paca) so early program check / mce don't use it */
|
| 533 | li r13,0
|
| 534 |
|
| 535 | /* Poison TOC */
|
| 536 | li r2,-1
|
| 537 |
|
| 538 | /*
|
| 539 | * Are we booted from a PROM Of-type client-interface ?
|
| 540 | */
|
| 541 | cmpldi cr0,r5,0
|
| 542 | beq 1f
|
| 543 | b __boot_from_prom /* yes -> prom */
|
| 544 | 1:
|
| 545 | /* Save parameters */
|
| 546 | mr r31,r3
|
| 547 | mr r30,r4
|
| 548 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
|
| 549 | /* Save OPAL entry */
|
| 550 | mr r28,r8
|
| 551 | mr r29,r9
|
| 552 | #endif
|
| 553 |
|
| 554 | /* Get TOC pointer (current runtime address) */
|
| 555 | bl relative_toc
|
| 556 |
|
| 557 | /* These functions return to the virtual (PAGE_OFFSET) address */
|
| 558 | #ifdef CONFIG_PPC_BOOK3E_64
|
| 559 | bl start_initialization_book3e
|
| 560 | #else
|
| 561 | bl start_initialization_book3s
|
| 562 | #endif /* CONFIG_PPC_BOOK3E_64 */
|
| 563 |
|
| 564 | /* Get TOC pointer, virtual */
|
| 565 | bl relative_toc
|
| 566 |
|
| 567 | /* find out where we are now */
|
| 568 |
|
| 569 | /* OPAL doesn't pass base address in r4, have to derive it. */
|
| 570 | bcl 20,31,$+4
|
| 571 | 0: mflr r26 /* r26 = runtime addr here */
|
| 572 | addis r26,r26,(_stext - 0b)@ha
|
| 573 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
|
| 574 |
|
| 575 | b __after_prom_start
|
| 576 |
|
| 577 | __REF
|
| 578 | __boot_from_prom:
|
| 579 | |
| 580 | /* Get TOC pointer, non-virtual */
|
| 581 | bl relative_toc
|
| 582 |
|
| 583 | /* find out where we are now */
|
| 584 | bcl 20,31,$+4
|
| 585 | 0: mflr r26 /* r26 = runtime addr here */
|
| 586 | addis r26,r26,(_stext - 0b)@ha
|
| 587 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
|
| 588 |
|
| 589 | /* Save parameters */
|
| 590 | mr r31,r3
|
| 591 | mr r30,r4
|
| 592 | mr r29,r5
|
| 593 | mr r28,r6
|
| 594 | mr r27,r7
|
| 595 |
|
| 596 | /*
|
| 597 | * Align the stack to 16-byte boundary
|
| 598 | * Depending on the size and layout of the ELF sections in the initial
|
| 599 | * boot binary, the stack pointer may be unaligned on PowerMac
|
| 600 | */
|
| 601 | rldicr r1,r1,0,59
|
| 602 |
|
| 603 | |
| 604 | /* Relocate code for where we are now */
|
| 605 | mr r3,r26
|
| 606 | bl relocate
|
| 607 | |
| 608 |
|
| 609 | /* Restore parameters */
|
| 610 | mr r3,r31
|
| 611 | mr r4,r30
|
| 612 | mr r5,r29
|
| 613 | mr r6,r28
|
| 614 | mr r7,r27
|
| 615 |
|
| 616 | /* Do all of the interaction with OF client interface */
|
| 617 | mr r8,r26
|
| 618 | bl CFUNC(prom_init)
|
| 619 | |
| 620 |
|
| 621 | /* We never return. We also hit that trap if trying to boot
|
| 622 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
|
| 623 | trap
|
| 624 | .previous
|
| 625 |
|
| 626 | __after_prom_start:
|
| 627 | #ifdef CONFIG_RELOCATABLE
|
| 628 | /* process relocations for the final address of the kernel */
|
| 629 | lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
|
| 630 | cmplwi cr0,r7,1 /* flagged to stay where we are ? */
|
| 631 | mr r25,r26 /* then use current kernel base */
|
| 632 | beq 1f
|
| 633 | LOAD_REG_IMMEDIATE(r25, PAGE_OFFSET) /* else use static kernel base */
|
| 634 | 1: mr r3,r25
|
| 635 | bl relocate
|
| 636 | #if defined(CONFIG_PPC_BOOK3E_64)
|
| 637 | /* IVPR needs to be set after relocation. */
|
| 638 | bl init_core_book3e
|
| 639 | #endif
|
| 640 | #endif
|
| 641 |
|
| 642 | /*
|
| 643 | * We need to run with _stext at physical address PHYSICAL_START.
|
| 644 | * This will leave some code in the first 256B of
|
| 645 | * real memory, which are reserved for software use.
|
| 646 | *
|
| 647 | * Note: This process overwrites the OF exception vectors.
|
| 648 | */
|
| 649 | LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET)
|
| 650 | mr r4,r26 /* Load the virtual source address into r4 */
|
| 651 | cmpld r3,r4 /* Check if source == dest */
|
| 652 | beq 9f /* If so skip the copy */
|
| 653 | li r6,0x100 /* Start offset, the first 0x100 */
|
| 654 | /* bytes were copied earlier. */
|
| 655 |
|
| 656 | #ifdef CONFIG_RELOCATABLE
|
| 657 | /*
|
| 658 | * Check if the kernel has to be running as relocatable kernel based on the
|
| 659 | * variable __run_at_load, if it is set the kernel is treated as relocatable
|
| 660 | * kernel, otherwise it will be moved to PHYSICAL_START
|
| 661 | */
|
| 662 | lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
|
| 663 | cmplwi cr0,r7,1
|
| 664 | bne 3f
|
| 665 |
|
| 666 | #ifdef CONFIG_PPC_BOOK3E_64
|
| 667 | LOAD_REG_ADDR(r5, __end_interrupts)
|
| 668 | LOAD_REG_ADDR(r11, _stext)
|
| 669 | sub r5,r5,r11
|
| 670 | #else
|
| 671 | /* just copy interrupts */
|
| 672 | LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
|
| 673 | #endif
|
| 674 | b 5f
|
| 675 | 3:
|
| 676 | #endif
|
| 677 | /* # bytes of memory to copy */
|
| 678 | lis r5,(ABS_ADDR(copy_to_here, text))@ha
|
| 679 | addi r5,r5,(ABS_ADDR(copy_to_here, text))@l
|
| 680 |
|
| 681 | bl copy_and_flush /* copy the first n bytes */
|
| 682 | /* this includes the code being */
|
| 683 | /* executed here. */
|
| 684 | /* Jump to the copy of this code that we just made */
|
| 685 | addis r8,r3,(ABS_ADDR(4f, text))@ha
|
| 686 | addi r12,r8,(ABS_ADDR(4f, text))@l
|
| 687 | mtctr r12
|
| 688 | bctr
|
| 689 |
|
| 690 | .balign 8
|
| 691 | p_end: .8byte _end - copy_to_here
|
| 692 |
|
| 693 | 4:
|
| 694 | /*
|
| 695 | * Now copy the rest of the kernel up to _end, add
|
| 696 | * _end - copy_to_here to the copy limit and run again.
|
| 697 | */
|
| 698 | addis r8,r26,(ABS_ADDR(p_end, text))@ha
|
| 699 | ld r8,(ABS_ADDR(p_end, text))@l(r8)
|
| 700 | add r5,r5,r8
|
| 701 | 5: bl copy_and_flush /* copy the rest */
|
| 702 |
|
| 703 | 9: b start_here_multiplatform
|
| 704 |
|
| 705 | /*
|
| 706 | * Copy routine used to copy the kernel to start at physical address 0
|
| 707 | * and flush and invalidate the caches as needed.
|
| 708 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
|
| 709 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
|
| 710 | *
|
| 711 | * Note: this routine *only* clobbers r0, r6 and lr
|
| 712 | */
|
| 713 | _GLOBAL(copy_and_flush)
|
| 714 | addi r5,r5,-8
|
| 715 | addi r6,r6,-8
|
| 716 | 4: li r0,8 /* r0 is the number of 8-byte words */
|
| 717 | /* to copy per cache sync iteration. */
|
| 718 | /* 8 words * 8 bytes = 64 bytes. 64B is */
|
| 719 | /* the current default cache line size. */
|
| 720 | /* This is a loop count, not a byte */
|
| 721 | /* count. Increasing it may skip */
|
| 722 | /* dcbst/icbi for lines in between and */
|
| 723 | /* leave stale instructions in icache. */
|
| 724 | /* This results in extra cache line */
|
| 725 | /* flushes but operation is correct. */
|
| 726 | /* Can't get cache line size from NACA */
|
| 727 | /* as it is being moved too. */
|
| 728 |
|
| 729 | mtctr r0 /* put |
| 730 | 3: addi r6,r6,8 /* copy a cache line */
|
| 731 | ldx r0,r6,r4
|
| 732 | stdx r0,r6,r3
|
| 733 | bdnz 3b
|
| 734 | dcbst r6,r3 /* write it to memory */
|
| 735 | sync
|
| 736 | icbi r6,r3 /* flush the icache line */
|
| 737 | cmpld 0,r6,r5
|
| 738 | blt 4b
|
| 739 | sync
|
| 740 | addi r5,r5,8
|
| 741 | addi r6,r6,8
|
| 742 | isync
|
| 743 | blr
|
| 744 |
|
| 745 | _ASM_NOKPROBE_SYMBOL(copy_and_flush); /* Called in real mode */
|
| 746 |
|
| 747 | .align 8
|
| 748 | copy_to_here:
|
| 749 |
|
| 750 | |
| 751 | |
| 752 | /*
|
| 753 | * On PowerMac, secondary processors starts from the reset vector, which
|
| 754 | * is temporarily turned into a call to one of the functions below.
|
| 755 | */
|
| 756 | .section ".text";
|
| 757 | .align 2 ;
|
| 758 |
|
| 759 | .globl __secondary_start_pmac_0
|
| 760 | __secondary_start_pmac_0:
|
| 761 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
|
| 762 | li r24,0
|
| 763 | b 1f
|
| 764 | li r24,1
|
| 765 | b 1f
|
| 766 | li r24,2
|
| 767 | b 1f
|
| 768 | li r24,3
|
| 769 | 1:
|
| 770 |
|
| 771 | _GLOBAL(pmac_secondary_start)
|
| 772 | /* turn on 64-bit mode */
|
| 773 | bl enable_64b_mode
|
| 774 |
|
| 775 | li r0,0
|
| 776 | mfspr r3,SPRN_HID4
|
| 777 | rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
|
| 778 | sync
|
| 779 | mtspr SPRN_HID4,r3
|
| 780 | isync
|
| 781 | sync
|
| 782 | slbia
|
| 783 |
|
| 784 | /* Branch to our PAGE_OFFSET address */
|
| 785 | bcl 20,31,$+4
|
| 786 | 1: mflr r11
|
| 787 | addi r11,r11,(2f - 1b)
|
| 788 | tovirt(r11, r11)
|
| 789 | mtctr r11
|
| 790 | bctr
|
| 791 | 2:
|
| 792 | bl relative_toc
|
| 793 |
|
| 794 | /* Copy some CPU settings from CPU 0 */
|
| 795 | bl __restore_cpu_ppc970
|
| 796 |
|
| 797 | /* pSeries do that early though I don't think we really need it */
|
| 798 | mfmsr r3
|
| 799 | ori r3,r3,MSR_RI
|
| 800 | mtmsrd r3 /* RI on */
|
| 801 |
|
| 802 | /* Set up a paca value for this processor. */
|
| 803 | LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
|
| 804 | ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
|
| 805 | sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
|
| 806 | ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
|
| 807 | SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
|
| 808 |
|
| 809 | /* Mark interrupts soft and hard disabled (they might be enabled
|
| 810 | * in the PACA when doing hotplug)
|
| 811 | */
|
| 812 | li r0,IRQS_DISABLED
|
| 813 | stb r0,PACAIRQSOFTMASK(r13)
|
| 814 | li r0,PACA_IRQ_HARD_DIS
|
| 815 | stb r0,PACAIRQHAPPENED(r13)
|
| 816 |
|
| 817 | /* Create a temp kernel stack for use before relocation is on. */
|
| 818 | ld r1,PACAEMERGSP(r13)
|
| 819 | subi r1,r1,STACK_FRAME_MIN_SIZE
|
| 820 |
|
| 821 | b __secondary_start
|
| 822 |
|
| 823 | #endif /* CONFIG_PPC_PMAC */
|
| 824 |
|
| 825 | /*
|
| 826 | * This function is called after the master CPU has released the
|
| 827 | * secondary processors. The execution environment is relocation off.
|
| 828 | * The paca for this processor has the following fields initialized at
|
| 829 | * this point:
|
| 830 | * 1. Processor number
|
| 831 | * 2. Segment table pointer (virtual address)
|
| 832 | * On entry the following are set:
|
| 833 | * r1 = stack pointer (real addr of temp stack)
|
| 834 | * r24 = cpu# (in Linux terms)
|
| 835 | * r13 = paca virtual address
|
| 836 | * SPRG_PACA = paca virtual address
|
| 837 | */
|
| 838 | .section ".text";
|
| 839 | .align 2 ;
|
| 840 |
|
| 841 | .globl __secondary_start
|
| 842 | __secondary_start:
|
| 843 | /* Set thread priority to MEDIUM */
|
| 844 | HMT_MEDIUM
|
| 845 |
|
| 846 | /*
|
| 847 | * Do early setup for this CPU, in particular initialising the MMU so we
|
| 848 | * can turn it on below. This is a call to C, which is OK, we're still
|
| 849 | * running on the emergency stack.
|
| 850 | */
|
| 851 | bl CFUNC(early_setup_secondary)
|
| 852 |
|
| 853 | /*
|
| 854 | * The primary has initialized our kernel stack for us in the paca, grab
|
| 855 | * it and put it in r1. We must *not* use it until we turn on the MMU
|
| 856 | * below, because it may not be inside the RMO.
|
| 857 | */
|
| 858 | ld r1, PACAKSAVE(r13)
|
| 859 |
|
| 860 | /* Clear backchain so we get nice backtraces */
|
| 861 | li r7,0
|
| 862 | mtlr r7
|
| 863 |
|
| 864 | /* Mark interrupts soft and hard disabled (they might be enabled
|
| 865 | * in the PACA when doing hotplug)
|
| 866 | */
|
| 867 | li r7,IRQS_DISABLED
|
| 868 | stb r7,PACAIRQSOFTMASK(r13)
|
| 869 | li r0,PACA_IRQ_HARD_DIS
|
| 870 | stb r0,PACAIRQHAPPENED(r13)
|
| 871 |
|
| 872 | /* enable MMU and jump to start_secondary */
|
| 873 | LOAD_REG_ADDR(r3, start_secondary_prolog)
|
| 874 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
|
| 875 |
|
| 876 | mtspr SPRN_SRR0,r3
|
| 877 | mtspr SPRN_SRR1,r4
|
| 878 | RFI_TO_KERNEL
|
| 879 | b . /* prevent speculative execution */
|
| 880 |
|
| 881 | /*
|
| 882 | * Running with relocation on at this point. All we want to do is
|
| 883 | * zero the stack back-chain pointer and get the TOC virtual address
|
| 884 | * before going into C code.
|
| 885 | */
|
| 886 | start_secondary_prolog:
|
| 887 | LOAD_PACA_TOC()
|
| 888 | li r3,0
|
| 889 | std r3,0(r1) /* Zero the stack frame pointer */
|
| 890 | bl CFUNC(start_secondary)
|
| 891 | b .
|
| 892 | /*
|
| 893 | * Reset stack pointer and call start_secondary
|
| 894 | * to continue with online operation when woken up
|
| 895 | * from cede in cpu offline.
|
| 896 | */
|
| 897 | _GLOBAL(start_secondary_resume)
|
| 898 | ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
|
| 899 | li r3,0
|
| 900 | std r3,0(r1) /* Zero the stack frame pointer */
|
| 901 | bl CFUNC(start_secondary)
|
| 902 | b .
|
| 903 | |
| 904 |
|
| 905 | /*
|
| 906 | * This subroutine clobbers r11 and r12
|
| 907 | */
|
| 908 | SYM_FUNC_START_LOCAL(enable_64b_mode)
|
| 909 | mfmsr r11 /* grab the current MSR */
|
| 910 | |
| 911 | oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
|
| 912 | mtmsr r11
|
| 913 | #else /* CONFIG_PPC_BOOK3E_64 */
|
| 914 | LOAD_REG_IMMEDIATE(r12, MSR_64BIT)
|
| 915 | or r11,r11,r12
|
| 916 | mtmsrd r11
|
| 917 | isync
|
| 918 | #endif
|
| 919 | blr
|
| 920 | SYM_FUNC_END(enable_64b_mode)
|
| 921 |
|
| 922 | /*
|
| 923 | * This puts the TOC pointer into r2, offset by 0x8000 (as expected
|
| 924 | * by the toolchain). It computes the correct value for wherever we
|
| 925 | * are running at the moment, using position-independent code.
|
| 926 | *
|
| 927 | * Note: The compiler constructs pointers using offsets from the
|
| 928 | * TOC in -mcmodel=medium mode. After we relocate to 0 but before
|
| 929 | * the MMU is on we need our TOC to be a virtual address otherwise
|
| 930 | * these pointers will be real addresses which may get stored and
|
| 931 | * accessed later with the MMU on. We branch to the virtual address
|
| 932 | * while still in real mode then call relative_toc again to handle
|
| 933 | * this.
|
| 934 | */
|
| 935 | _GLOBAL(relative_toc)
|
| 936 | #ifdef CONFIG_PPC_KERNEL_PCREL
|
| 937 | tdnei r2,-1
|
| 938 | blr
|
| 939 | #else
|
| 940 | mflr r0
|
| 941 | bcl 20,31,$+4
|
| 942 | 0: mflr r11
|
| 943 | ld r2,(p_toc - 0b)(r11)
|
| 944 | add r2,r2,r11
|
| 945 | mtlr r0
|
| 946 | blr
|
| 947 |
|
| 948 | .balign 8
|
| 949 | p_toc: .8byte .TOC. - 0b
|
| 950 | #endif
|
| 951 |
|
| 952 | /*
|
| 953 | * This is where the main kernel code starts.
|
| 954 | */
|
| 955 | __REF
|
| 956 | start_here_multiplatform:
|
| 957 | /* Adjust TOC for moved kernel. Could adjust when moving it instead. */
|
| 958 | bl relative_toc
|
| 959 |
|
| 960 | /* Clear out the BSS. It may have been done in prom_init,
|
| 961 | * already but that's irrelevant since prom_init will soon
|
| 962 | * be detached from the kernel completely. Besides, we need
|
| 963 | * to clear it now for kexec-style entry.
|
| 964 | */
|
| 965 | LOAD_REG_ADDR(r11,__bss_stop)
|
| 966 | LOAD_REG_ADDR(r8,__bss_start)
|
| 967 | sub r11,r11,r8 /* bss size */
|
| 968 | addi r11,r11,7 /* round up to an even double word */
|
| 969 | srdi. r11,r11,3 /* shift right by 3 */
|
| 970 | beq 4f
|
| 971 | addi r8,r8,-8
|
| 972 | li r0,0
|
| 973 | mtctr r11 /* zero this many doublewords */
|
| 974 | 3: stdu r0,8(r8)
|
| 975 | bdnz 3b
|
| 976 | 4:
|
| 977 |
|
| 978 | |
| 979 | /* Setup OPAL entry */
|
| 980 | LOAD_REG_ADDR(r11, opal)
|
| 981 | std r28,0(r11);
|
| 982 | std r29,8(r11);
|
| 983 | |
| 984 |
|
| 985 | |
| 986 | mfmsr r6
|
| 987 | ori r6,r6,MSR_RI
|
| 988 | mtmsrd r6 /* RI on */
|
| 989 | |
| 990 |
|
| 991 | |
| 992 | /* Save the physical address we're running at in kernstart_addr */
|
| 993 | LOAD_REG_ADDR(r4, kernstart_addr)
|
| 994 | clrldi r0,r25,2
|
| 995 | std r0,0(r4)
|
| 996 | #endif
|
| 997 |
|
| 998 | /* set up a stack pointer */
|
| 999 | LOAD_REG_ADDR(r3,init_thread_union)
|
| 1000 | LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
|
| 1001 | add r1,r3,r1
|
| 1002 | li r0,0
|
| 1003 | stdu r0,-STACK_FRAME_MIN_SIZE(r1)
|
| 1004 |
|
| 1005 | /*
|
| 1006 | * Do very early kernel initializations, including initial hash table
|
| 1007 | * and SLB setup before we turn on relocation.
|
| 1008 | */
|
| 1009 |
|
| 1010 | #ifdef CONFIG_KASAN
|
| 1011 | bl CFUNC(kasan_early_init)
|
| 1012 | #endif
|
| 1013 | /* Restore parameters passed from prom_init/kexec */
|
| 1014 | mr r3,r31
|
| 1015 | LOAD_REG_ADDR(r12, DOTSYM(early_setup))
|
| 1016 | mtctr r12
|
| 1017 | bctrl /* also sets r13 and SPRG_PACA */
|
| 1018 |
|
| 1019 | LOAD_REG_ADDR(r3, start_here_common)
|
| 1020 | ld r4,PACAKMSR(r13)
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| 1021 | mtspr SPRN_SRR0,r3
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| 1022 | mtspr SPRN_SRR1,r4
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| 1023 | RFI_TO_KERNEL
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| 1024 | b . /* prevent speculative execution */
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| 1025 |
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| 1026 | /* This is where all platforms converge execution */
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| 1027 |
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| 1028 | start_here_common:
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| 1029 | /* relocation is on at this point */
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| 1030 | std r1,PACAKSAVE(r13)
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| 1031 |
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| 1032 | /* Load the TOC (virtual address) */
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| 1033 | LOAD_PACA_TOC()
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| 1034 |
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| 1035 | /* Mark interrupts soft and hard disabled (they might be enabled
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| 1036 | * in the PACA when doing hotplug)
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| 1037 | */
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| 1038 | li r0,IRQS_DISABLED
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| 1039 | stb r0,PACAIRQSOFTMASK(r13)
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| 1040 | li r0,PACA_IRQ_HARD_DIS
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| 1041 | stb r0,PACAIRQHAPPENED(r13)
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| 1042 |
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| 1043 | /* Generic kernel entry */
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| 1044 | bl CFUNC(start_kernel)
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| 1045 |
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| 1046 | /* Not reached */
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| 1047 | 0: trap
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| 1048 | EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
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| 1049 | .previous
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