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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Derived from arch/i386/kernel/irq.c
4 * Copyright (C) 1992 Linus Torvalds
5 * Adapted from arch/i386 by Gary Thomas
6 * Copyright (C) 1995-1996 Gary Thomas ([email protected])
7 * Updated and modified by Cort Dougan <[email protected]>
8 * Copyright (C) 1996-2001 Cort Dougan
9 * Adapted for Power Macintosh by Paul Mackerras
10 * Copyright (C) 1996 Paul Mackerras ([email protected])
11 *
12 * This file contains the code used by various IRQ handling routines:
13 * asking for different IRQ's should be done through these routines
14 * instead of just grabbing them. Thus setups with different IRQ numbers
15 * shouldn't result in any weird surprises, and installing new handlers
16 * should be easier.
17 *
18 * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the
19 * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit
20 * mask register (of which only 16 are defined), hence the weird shifting
21 * and complement of the cached_irq_mask. I want to be able to stuff
22 * this right into the SIU SMASK register.
23 * Many of the prep/chrp functions are conditional compiled on CONFIG_PPC_8xx
24 * to reduce code space and undefined function references.
25 */
26
27#undef DEBUG
28
29#include <linux/export.h>
30#include <linux/threads.h>
31#include <linux/kernel_stat.h>
32#include <linux/signal.h>
33#include <linux/sched.h>
34#include <linux/ptrace.h>
35#include <linux/ioport.h>
36#include <linux/interrupt.h>
37#include <linux/timex.h>
38#include <linux/init.h>
39#include <linux/slab.h>
40#include <linux/delay.h>
41#include <linux/irq.h>
42#include <linux/seq_file.h>
43#include <linux/cpumask.h>
44#include <linux/profile.h>
45#include <linux/bitops.h>
46#include <linux/list.h>
47#include <linux/radix-tree.h>
48#include <linux/mutex.h>
49#include <linux/pci.h>
50#include <linux/debugfs.h>
51#include <linux/of.h>
52#include <linux/of_irq.h>
53#include <linux/vmalloc.h>
54#include <linux/pgtable.h>
55#include <linux/static_call.h>
56
57#include <linux/uaccess.h>
58#include <asm/interrupt.h>
59#include <asm/io.h>
60#include <asm/irq.h>
61#include <asm/cache.h>
62#include <asm/ptrace.h>
63#include <asm/machdep.h>
64#include <asm/udbg.h>
65#include <asm/smp.h>
66#include <asm/hw_irq.h>
67#include <asm/softirq_stack.h>
68#include <asm/ppc_asm.h>
69
70#define CREATE_TRACE_POINTS
71#include <asm/trace.h>
72#include <asm/cpu_has_feature.h>
73
74DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
75EXPORT_PER_CPU_SYMBOL(irq_stat);
76
77#ifdef CONFIG_PPC32
78atomic_t ppc_n_lost_interrupts;
79
80#ifdef CONFIG_TAU_INT
81extern int tau_initialized;
82u32 tau_interrupts(unsigned long cpu);
83#endif
84#endif /* CONFIG_PPC32 */
85
86int arch_show_interrupts(struct seq_file *p, int prec)
87{
88 int j;
89
90#if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
91 if (tau_initialized) {
92 seq_printf(p, "%*s:", prec, "TAU");
93 for_each_online_cpu(j)
94 seq_put_decimal_ull_width(p, " ", tau_interrupts(j), 10);
95 seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n");
96 }
97#endif /* CONFIG_PPC32 && CONFIG_TAU_INT */
98
99 seq_printf(p, "%*s:", prec, "LOC");
100 for_each_online_cpu(j)
101 seq_put_decimal_ull_width(p, " ", per_cpu(irq_stat, j).timer_irqs_event, 10);
102 seq_printf(p, " Local timer interrupts for timer event device\n");
103
104 seq_printf(p, "%*s:", prec, "BCT");
105 for_each_online_cpu(j)
106 seq_put_decimal_ull_width(p, " ", per_cpu(irq_stat, j).broadcast_irqs_event, 10);
107 seq_printf(p, " Broadcast timer interrupts for timer event device\n");
108
109 seq_printf(p, "%*s:", prec, "LOC");
110 for_each_online_cpu(j)
111 seq_put_decimal_ull_width(p, " ", per_cpu(irq_stat, j).timer_irqs_others, 10);
112 seq_printf(p, " Local timer interrupts for others\n");
113
114 seq_printf(p, "%*s:", prec, "SPU");
115 for_each_online_cpu(j)
116 seq_put_decimal_ull_width(p, " ", per_cpu(irq_stat, j).spurious_irqs, 10);
117 seq_printf(p, " Spurious interrupts\n");
118
119 seq_printf(p, "%*s:", prec, "PMI");
120 for_each_online_cpu(j)
121 seq_put_decimal_ull_width(p, " ", per_cpu(irq_stat, j).pmu_irqs, 10);
122 seq_printf(p, " Performance monitoring interrupts\n");
123
124 seq_printf(p, "%*s:", prec, "MCE");
125 for_each_online_cpu(j)
126 seq_put_decimal_ull_width(p, " ", per_cpu(irq_stat, j).mce_exceptions, 10);
127 seq_printf(p, " Machine check exceptions\n");
128
129#ifdef CONFIG_PPC_BOOK3S_64
130 if (cpu_has_feature(CPU_FTR_HVMODE)) {
131 seq_printf(p, "%*s:", prec, "HMI");
132 for_each_online_cpu(j)
133 seq_put_decimal_ull_width(p, " ", paca_ptrs[j]->hmi_irqs, 10);
134 seq_printf(p, " Hypervisor Maintenance Interrupts\n");
135 }
136#endif
137
138 seq_printf(p, "%*s:", prec, "NMI");
139 for_each_online_cpu(j)
140 seq_put_decimal_ull_width(p, " ", per_cpu(irq_stat, j).sreset_irqs, 10);
141 seq_printf(p, " System Reset interrupts\n");
142
143#ifdef CONFIG_PPC_WATCHDOG
144 seq_printf(p, "%*s:", prec, "WDG");
145 for_each_online_cpu(j)
146 seq_put_decimal_ull_width(p, " ", per_cpu(irq_stat, j).soft_nmi_irqs, 10);
147 seq_printf(p, " Watchdog soft-NMI interrupts\n");
148#endif
149
150#ifdef CONFIG_PPC_DOORBELL
151 if (cpu_has_feature(CPU_FTR_DBELL)) {
152 seq_printf(p, "%*s:", prec, "DBL");
153 for_each_online_cpu(j)
154 seq_put_decimal_ull_width(p, " ", per_cpu(irq_stat, j).doorbell_irqs, 10);
155 seq_printf(p, " Doorbell interrupts\n");
156 }
157#endif
158
159 return 0;
160}
161
162/*
163 * /proc/stat helpers
164 */
165u64 arch_irq_stat_cpu(unsigned int cpu)
166{
167 u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event;
168
169 sum += per_cpu(irq_stat, cpu).broadcast_irqs_event;
170 sum += per_cpu(irq_stat, cpu).pmu_irqs;
171 sum += per_cpu(irq_stat, cpu).mce_exceptions;
172 sum += per_cpu(irq_stat, cpu).spurious_irqs;
173 sum += per_cpu(irq_stat, cpu).timer_irqs_others;
174#ifdef CONFIG_PPC_BOOK3S_64
175 sum += paca_ptrs[cpu]->hmi_irqs;
176#endif
177 sum += per_cpu(irq_stat, cpu).sreset_irqs;
178#ifdef CONFIG_PPC_WATCHDOG
179 sum += per_cpu(irq_stat, cpu).soft_nmi_irqs;
180#endif
181#ifdef CONFIG_PPC_DOORBELL
182 sum += per_cpu(irq_stat, cpu).doorbell_irqs;
183#endif
184
185 return sum;
186}
187
188static inline void check_stack_overflow(unsigned long sp)
189{
190 if (!IS_ENABLED(CONFIG_DEBUG_STACKOVERFLOW))
191 return;
192
193 sp &= THREAD_SIZE - 1;
194
195 /* check for stack overflow: is there less than 1/4th free? */
196 if (unlikely(sp < THREAD_SIZE / 4)) {
197 pr_err("do_IRQ: stack overflow: %ld\n", sp);
198 dump_stack();
199 }
200}
201
202#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
203static __always_inline void call_do_softirq(const void *sp)
204{
205 /* Temporarily switch r1 to sp, call __do_softirq() then restore r1. */
206 asm volatile (
207 PPC_STLU " %%r1, %[offset](%[sp]) ;"
208 "mr %%r1, %[sp] ;"
209#ifdef CONFIG_PPC_KERNEL_PCREL
210 "bl %[callee]@notoc ;"
211#else
212 "bl %[callee] ;"
213#endif
214 PPC_LL " %%r1, 0(%%r1) ;"
215 : // Outputs
216 : // Inputs
217 [sp] "b" (sp), [offset] "i" (THREAD_SIZE - STACK_FRAME_MIN_SIZE),
218 [callee] "i" (__do_softirq)
219 : // Clobbers
220 "lr", "xer", "ctr", "memory", "cr0", "cr1", "cr5", "cr6", "cr7", "r0",
221 /* r2 may be clobbered by the callee when using PCREL mode in the ELFv2 ABI. */
222#ifdef CONFIG_PPC_KERNEL_PCREL
223 "r2",
224#endif
225 "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
226 "r11", "r12"
227 );
228}
229#endif
230
231DEFINE_STATIC_CALL_RET0(ppc_get_irq, *ppc_md.get_irq);
232
233static void __do_irq(struct pt_regs *regs, unsigned long oldsp)
234{
235 unsigned int irq;
236
237 trace_irq_entry(regs);
238
239 check_stack_overflow(oldsp);
240
241 /*
242 * Query the platform PIC for the interrupt & ack it.
243 *
244 * This will typically lower the interrupt line to the CPU
245 */
246 irq = static_call(ppc_get_irq)();
247
248 /* We can hard enable interrupts now to allow perf interrupts */
249 if (should_hard_irq_enable(regs))
250 do_hard_irq_enable();
251
252 /* And finally process it */
253 if (unlikely(!irq))
254 __this_cpu_inc(irq_stat.spurious_irqs);
255 else
256 generic_handle_irq(irq);
257
258 trace_irq_exit(regs);
259}
260
261static __always_inline void call_do_irq(struct pt_regs *regs, void *sp)
262{
263 register unsigned long r3 asm("r3") = (unsigned long)regs;
264
265 /* Temporarily switch r1 to sp, call __do_irq() then restore r1. */
266 asm volatile (
267 PPC_STLU " %%r1, %[offset](%[sp]) ;"
268 "mr %%r4, %%r1 ;"
269 "mr %%r1, %[sp] ;"
270#ifdef CONFIG_PPC_KERNEL_PCREL
271 "bl %[callee]@notoc ;"
272#else
273 "bl %[callee] ;"
274#endif
275 PPC_LL " %%r1, 0(%%r1) ;"
276 : // Outputs
277 "+r" (r3)
278 : // Inputs
279 [sp] "b" (sp), [offset] "i" (THREAD_SIZE - STACK_FRAME_MIN_SIZE),
280 [callee] "i" (__do_irq)
281 : // Clobbers
282 "lr", "xer", "ctr", "memory", "cr0", "cr1", "cr5", "cr6", "cr7", "r0",
283 /* r2 may be clobbered by the callee when using PCREL mode in the ELFv2 ABI. */
284#ifdef CONFIG_PPC_KERNEL_PCREL
285 "r2",
286#endif
287 "r4", "r5", "r6", "r7", "r8", "r9", "r10",
288 "r11", "r12"
289 );
290}
291
292void __do_IRQ(struct pt_regs *regs)
293{
294 struct pt_regs *old_regs = set_irq_regs(regs);
295 void *cursp, *irqsp;
296
297 /* Switch to the irq stack to handle this */
298 cursp = (void *)(current_stack_pointer & ~(THREAD_SIZE - 1));
299 irqsp = hardirq_ctx[raw_smp_processor_id()];
300
301 /* Already there ? If not switch stack and call */
302 if (unlikely(cursp == irqsp))
303 __do_irq(regs, current_stack_pointer);
304 else
305 call_do_irq(regs, irqsp);
306
307 set_irq_regs(old_regs);
308}
309
310DEFINE_INTERRUPT_HANDLER_ASYNC(do_IRQ)
311{
312 __do_IRQ(regs);
313}
314
315static void *__init alloc_vm_stack(void)
316{
317 return __vmalloc_node(THREAD_SIZE, THREAD_ALIGN, THREADINFO_GFP,
318 NUMA_NO_NODE, (void *)_RET_IP_);
319}
320
321static void __init vmap_irqstack_init(void)
322{
323 int i;
324
325 for_each_possible_cpu(i) {
326 softirq_ctx[i] = alloc_vm_stack();
327 hardirq_ctx[i] = alloc_vm_stack();
328 }
329}
330
331
332void __init init_IRQ(void)
333{
334 if (IS_ENABLED(CONFIG_VMAP_STACK))
335 vmap_irqstack_init();
336
337 if (ppc_md.init_IRQ)
338 ppc_md.init_IRQ();
339
340 if (!WARN_ON(!ppc_md.get_irq))
341 static_call_update(ppc_get_irq, ppc_md.get_irq);
342}
343
344#ifdef CONFIG_BOOKE
345void *critirq_ctx[NR_CPUS] __read_mostly;
346void *dbgirq_ctx[NR_CPUS] __read_mostly;
347void *mcheckirq_ctx[NR_CPUS] __read_mostly;
348#endif
349
350void *softirq_ctx[NR_CPUS] __read_mostly;
351void *hardirq_ctx[NR_CPUS] __read_mostly;
352
353#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
354void do_softirq_own_stack(void)
355{
356 call_do_softirq(softirq_ctx[smp_processor_id()]);
357}
358#endif
359
360irq_hw_number_t virq_to_hw(unsigned int virq)
361{
362 struct irq_data *irq_data = irq_get_irq_data(virq);
363 return WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
364}
365EXPORT_SYMBOL_GPL(virq_to_hw);
366
367#ifdef CONFIG_SMP
368int irq_choose_cpu(const struct cpumask *mask)
369{
370 int cpuid;
371
372 if (cpumask_equal(mask, cpu_online_mask)) {
373 static int irq_rover;
374 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
375 unsigned long flags;
376
377 /* Round-robin distribution... */
378do_round_robin:
379 raw_spin_lock_irqsave(&irq_rover_lock, flags);
380
381 irq_rover = cpumask_next_wrap(irq_rover, cpu_online_mask);
382 cpuid = irq_rover;
383
384 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
385 } else {
386 cpuid = cpumask_first_and(mask, cpu_online_mask);
387 if (cpuid >= nr_cpu_ids)
388 goto do_round_robin;
389 }
390
391 return get_hard_smp_processor_id(cpuid);
392}
393#else
394int irq_choose_cpu(const struct cpumask *mask)
395{
396 return hard_smp_processor_id();
397}
398#endif