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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
5 *
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 *
9 * Copyright (C) 2003 Anton Blanchard <[email protected]>, IBM
10 * Rework, based on alpha PCI code.
11 *
12 * Common pmac/prep/chrp pci routines. -- Cort
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/string.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/export.h>
21#include <linux/of_address.h>
22#include <linux/of_pci.h>
23#include <linux/mm.h>
24#include <linux/shmem_fs.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30#include <linux/vgaarb.h>
31#include <linux/numa.h>
32#include <linux/msi.h>
33#include <linux/irqdomain.h>
34
35#include <asm/processor.h>
36#include <asm/io.h>
37#include <asm/pci-bridge.h>
38#include <asm/byteorder.h>
39#include <asm/machdep.h>
40#include <asm/ppc-pci.h>
41#include <asm/eeh.h>
42#include <asm/setup.h>
43
44#include "../../../drivers/pci/pci.h"
45
46/* hose_spinlock protects accesses to the phb_bitmap. */
47static DEFINE_SPINLOCK(hose_spinlock);
48LIST_HEAD(hose_list);
49
50/* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
51#define MAX_PHBS 0x10000
52
53/*
54 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
55 * Accesses to this bitmap should be protected by hose_spinlock.
56 */
57static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
58
59/* ISA Memory physical address */
60resource_size_t isa_mem_base;
61EXPORT_SYMBOL(isa_mem_base);
62
63
64static const struct dma_map_ops *pci_dma_ops;
65
66void __init set_pci_dma_ops(const struct dma_map_ops *dma_ops)
67{
68 pci_dma_ops = dma_ops;
69}
70
71static int get_phb_number(struct device_node *dn)
72{
73 int ret, phb_id = -1;
74 u64 prop;
75
76 /*
77 * Try fixed PHB numbering first, by checking archs and reading
78 * the respective device-tree properties. Firstly, try reading
79 * standard "linux,pci-domain", then try reading "ibm,opal-phbid"
80 * (only present in powernv OPAL environment), then try device-tree
81 * alias and as the last try to use lower bits of "reg" property.
82 */
83 ret = of_get_pci_domain_nr(dn);
84 if (ret >= 0) {
85 prop = ret;
86 ret = 0;
87 }
88 if (ret)
89 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
90
91 if (ret) {
92 ret = of_alias_get_id(dn, "pci");
93 if (ret >= 0) {
94 prop = ret;
95 ret = 0;
96 }
97 }
98 if (ret) {
99 u32 prop_32;
100 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
101 prop = prop_32;
102 }
103
104 if (!ret)
105 phb_id = (int)(prop & (MAX_PHBS - 1));
106
107 spin_lock(&hose_spinlock);
108
109 /* We need to be sure to not use the same PHB number twice. */
110 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
111 goto out_unlock;
112
113 /* If everything fails then fallback to dynamic PHB numbering. */
114 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
115 BUG_ON(phb_id >= MAX_PHBS);
116 set_bit(phb_id, phb_bitmap);
117
118out_unlock:
119 spin_unlock(&hose_spinlock);
120
121 return phb_id;
122}
123
124struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
125{
126 struct pci_controller *phb;
127
128 phb = kzalloc_obj(struct pci_controller);
129 if (phb == NULL)
130 return NULL;
131
132 phb->global_number = get_phb_number(dev);
133
134 spin_lock(&hose_spinlock);
135 list_add_tail(&phb->list_node, &hose_list);
136 spin_unlock(&hose_spinlock);
137
138 phb->dn = of_node_get(dev);
139 phb->is_dynamic = slab_is_available();
140#ifdef CONFIG_PPC64
141 if (dev) {
142 int nid = of_node_to_nid(dev);
143
144 if (nid < 0 || !node_online(nid))
145 nid = NUMA_NO_NODE;
146
147 PHB_SET_NODE(phb, nid);
148 }
149#endif
150 return phb;
151}
152EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
153
154void pcibios_free_controller(struct pci_controller *phb)
155{
156 spin_lock(&hose_spinlock);
157
158 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
159 if (phb->global_number < MAX_PHBS)
160 clear_bit(phb->global_number, phb_bitmap);
161 of_node_put(phb->dn);
162 list_del(&phb->list_node);
163 spin_unlock(&hose_spinlock);
164
165 if (phb->is_dynamic)
166 kfree(phb);
167}
168EXPORT_SYMBOL_GPL(pcibios_free_controller);
169
170/*
171 * This function is used to call pcibios_free_controller()
172 * in a deferred manner: a callback from the PCI subsystem.
173 *
174 * _*DO NOT*_ call pcibios_free_controller() explicitly if
175 * this is used (or it may access an invalid *phb pointer).
176 *
177 * The callback occurs when all references to the root bus
178 * are dropped (e.g., child buses/devices and their users).
179 *
180 * It's called as .release_fn() of 'struct pci_host_bridge'
181 * which is associated with the 'struct pci_controller.bus'
182 * (root bus) - it expects .release_data to hold a pointer
183 * to 'struct pci_controller'.
184 *
185 * In order to use it, register .release_fn()/release_data
186 * like this:
187 *
188 * pci_set_host_bridge_release(bridge,
189 * pcibios_free_controller_deferred
190 * (void *) phb);
191 *
192 * e.g. in the pcibios_root_bridge_prepare() callback from
193 * pci_create_root_bus().
194 */
195void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
196{
197 struct pci_controller *phb = (struct pci_controller *)
198 bridge->release_data;
199
200 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
201
202 pcibios_free_controller(phb);
203}
204EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
205
206/*
207 * The function is used to return the minimal alignment
208 * for memory or I/O windows of the associated P2P bridge.
209 * By default, 4KiB alignment for I/O windows and 1MiB for
210 * memory windows.
211 */
212resource_size_t pcibios_window_alignment(struct pci_bus *bus,
213 unsigned long type)
214{
215 struct pci_controller *phb = pci_bus_to_host(bus);
216
217 if (phb->controller_ops.window_alignment)
218 return phb->controller_ops.window_alignment(bus, type);
219
220 /*
221 * PCI core will figure out the default
222 * alignment: 4KiB for I/O and 1MiB for
223 * memory window.
224 */
225 return 1;
226}
227
228void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
229{
230 struct pci_controller *hose = pci_bus_to_host(bus);
231
232 if (hose->controller_ops.setup_bridge)
233 hose->controller_ops.setup_bridge(bus, type);
234}
235
236void pcibios_reset_secondary_bus(struct pci_dev *dev)
237{
238 struct pci_controller *phb = pci_bus_to_host(dev->bus);
239
240 if (phb->controller_ops.reset_secondary_bus) {
241 phb->controller_ops.reset_secondary_bus(dev);
242 return;
243 }
244
245 pci_reset_secondary_bus(dev);
246}
247
248resource_size_t pcibios_default_alignment(void)
249{
250 if (ppc_md.pcibios_default_alignment)
251 return ppc_md.pcibios_default_alignment();
252
253 return 0;
254}
255
256#ifdef CONFIG_PCI_IOV
257resource_size_t pcibios_iov_resource_alignment(const struct pci_dev *pdev, int resno)
258{
259 if (ppc_md.pcibios_iov_resource_alignment)
260 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
261
262 return pci_iov_resource_size(pdev, resno);
263}
264
265int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
266{
267 if (ppc_md.pcibios_sriov_enable)
268 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
269
270 return 0;
271}
272
273int pcibios_sriov_disable(struct pci_dev *pdev)
274{
275 if (ppc_md.pcibios_sriov_disable)
276 return ppc_md.pcibios_sriov_disable(pdev);
277
278 return 0;
279}
280
281#endif /* CONFIG_PCI_IOV */
282
283static resource_size_t pcibios_io_size(const struct pci_controller *hose)
284{
285#ifdef CONFIG_PPC64
286 return hose->pci_io_size;
287#else
288 return resource_size(&hose->io_resource);
289#endif
290}
291
292int pcibios_vaddr_is_ioport(void __iomem *address)
293{
294 int ret = 0;
295 struct pci_controller *hose;
296 resource_size_t size;
297
298 spin_lock(&hose_spinlock);
299 list_for_each_entry(hose, &hose_list, list_node) {
300 size = pcibios_io_size(hose);
301 if (address >= hose->io_base_virt &&
302 address < (hose->io_base_virt + size)) {
303 ret = 1;
304 break;
305 }
306 }
307 spin_unlock(&hose_spinlock);
308 return ret;
309}
310
311unsigned long pci_address_to_pio(phys_addr_t address)
312{
313 struct pci_controller *hose;
314 resource_size_t size;
315 unsigned long ret = ~0;
316
317 spin_lock(&hose_spinlock);
318 list_for_each_entry(hose, &hose_list, list_node) {
319 size = pcibios_io_size(hose);
320 if (address >= hose->io_base_phys &&
321 address < (hose->io_base_phys + size)) {
322 unsigned long base =
323 (unsigned long)hose->io_base_virt - _IO_BASE;
324 ret = base + (address - hose->io_base_phys);
325 break;
326 }
327 }
328 spin_unlock(&hose_spinlock);
329
330 return ret;
331}
332EXPORT_SYMBOL_GPL(pci_address_to_pio);
333
334/*
335 * Return the domain number for this bus.
336 */
337int pci_domain_nr(struct pci_bus *bus)
338{
339 struct pci_controller *hose = pci_bus_to_host(bus);
340
341 return hose->global_number;
342}
343EXPORT_SYMBOL(pci_domain_nr);
344
345/* This routine is meant to be used early during boot, when the
346 * PCI bus numbers have not yet been assigned, and you need to
347 * issue PCI config cycles to an OF device.
348 * It could also be used to "fix" RTAS config cycles if you want
349 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
350 * config cycles.
351 */
352struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
353{
354 while(node) {
355 struct pci_controller *hose, *tmp;
356 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
357 if (hose->dn == node)
358 return hose;
359 node = node->parent;
360 }
361 return NULL;
362}
363
364struct pci_controller *pci_find_controller_for_domain(int domain_nr)
365{
366 struct pci_controller *hose;
367
368 list_for_each_entry(hose, &hose_list, list_node)
369 if (hose->global_number == domain_nr)
370 return hose;
371
372 return NULL;
373}
374
375struct pci_intx_virq {
376 int virq;
377 struct kref kref;
378 struct list_head list_node;
379};
380
381static LIST_HEAD(intx_list);
382static DEFINE_MUTEX(intx_mutex);
383
384static void ppc_pci_intx_release(struct kref *kref)
385{
386 struct pci_intx_virq *vi = container_of(kref, struct pci_intx_virq, kref);
387
388 list_del(&vi->list_node);
389 irq_dispose_mapping(vi->virq);
390 kfree(vi);
391}
392
393static int ppc_pci_unmap_irq_line(struct notifier_block *nb,
394 unsigned long action, void *data)
395{
396 struct pci_dev *pdev = to_pci_dev(data);
397
398 if (action == BUS_NOTIFY_DEL_DEVICE) {
399 struct pci_intx_virq *vi;
400
401 mutex_lock(&intx_mutex);
402 list_for_each_entry(vi, &intx_list, list_node) {
403 if (vi->virq == pdev->irq) {
404 kref_put(&vi->kref, ppc_pci_intx_release);
405 break;
406 }
407 }
408 mutex_unlock(&intx_mutex);
409 }
410
411 return NOTIFY_DONE;
412}
413
414static struct notifier_block ppc_pci_unmap_irq_notifier = {
415 .notifier_call = ppc_pci_unmap_irq_line,
416};
417
418static int ppc_pci_register_irq_notifier(void)
419{
420 return bus_register_notifier(&pci_bus_type, &ppc_pci_unmap_irq_notifier);
421}
422arch_initcall(ppc_pci_register_irq_notifier);
423
424/*
425 * Reads the interrupt pin to determine if interrupt is use by card.
426 * If the interrupt is used, then gets the interrupt line from the
427 * openfirmware and sets it in the pci_dev and pci_config line.
428 */
429static int pci_read_irq_line(struct pci_dev *pci_dev)
430{
431 int virq;
432 struct pci_intx_virq *vi, *vitmp;
433
434 /* Preallocate vi as rewind is complex if this fails after mapping */
435 vi = kzalloc_obj(struct pci_intx_virq);
436 if (!vi)
437 return -1;
438
439 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
440
441 /* Try to get a mapping from the device-tree */
442 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
443 if (virq <= 0) {
444 u8 line, pin;
445
446 /* If that fails, lets fallback to what is in the config
447 * space and map that through the default controller. We
448 * also set the type to level low since that's what PCI
449 * interrupts are. If your platform does differently, then
450 * either provide a proper interrupt tree or don't use this
451 * function.
452 */
453 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
454 goto error_exit;
455 if (pin == 0)
456 goto error_exit;
457 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
458 line == 0xff || line == 0) {
459 goto error_exit;
460 }
461 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
462 line, pin);
463
464 virq = irq_create_mapping(NULL, line);
465 if (virq)
466 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
467 }
468
469 if (!virq) {
470 pr_debug(" Failed to map !\n");
471 goto error_exit;
472 }
473
474 pr_debug(" Mapped to linux irq %d\n", virq);
475
476 pci_dev->irq = virq;
477
478 mutex_lock(&intx_mutex);
479 list_for_each_entry(vitmp, &intx_list, list_node) {
480 if (vitmp->virq == virq) {
481 kref_get(&vitmp->kref);
482 kfree(vi);
483 vi = NULL;
484 break;
485 }
486 }
487 if (vi) {
488 vi->virq = virq;
489 kref_init(&vi->kref);
490 list_add_tail(&vi->list_node, &intx_list);
491 }
492 mutex_unlock(&intx_mutex);
493
494 return 0;
495error_exit:
496 kfree(vi);
497 return -1;
498}
499
500/*
501 * Platform support for /proc/bus/pci/X/Y mmap()s.
502 * -- paulus.
503 */
504int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
505{
506 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
507 resource_size_t ioaddr = pci_resource_start(pdev, bar);
508
509 if (!hose)
510 return -EINVAL;
511
512 /* Convert to an offset within this PCI controller */
513 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
514
515 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
516 return 0;
517}
518
519/*
520 * This one is used by /dev/mem and video who have no clue about the
521 * PCI device, it tries to find the PCI device first and calls the
522 * above routine
523 */
524pgprot_t pci_phys_mem_access_prot(unsigned long pfn,
525 unsigned long size,
526 pgprot_t prot)
527{
528 struct pci_dev *pdev = NULL;
529 struct resource *found = NULL;
530 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
531 int i;
532
533 if (page_is_ram(pfn))
534 return prot;
535
536 prot = pgprot_noncached(prot);
537 for_each_pci_dev(pdev) {
538 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
539 struct resource *rp = &pdev->resource[i];
540 int flags = rp->flags;
541
542 /* Active and same type? */
543 if ((flags & IORESOURCE_MEM) == 0)
544 continue;
545 /* In the range of this resource? */
546 if (offset < (rp->start & PAGE_MASK) ||
547 offset > rp->end)
548 continue;
549 found = rp;
550 break;
551 }
552 if (found)
553 break;
554 }
555 if (found) {
556 if (found->flags & IORESOURCE_PREFETCH)
557 prot = pgprot_noncached_wc(prot);
558 pci_dev_put(pdev);
559 }
560
561 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
562 (unsigned long long)offset, pgprot_val(prot));
563
564 return prot;
565}
566
567/* This provides legacy IO read access on a bus */
568int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
569{
570 unsigned long offset;
571 struct pci_controller *hose = pci_bus_to_host(bus);
572 struct resource *rp = &hose->io_resource;
573 void __iomem *addr;
574
575 /* Check if port can be supported by that bus. We only check
576 * the ranges of the PHB though, not the bus itself as the rules
577 * for forwarding legacy cycles down bridges are not our problem
578 * here. So if the host bridge supports it, we do it.
579 */
580 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
581 offset += port;
582
583 if (!(rp->flags & IORESOURCE_IO))
584 return -ENXIO;
585 if (offset < rp->start || (offset + size) > rp->end)
586 return -ENXIO;
587 addr = hose->io_base_virt + port;
588
589 switch(size) {
590 case 1:
591 *((u8 *)val) = in_8(addr);
592 return 1;
593 case 2:
594 if (port & 1)
595 return -EINVAL;
596 *((u16 *)val) = in_le16(addr);
597 return 2;
598 case 4:
599 if (port & 3)
600 return -EINVAL;
601 *((u32 *)val) = in_le32(addr);
602 return 4;
603 }
604 return -EINVAL;
605}
606
607/* This provides legacy IO write access on a bus */
608int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
609{
610 unsigned long offset;
611 struct pci_controller *hose = pci_bus_to_host(bus);
612 struct resource *rp = &hose->io_resource;
613 void __iomem *addr;
614
615 /* Check if port can be supported by that bus. We only check
616 * the ranges of the PHB though, not the bus itself as the rules
617 * for forwarding legacy cycles down bridges are not our problem
618 * here. So if the host bridge supports it, we do it.
619 */
620 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
621 offset += port;
622
623 if (!(rp->flags & IORESOURCE_IO))
624 return -ENXIO;
625 if (offset < rp->start || (offset + size) > rp->end)
626 return -ENXIO;
627 addr = hose->io_base_virt + port;
628
629 switch(size) {
630 case 1:
631 out_8(addr, val);
632 return 1;
633 case 2:
634 if (port & 1)
635 return -EINVAL;
636 out_le16(addr, val);
637 return 2;
638 case 4:
639 if (port & 3)
640 return -EINVAL;
641 out_le32(addr, val);
642 return 4;
643 }
644 return -EINVAL;
645}
646
647/* This provides legacy IO or memory mmap access on a bus */
648int pci_mmap_legacy_page_range(struct pci_bus *bus,
649 struct vm_area_struct *vma,
650 enum pci_mmap_state mmap_state)
651{
652 struct pci_controller *hose = pci_bus_to_host(bus);
653 resource_size_t offset =
654 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
655 resource_size_t size = vma->vm_end - vma->vm_start;
656 struct resource *rp;
657
658 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
659 pci_domain_nr(bus), bus->number,
660 mmap_state == pci_mmap_mem ? "MEM" : "IO",
661 (unsigned long long)offset,
662 (unsigned long long)(offset + size - 1));
663
664 if (mmap_state == pci_mmap_mem) {
665 /* Hack alert !
666 *
667 * Because X is lame and can fail starting if it gets an error trying
668 * to mmap legacy_mem (instead of just moving on without legacy memory
669 * access) we fake it here by giving it anonymous memory, effectively
670 * behaving just like /dev/zero
671 */
672 if ((offset + size) > hose->isa_mem_size) {
673 printk(KERN_DEBUG
674 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
675 current->comm, current->pid, pci_domain_nr(bus), bus->number);
676 if (vma->vm_flags & VM_SHARED)
677 return shmem_zero_setup(vma);
678 return 0;
679 }
680 offset += hose->isa_mem_phys;
681 } else {
682 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
683 unsigned long roffset = offset + io_offset;
684 rp = &hose->io_resource;
685 if (!(rp->flags & IORESOURCE_IO))
686 return -ENXIO;
687 if (roffset < rp->start || (roffset + size) > rp->end)
688 return -ENXIO;
689 offset += hose->io_base_phys;
690 }
691 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
692
693 vma->vm_pgoff = offset >> PAGE_SHIFT;
694 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
695 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
696 vma->vm_end - vma->vm_start,
697 vma->vm_page_prot);
698}
699
700void pci_resource_to_user(const struct pci_dev *dev, int bar,
701 const struct resource *rsrc,
702 resource_size_t *start, resource_size_t *end)
703{
704 struct pci_bus_region region;
705
706 if (rsrc->flags & IORESOURCE_IO) {
707 pcibios_resource_to_bus(dev->bus, &region,
708 (struct resource *) rsrc);
709 *start = region.start;
710 *end = region.end;
711 return;
712 }
713
714 /* We pass a CPU physical address to userland for MMIO instead of a
715 * BAR value because X is lame and expects to be able to use that
716 * to pass to /dev/mem!
717 *
718 * That means we may have 64-bit values where some apps only expect
719 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
720 */
721 *start = rsrc->start;
722 *end = rsrc->end;
723}
724
725/**
726 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
727 * @hose: newly allocated pci_controller to be setup
728 * @dev: device node of the host bridge
729 * @primary: set if primary bus (32 bits only, soon to be deprecated)
730 *
731 * This function will parse the "ranges" property of a PCI host bridge device
732 * node and setup the resource mapping of a pci controller based on its
733 * content.
734 *
735 * Life would be boring if it wasn't for a few issues that we have to deal
736 * with here:
737 *
738 * - We can only cope with one IO space range and up to 3 Memory space
739 * ranges. However, some machines (thanks Apple !) tend to split their
740 * space into lots of small contiguous ranges. So we have to coalesce.
741 *
742 * - Some busses have IO space not starting at 0, which causes trouble with
743 * the way we do our IO resource renumbering. The code somewhat deals with
744 * it for 64 bits but I would expect problems on 32 bits.
745 *
746 * - Some 32 bits platforms such as 4xx can have physical space larger than
747 * 32 bits so we need to use 64 bits values for the parsing
748 */
749void pci_process_bridge_OF_ranges(struct pci_controller *hose,
750 struct device_node *dev, int primary)
751{
752 int memno = 0;
753 struct resource *res;
754 struct of_pci_range range;
755 struct of_pci_range_parser parser;
756
757 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
758 dev, primary ? "(primary)" : "");
759
760 /* Check for ranges property */
761 if (of_pci_range_parser_init(&parser, dev))
762 return;
763
764 /* Parse it */
765 for_each_of_pci_range(&parser, &range) {
766 /* If we failed translation or got a zero-sized region
767 * (some FW try to feed us with non sensical zero sized regions
768 * such as power3 which look like some kind of attempt at exposing
769 * the VGA memory hole)
770 */
771 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
772 continue;
773
774 /* Act based on address space type */
775 res = NULL;
776 switch (range.flags & IORESOURCE_TYPE_BITS) {
777 case IORESOURCE_IO:
778 printk(KERN_INFO
779 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
780 range.cpu_addr, range.cpu_addr + range.size - 1,
781 range.pci_addr);
782
783 /* We support only one IO range */
784 if (hose->pci_io_size) {
785 printk(KERN_INFO
786 " \\--> Skipped (too many) !\n");
787 continue;
788 }
789#ifdef CONFIG_PPC32
790 /* On 32 bits, limit I/O space to 16MB */
791 if (range.size > 0x01000000)
792 range.size = 0x01000000;
793
794 /* 32 bits needs to map IOs here */
795 hose->io_base_virt = ioremap(range.cpu_addr,
796 range.size);
797
798 /* Expect trouble if pci_addr is not 0 */
799 if (primary)
800 isa_io_base =
801 (unsigned long)hose->io_base_virt;
802#endif /* CONFIG_PPC32 */
803 /* pci_io_size and io_base_phys always represent IO
804 * space starting at 0 so we factor in pci_addr
805 */
806 hose->pci_io_size = range.pci_addr + range.size;
807 hose->io_base_phys = range.cpu_addr - range.pci_addr;
808
809 /* Build resource */
810 res = &hose->io_resource;
811 range.cpu_addr = range.pci_addr;
812 break;
813 case IORESOURCE_MEM:
814 printk(KERN_INFO
815 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
816 range.cpu_addr, range.cpu_addr + range.size - 1,
817 range.pci_addr,
818 (range.flags & IORESOURCE_PREFETCH) ?
819 "Prefetch" : "");
820
821 /* We support only 3 memory ranges */
822 if (memno >= 3) {
823 printk(KERN_INFO
824 " \\--> Skipped (too many) !\n");
825 continue;
826 }
827 /* Handles ISA memory hole space here */
828 if (range.pci_addr == 0) {
829 if (primary || isa_mem_base == 0)
830 isa_mem_base = range.cpu_addr;
831 hose->isa_mem_phys = range.cpu_addr;
832 hose->isa_mem_size = range.size;
833 }
834
835 /* Build resource */
836 hose->mem_offset[memno] = range.cpu_addr -
837 range.pci_addr;
838 res = &hose->mem_resources[memno++];
839 break;
840 }
841 if (res != NULL) {
842 res->name = dev->full_name;
843 res->flags = range.flags;
844 res->start = range.cpu_addr;
845 res->end = range.cpu_addr + range.size - 1;
846 res->parent = res->child = res->sibling = NULL;
847 }
848 }
849}
850
851/* Decide whether to display the domain number in /proc */
852int pci_proc_domain(struct pci_bus *bus)
853{
854 struct pci_controller *hose = pci_bus_to_host(bus);
855
856 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
857 return 0;
858 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
859 return hose->global_number != 0;
860 return 1;
861}
862
863int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
864{
865 if (ppc_md.pcibios_root_bridge_prepare)
866 return ppc_md.pcibios_root_bridge_prepare(bridge);
867
868 return 0;
869}
870
871/* This header fixup will do the resource fixup for all devices as they are
872 * probed, but not for bridge ranges
873 */
874static void pcibios_fixup_resources(struct pci_dev *dev)
875{
876 struct pci_controller *hose = pci_bus_to_host(dev->bus);
877 struct resource *res;
878 int i;
879
880 if (!hose) {
881 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
882 pci_name(dev));
883 return;
884 }
885
886 if (dev->is_virtfn)
887 return;
888
889 pci_dev_for_each_resource(dev, res, i) {
890 struct pci_bus_region reg;
891
892 if (!res->flags)
893 continue;
894
895 /* If we're going to re-assign everything, we mark all resources
896 * as unset (and 0-base them). In addition, we mark BARs starting
897 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
898 * since in that case, we don't want to re-assign anything
899 */
900 pcibios_resource_to_bus(dev->bus, &reg, res);
901 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
902 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
903 /* Only print message if not re-assigning */
904 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
905 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
906 pci_name(dev), i, res);
907 res->end -= res->start;
908 res->start = 0;
909 res->flags |= IORESOURCE_UNSET;
910 continue;
911 }
912
913 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
914 }
915
916 /* Call machine specific resource fixup */
917 if (ppc_md.pcibios_fixup_resources)
918 ppc_md.pcibios_fixup_resources(dev);
919}
920DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
921
922/* This function tries to figure out if a bridge resource has been initialized
923 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
924 * things go more smoothly when it gets it right. It should covers cases such
925 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
926 */
927static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
928 struct resource *res)
929{
930 struct pci_controller *hose = pci_bus_to_host(bus);
931 struct pci_dev *dev = bus->self;
932 resource_size_t offset;
933 struct pci_bus_region region;
934 u16 command;
935 int i;
936
937 /* We don't do anything if PCI_PROBE_ONLY is set */
938 if (pci_has_flag(PCI_PROBE_ONLY))
939 return 0;
940
941 /* Job is a bit different between memory and IO */
942 if (res->flags & IORESOURCE_MEM) {
943 pcibios_resource_to_bus(dev->bus, &region, res);
944
945 /* If the BAR is non-0 then it's probably been initialized */
946 if (region.start != 0)
947 return 0;
948
949 /* The BAR is 0, let's check if memory decoding is enabled on
950 * the bridge. If not, we consider it unassigned
951 */
952 pci_read_config_word(dev, PCI_COMMAND, &command);
953 if ((command & PCI_COMMAND_MEMORY) == 0)
954 return 1;
955
956 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
957 * resources covers that starting address (0 then it's good enough for
958 * us for memory space)
959 */
960 for (i = 0; i < 3; i++) {
961 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
962 hose->mem_resources[i].start == hose->mem_offset[i])
963 return 0;
964 }
965
966 /* Well, it starts at 0 and we know it will collide so we may as
967 * well consider it as unassigned. That covers the Apple case.
968 */
969 return 1;
970 } else {
971 /* If the BAR is non-0, then we consider it assigned */
972 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
973 if (((res->start - offset) & 0xfffffffful) != 0)
974 return 0;
975
976 /* Here, we are a bit different than memory as typically IO space
977 * starting at low addresses -is- valid. What we do instead if that
978 * we consider as unassigned anything that doesn't have IO enabled
979 * in the PCI command register, and that's it.
980 */
981 pci_read_config_word(dev, PCI_COMMAND, &command);
982 if (command & PCI_COMMAND_IO)
983 return 0;
984
985 /* It's starting at 0 and IO is disabled in the bridge, consider
986 * it unassigned
987 */
988 return 1;
989 }
990}
991
992/* Fixup resources of a PCI<->PCI bridge */
993static void pcibios_fixup_bridge(struct pci_bus *bus)
994{
995 struct resource *res;
996 int i;
997
998 struct pci_dev *dev = bus->self;
999
1000 pci_bus_for_each_resource(bus, res, i) {
1001 if (!res || !res->flags)
1002 continue;
1003 if (i >= 3 && bus->self->transparent)
1004 continue;
1005
1006 /* If we're going to reassign everything, we can
1007 * shrink the P2P resource to have size as being
1008 * of 0 in order to save space.
1009 */
1010 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1011 res->flags |= IORESOURCE_UNSET;
1012 res->start = 0;
1013 res->end = -1;
1014 continue;
1015 }
1016
1017 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
1018
1019 /* Try to detect uninitialized P2P bridge resources,
1020 * and clear them out so they get re-assigned later
1021 */
1022 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1023 res->flags = 0;
1024 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1025 }
1026 }
1027}
1028
1029void pcibios_setup_bus_self(struct pci_bus *bus)
1030{
1031 struct pci_controller *phb;
1032
1033 /* Fix up the bus resources for P2P bridges */
1034 if (bus->self != NULL)
1035 pcibios_fixup_bridge(bus);
1036
1037 /* Platform specific bus fixups. This is currently only used
1038 * by fsl_pci and I'm hoping to get rid of it at some point
1039 */
1040 if (ppc_md.pcibios_fixup_bus)
1041 ppc_md.pcibios_fixup_bus(bus);
1042
1043 /* Setup bus DMA mappings */
1044 phb = pci_bus_to_host(bus);
1045 if (phb->controller_ops.dma_bus_setup)
1046 phb->controller_ops.dma_bus_setup(bus);
1047}
1048
1049void pcibios_bus_add_device(struct pci_dev *dev)
1050{
1051 struct pci_controller *phb;
1052 /* Fixup NUMA node as it may not be setup yet by the generic
1053 * code and is needed by the DMA init
1054 */
1055 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1056
1057 /* Hook up default DMA ops */
1058 set_dma_ops(&dev->dev, pci_dma_ops);
1059 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
1060
1061 /* Additional platform DMA/iommu setup */
1062 phb = pci_bus_to_host(dev->bus);
1063 if (phb->controller_ops.dma_dev_setup)
1064 phb->controller_ops.dma_dev_setup(dev);
1065
1066 /* Read default IRQs and fixup if necessary */
1067 pci_read_irq_line(dev);
1068 if (ppc_md.pci_irq_fixup)
1069 ppc_md.pci_irq_fixup(dev);
1070
1071 if (ppc_md.pcibios_bus_add_device)
1072 ppc_md.pcibios_bus_add_device(dev);
1073}
1074
1075int pcibios_device_add(struct pci_dev *dev)
1076{
1077 struct irq_domain *d;
1078
1079#ifdef CONFIG_PCI_IOV
1080 if (ppc_md.pcibios_fixup_sriov)
1081 ppc_md.pcibios_fixup_sriov(dev);
1082#endif /* CONFIG_PCI_IOV */
1083
1084 d = dev_get_msi_domain(&dev->bus->dev);
1085 if (d)
1086 dev_set_msi_domain(&dev->dev, d);
1087 return 0;
1088}
1089
1090void pcibios_set_master(struct pci_dev *dev)
1091{
1092 /* No special bus mastering setup handling */
1093}
1094
1095void pcibios_fixup_bus(struct pci_bus *bus)
1096{
1097 /* When called from the generic PCI probe, read PCI<->PCI bridge
1098 * bases. This is -not- called when generating the PCI tree from
1099 * the OF device-tree.
1100 */
1101 pci_read_bridge_bases(bus);
1102
1103 /* Now fixup the bus */
1104 pcibios_setup_bus_self(bus);
1105}
1106EXPORT_SYMBOL(pcibios_fixup_bus);
1107
1108static int skip_isa_ioresource_align(struct pci_dev *dev)
1109{
1110 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1111 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1112 return 1;
1113 return 0;
1114}
1115
1116/*
1117 * We need to avoid collisions with `mirrored' VGA ports
1118 * and other strange ISA hardware, so we always want the
1119 * addresses to be allocated in the 0x000-0x0ff region
1120 * modulo 0x400.
1121 *
1122 * Why? Because some silly external IO cards only decode
1123 * the low 10 bits of the IO address. The 0x00-0xff region
1124 * is reserved for motherboard devices that decode all 16
1125 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1126 * but we want to try to avoid allocating at 0x2900-0x2bff
1127 * which might have be mirrored at 0x0100-0x03ff..
1128 */
1129resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1130 const struct resource *empty_res,
1131 resource_size_t size,
1132 resource_size_t align)
1133{
1134 struct pci_dev *dev = data;
1135 resource_size_t start = res->start;
1136
1137 if (res->flags & IORESOURCE_IO) {
1138 if (skip_isa_ioresource_align(dev))
1139 return start;
1140 if (start & 0x300)
1141 start = (start + 0x3ff) & ~0x3ff;
1142 } else if (res->flags & IORESOURCE_MEM) {
1143 start = pci_align_resource(dev, res, empty_res, size, align);
1144 }
1145
1146 return start;
1147}
1148EXPORT_SYMBOL(pcibios_align_resource);
1149
1150/*
1151 * Reparent resource children of pr that conflict with res
1152 * under res, and make res replace those children.
1153 */
1154static int reparent_resources(struct resource *parent,
1155 struct resource *res)
1156{
1157 struct resource *p, **pp;
1158 struct resource **firstpp = NULL;
1159
1160 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1161 if (p->end < res->start)
1162 continue;
1163 if (res->end < p->start)
1164 break;
1165 if (p->start < res->start || p->end > res->end)
1166 return -1; /* not completely contained */
1167 if (firstpp == NULL)
1168 firstpp = pp;
1169 }
1170 if (firstpp == NULL)
1171 return -1; /* didn't find any conflicting entries? */
1172 res->parent = parent;
1173 res->child = *firstpp;
1174 res->sibling = *pp;
1175 *firstpp = res;
1176 *pp = NULL;
1177 for (p = res->child; p != NULL; p = p->sibling) {
1178 p->parent = res;
1179 pr_debug("PCI: Reparented %s %pR under %s\n",
1180 p->name, p, res->name);
1181 }
1182 return 0;
1183}
1184
1185/*
1186 * Handle resources of PCI devices. If the world were perfect, we could
1187 * just allocate all the resource regions and do nothing more. It isn't.
1188 * On the other hand, we cannot just re-allocate all devices, as it would
1189 * require us to know lots of host bridge internals. So we attempt to
1190 * keep as much of the original configuration as possible, but tweak it
1191 * when it's found to be wrong.
1192 *
1193 * Known BIOS problems we have to work around:
1194 * - I/O or memory regions not configured
1195 * - regions configured, but not enabled in the command register
1196 * - bogus I/O addresses above 64K used
1197 * - expansion ROMs left enabled (this may sound harmless, but given
1198 * the fact the PCI specs explicitly allow address decoders to be
1199 * shared between expansion ROMs and other resource regions, it's
1200 * at least dangerous)
1201 *
1202 * Our solution:
1203 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1204 * This gives us fixed barriers on where we can allocate.
1205 * (2) Allocate resources for all enabled devices. If there is
1206 * a collision, just mark the resource as unallocated. Also
1207 * disable expansion ROMs during this step.
1208 * (3) Try to allocate resources for disabled devices. If the
1209 * resources were assigned correctly, everything goes well,
1210 * if they weren't, they won't disturb allocation of other
1211 * resources.
1212 * (4) Assign new addresses to resources which were either
1213 * not configured at all or misconfigured. If explicitly
1214 * requested by the user, configure expansion ROM address
1215 * as well.
1216 */
1217
1218static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1219{
1220 struct pci_bus *b;
1221 int i;
1222 struct resource *res, *pr;
1223
1224 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1225 pci_domain_nr(bus), bus->number);
1226
1227 pci_bus_for_each_resource(bus, res, i) {
1228 if (!res || !res->flags || res->start > res->end || res->parent)
1229 continue;
1230
1231 /* If the resource was left unset at this point, we clear it */
1232 if (res->flags & IORESOURCE_UNSET)
1233 goto clear_resource;
1234
1235 if (bus->parent == NULL)
1236 pr = (res->flags & IORESOURCE_IO) ?
1237 &ioport_resource : &iomem_resource;
1238 else {
1239 pr = pci_find_parent_resource(bus->self, res);
1240 if (pr == res) {
1241 /* this happens when the generic PCI
1242 * code (wrongly) decides that this
1243 * bridge is transparent -- paulus
1244 */
1245 continue;
1246 }
1247 }
1248
1249 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1250 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1251 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1252
1253 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1254 struct pci_dev *dev = bus->self;
1255
1256 if (request_resource(pr, res) == 0)
1257 continue;
1258 /*
1259 * Must be a conflict with an existing entry.
1260 * Move that entry (or entries) under the
1261 * bridge resource and try again.
1262 */
1263 if (reparent_resources(pr, res) == 0)
1264 continue;
1265
1266 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1267 pci_claim_bridge_resource(dev,
1268 i + PCI_BRIDGE_RESOURCES) == 0)
1269 continue;
1270 }
1271 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1272 i, bus->number);
1273 clear_resource:
1274 /* The resource might be figured out when doing
1275 * reassignment based on the resources required
1276 * by the downstream PCI devices. Here we set
1277 * the size of the resource to be 0 in order to
1278 * save more space.
1279 */
1280 res->start = 0;
1281 res->end = -1;
1282 res->flags = 0;
1283 }
1284
1285 list_for_each_entry(b, &bus->children, node)
1286 pcibios_allocate_bus_resources(b);
1287}
1288
1289static inline void alloc_resource(struct pci_dev *dev, int idx)
1290{
1291 struct resource *pr, *r = &dev->resource[idx];
1292
1293 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1294 pci_name(dev), idx, r);
1295
1296 pr = pci_find_parent_resource(dev, r);
1297 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1298 request_resource(pr, r) < 0) {
1299 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1300 " of device %s, will remap\n", idx, pci_name(dev));
1301 if (pr)
1302 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1303 /* We'll assign a new address later */
1304 r->flags |= IORESOURCE_UNSET;
1305 r->end -= r->start;
1306 r->start = 0;
1307 }
1308}
1309
1310static void __init pcibios_allocate_resources(int pass)
1311{
1312 struct pci_dev *dev = NULL;
1313 int idx, disabled;
1314 u16 command;
1315 struct resource *r;
1316
1317 for_each_pci_dev(dev) {
1318 pci_read_config_word(dev, PCI_COMMAND, &command);
1319 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1320 r = &dev->resource[idx];
1321 if (r->parent) /* Already allocated */
1322 continue;
1323 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1324 continue; /* Not assigned at all */
1325 /* We only allocate ROMs on pass 1 just in case they
1326 * have been screwed up by firmware
1327 */
1328 if (idx == PCI_ROM_RESOURCE )
1329 disabled = 1;
1330 if (r->flags & IORESOURCE_IO)
1331 disabled = !(command & PCI_COMMAND_IO);
1332 else
1333 disabled = !(command & PCI_COMMAND_MEMORY);
1334 if (pass == disabled)
1335 alloc_resource(dev, idx);
1336 }
1337 if (pass)
1338 continue;
1339 r = &dev->resource[PCI_ROM_RESOURCE];
1340 if (r->flags) {
1341 /* Turn the ROM off, leave the resource region,
1342 * but keep it unregistered.
1343 */
1344 u32 reg;
1345 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
1346 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1347 pr_debug("PCI: Switching off ROM of %s\n",
1348 pci_name(dev));
1349 r->flags &= ~IORESOURCE_ROM_ENABLE;
1350 pci_write_config_dword(dev, dev->rom_base_reg,
1351 reg & ~PCI_ROM_ADDRESS_ENABLE);
1352 }
1353 }
1354 }
1355}
1356
1357static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1358{
1359 struct pci_controller *hose = pci_bus_to_host(bus);
1360 resource_size_t offset;
1361 struct resource *res, *pres;
1362 int i;
1363
1364 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1365
1366 /* Check for IO */
1367 if (!(hose->io_resource.flags & IORESOURCE_IO))
1368 goto no_io;
1369 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1370 res = kzalloc_obj(struct resource);
1371 BUG_ON(res == NULL);
1372 res->name = "Legacy IO";
1373 res->flags = IORESOURCE_IO;
1374 res->start = offset;
1375 res->end = (offset + 0xfff) & 0xfffffffful;
1376 pr_debug("Candidate legacy IO: %pR\n", res);
1377 if (request_resource(&hose->io_resource, res)) {
1378 printk(KERN_DEBUG
1379 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1380 pci_domain_nr(bus), bus->number, res);
1381 kfree(res);
1382 }
1383
1384 no_io:
1385 /* Check for memory */
1386 for (i = 0; i < 3; i++) {
1387 pres = &hose->mem_resources[i];
1388 offset = hose->mem_offset[i];
1389 if (!(pres->flags & IORESOURCE_MEM))
1390 continue;
1391 pr_debug("hose mem res: %pR\n", pres);
1392 if ((pres->start - offset) <= 0xa0000 &&
1393 (pres->end - offset) >= 0xbffff)
1394 break;
1395 }
1396 if (i >= 3)
1397 return;
1398 res = kzalloc_obj(struct resource);
1399 BUG_ON(res == NULL);
1400 res->name = "Legacy VGA memory";
1401 res->flags = IORESOURCE_MEM;
1402 res->start = 0xa0000 + offset;
1403 res->end = 0xbffff + offset;
1404 pr_debug("Candidate VGA memory: %pR\n", res);
1405 if (request_resource(pres, res)) {
1406 printk(KERN_DEBUG
1407 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1408 pci_domain_nr(bus), bus->number, res);
1409 kfree(res);
1410 }
1411}
1412
1413void __init pcibios_resource_survey(void)
1414{
1415 struct pci_bus *b;
1416
1417 /* Allocate and assign resources */
1418 list_for_each_entry(b, &pci_root_buses, node)
1419 pcibios_allocate_bus_resources(b);
1420 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1421 pcibios_allocate_resources(0);
1422 pcibios_allocate_resources(1);
1423 }
1424
1425 /* Before we start assigning unassigned resource, we try to reserve
1426 * the low IO area and the VGA memory area if they intersect the
1427 * bus available resources to avoid allocating things on top of them
1428 */
1429 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1430 list_for_each_entry(b, &pci_root_buses, node)
1431 pcibios_reserve_legacy_regions(b);
1432 }
1433
1434 /* Now, if the platform didn't decide to blindly trust the firmware,
1435 * we proceed to assigning things that were left unassigned
1436 */
1437 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1438 pr_debug("PCI: Assigning unassigned resources...\n");
1439 pci_assign_unassigned_resources();
1440 }
1441}
1442
1443/* This is used by the PCI hotplug driver to allocate resource
1444 * of newly plugged busses. We can try to consolidate with the
1445 * rest of the code later, for now, keep it as-is as our main
1446 * resource allocation function doesn't deal with sub-trees yet.
1447 */
1448void pcibios_claim_one_bus(struct pci_bus *bus)
1449{
1450 struct pci_dev *dev;
1451 struct pci_bus *child_bus;
1452
1453 list_for_each_entry(dev, &bus->devices, bus_list) {
1454 struct resource *r;
1455 int i;
1456
1457 pci_dev_for_each_resource(dev, r, i) {
1458 if (r->parent || !r->start || !r->flags)
1459 continue;
1460
1461 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1462 pci_name(dev), i, r);
1463
1464 if (pci_claim_resource(dev, i) == 0)
1465 continue;
1466
1467 pci_claim_bridge_resource(dev, i);
1468 }
1469 }
1470
1471 list_for_each_entry(child_bus, &bus->children, node)
1472 pcibios_claim_one_bus(child_bus);
1473}
1474EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1475
1476
1477/* pcibios_finish_adding_to_bus
1478 *
1479 * This is to be called by the hotplug code after devices have been
1480 * added to a bus, this include calling it for a PHB that is just
1481 * being added
1482 */
1483void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1484{
1485 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1486 pci_domain_nr(bus), bus->number);
1487
1488 /* Allocate bus and devices resources */
1489 pcibios_allocate_bus_resources(bus);
1490 pcibios_claim_one_bus(bus);
1491 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1492 if (bus->self)
1493 pci_assign_unassigned_bridge_resources(bus->self);
1494 else
1495 pci_assign_unassigned_bus_resources(bus);
1496 }
1497
1498 /* Add new devices to global lists. Register in proc, sysfs. */
1499 pci_bus_add_devices(bus);
1500}
1501EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1502
1503int pcibios_enable_device(struct pci_dev *dev, int mask)
1504{
1505 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1506
1507 if (phb->controller_ops.enable_device_hook)
1508 if (!phb->controller_ops.enable_device_hook(dev))
1509 return -EINVAL;
1510
1511 return pci_enable_resources(dev, mask);
1512}
1513
1514void pcibios_disable_device(struct pci_dev *dev)
1515{
1516 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1517
1518 if (phb->controller_ops.disable_device)
1519 phb->controller_ops.disable_device(dev);
1520}
1521
1522resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1523{
1524 return (unsigned long) hose->io_base_virt - _IO_BASE;
1525}
1526
1527static void pcibios_setup_phb_resources(struct pci_controller *hose,
1528 struct list_head *resources)
1529{
1530 struct resource *res;
1531 resource_size_t offset;
1532 int i;
1533
1534 /* Hookup PHB IO resource */
1535 res = &hose->io_resource;
1536
1537 if (!res->flags) {
1538 pr_debug("PCI: I/O resource not set for host"
1539 " bridge %pOF (domain %d)\n",
1540 hose->dn, hose->global_number);
1541 } else {
1542 offset = pcibios_io_space_offset(hose);
1543
1544 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1545 res, (unsigned long long)offset);
1546 pci_add_resource_offset(resources, res, offset);
1547 }
1548
1549 /* Hookup PHB Memory resources */
1550 for (i = 0; i < 3; ++i) {
1551 res = &hose->mem_resources[i];
1552 if (!res->flags)
1553 continue;
1554
1555 offset = hose->mem_offset[i];
1556 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1557 res, (unsigned long long)offset);
1558
1559 pci_add_resource_offset(resources, res, offset);
1560 }
1561}
1562
1563/*
1564 * Null PCI config access functions, for the case when we can't
1565 * find a hose.
1566 */
1567#define NULL_PCI_OP(rw, size, type) \
1568static int \
1569null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1570{ \
1571 return PCIBIOS_DEVICE_NOT_FOUND; \
1572}
1573
1574static int
1575null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1576 int len, u32 *val)
1577{
1578 return PCIBIOS_DEVICE_NOT_FOUND;
1579}
1580
1581static int
1582null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1583 int len, u32 val)
1584{
1585 return PCIBIOS_DEVICE_NOT_FOUND;
1586}
1587
1588static struct pci_ops null_pci_ops =
1589{
1590 .read = null_read_config,
1591 .write = null_write_config,
1592};
1593
1594/*
1595 * These functions are used early on before PCI scanning is done
1596 * and all of the pci_dev and pci_bus structures have been created.
1597 */
1598static struct pci_bus *
1599fake_pci_bus(struct pci_controller *hose, int busnr)
1600{
1601 static struct pci_bus bus;
1602
1603 if (hose == NULL) {
1604 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1605 }
1606 bus.number = busnr;
1607 bus.sysdata = hose;
1608 bus.ops = hose? hose->ops: &null_pci_ops;
1609 return &bus;
1610}
1611
1612#define EARLY_PCI_OP(rw, size, type) \
1613int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1614 int devfn, int offset, type value) \
1615{ \
1616 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1617 devfn, offset, value); \
1618}
1619
1620EARLY_PCI_OP(read, byte, u8 *)
1621EARLY_PCI_OP(read, word, u16 *)
1622EARLY_PCI_OP(read, dword, u32 *)
1623EARLY_PCI_OP(write, byte, u8)
1624EARLY_PCI_OP(write, word, u16)
1625EARLY_PCI_OP(write, dword, u32)
1626
1627int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1628 int cap)
1629{
1630 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1631}
1632
1633struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1634{
1635 struct pci_controller *hose = bus->sysdata;
1636
1637 return of_node_get(hose->dn);
1638}
1639
1640/**
1641 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1642 * @hose: Pointer to the PCI host controller instance structure
1643 */
1644void pcibios_scan_phb(struct pci_controller *hose)
1645{
1646 LIST_HEAD(resources);
1647 struct pci_bus *bus;
1648 struct device_node *node = hose->dn;
1649 int mode;
1650
1651 pr_debug("PCI: Scanning PHB %pOF\n", node);
1652
1653 /* Get some IO space for the new PHB */
1654 pcibios_setup_phb_io_space(hose);
1655
1656 /* Wire up PHB bus resources */
1657 pcibios_setup_phb_resources(hose, &resources);
1658
1659 hose->busn.start = hose->first_busno;
1660 hose->busn.end = hose->last_busno;
1661 hose->busn.flags = IORESOURCE_BUS;
1662 pci_add_resource(&resources, &hose->busn);
1663
1664 /* Create an empty bus for the toplevel */
1665 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1666 hose->ops, hose, &resources);
1667 if (bus == NULL) {
1668 pr_err("Failed to create bus for PCI domain %04x\n",
1669 hose->global_number);
1670 pci_free_resource_list(&resources);
1671 return;
1672 }
1673 hose->bus = bus;
1674
1675 /* Get probe mode and perform scan */
1676 mode = PCI_PROBE_NORMAL;
1677 if (node && hose->controller_ops.probe_mode)
1678 mode = hose->controller_ops.probe_mode(bus);
1679 pr_debug(" probe mode: %d\n", mode);
1680 if (mode == PCI_PROBE_DEVTREE)
1681 of_scan_bus(node, bus);
1682
1683 if (mode == PCI_PROBE_NORMAL) {
1684 pci_bus_update_busn_res_end(bus, 255);
1685 hose->last_busno = pci_scan_child_bus(bus);
1686 pci_bus_update_busn_res_end(bus, hose->last_busno);
1687 }
1688
1689 /* Platform gets a chance to do some global fixups before
1690 * we proceed to resource allocation
1691 */
1692 if (ppc_md.pcibios_fixup_phb)
1693 ppc_md.pcibios_fixup_phb(hose);
1694
1695 /* Configure PCI Express settings */
1696 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1697 struct pci_bus *child;
1698 list_for_each_entry(child, &bus->children, node)
1699 pcie_bus_configure_settings(child);
1700 }
1701}
1702EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1703
1704static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1705{
1706 int class = dev->class >> 8;
1707 /* When configured as agent, programming interface = 1 */
1708 int prog_if = dev->class & 0xf;
1709 struct resource *r;
1710
1711 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1712 class == PCI_CLASS_BRIDGE_OTHER) &&
1713 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1714 (prog_if == 0) &&
1715 (dev->bus->parent == NULL)) {
1716 pci_dev_for_each_resource(dev, r) {
1717 r->start = 0;
1718 r->end = 0;
1719 r->flags = 0;
1720 }
1721 }
1722}
1723DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1724DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1725
1726
1727static int __init discover_phbs(void)
1728{
1729 if (ppc_md.discover_phbs)
1730 ppc_md.discover_phbs();
1731
1732 return 0;
1733}
1734core_initcall(discover_phbs);