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1/*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation being IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
13 * for more details.
14 */
15
16#undef DEBUG
17#undef DEBUG_IPI
18#undef DEBUG_IRQ
19#undef DEBUG_LOW
20
21#include <linux/types.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/irq.h>
25#include <linux/smp.h>
26#include <linux/interrupt.h>
27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/slab.h>
30#include <linux/string_choices.h>
31#include <linux/syscore_ops.h>
32#include <linux/ratelimit.h>
33#include <linux/pgtable.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
36
37#include <asm/ptrace.h>
38#include <asm/signal.h>
39#include <asm/io.h>
40#include <asm/irq.h>
41#include <asm/machdep.h>
42#include <asm/mpic.h>
43#include <asm/smp.h>
44
45#include "mpic.h"
46
47#ifdef DEBUG
48#define DBG(fmt...) printk(fmt)
49#else
50#define DBG(fmt...)
51#endif
52
53const struct bus_type mpic_subsys = {
54 .name = "mpic",
55 .dev_name = "mpic",
56};
57EXPORT_SYMBOL_GPL(mpic_subsys);
58
59static struct mpic *mpics;
60static struct mpic *mpic_primary;
61static DEFINE_RAW_SPINLOCK(mpic_lock);
62
63#ifdef CONFIG_PPC32 /* XXX for now */
64#ifdef CONFIG_IRQ_ALL_CPUS
65#define distribute_irqs (1)
66#else
67#define distribute_irqs (0)
68#endif
69#endif
70
71#ifdef CONFIG_MPIC_WEIRD
72static u32 mpic_infos[][MPIC_IDX_END] = {
73 [0] = { /* Original OpenPIC compatible MPIC */
74 MPIC_GREG_BASE,
75 MPIC_GREG_FEATURE_0,
76 MPIC_GREG_GLOBAL_CONF_0,
77 MPIC_GREG_VENDOR_ID,
78 MPIC_GREG_IPI_VECTOR_PRI_0,
79 MPIC_GREG_IPI_STRIDE,
80 MPIC_GREG_SPURIOUS,
81 MPIC_GREG_TIMER_FREQ,
82
83 MPIC_TIMER_BASE,
84 MPIC_TIMER_STRIDE,
85 MPIC_TIMER_CURRENT_CNT,
86 MPIC_TIMER_BASE_CNT,
87 MPIC_TIMER_VECTOR_PRI,
88 MPIC_TIMER_DESTINATION,
89
90 MPIC_CPU_BASE,
91 MPIC_CPU_STRIDE,
92 MPIC_CPU_IPI_DISPATCH_0,
93 MPIC_CPU_IPI_DISPATCH_STRIDE,
94 MPIC_CPU_CURRENT_TASK_PRI,
95 MPIC_CPU_WHOAMI,
96 MPIC_CPU_INTACK,
97 MPIC_CPU_EOI,
98 MPIC_CPU_MCACK,
99
100 MPIC_IRQ_BASE,
101 MPIC_IRQ_STRIDE,
102 MPIC_IRQ_VECTOR_PRI,
103 MPIC_VECPRI_VECTOR_MASK,
104 MPIC_VECPRI_POLARITY_POSITIVE,
105 MPIC_VECPRI_POLARITY_NEGATIVE,
106 MPIC_VECPRI_SENSE_LEVEL,
107 MPIC_VECPRI_SENSE_EDGE,
108 MPIC_VECPRI_POLARITY_MASK,
109 MPIC_VECPRI_SENSE_MASK,
110 MPIC_IRQ_DESTINATION
111 },
112 [1] = { /* Tsi108/109 PIC */
113 TSI108_GREG_BASE,
114 TSI108_GREG_FEATURE_0,
115 TSI108_GREG_GLOBAL_CONF_0,
116 TSI108_GREG_VENDOR_ID,
117 TSI108_GREG_IPI_VECTOR_PRI_0,
118 TSI108_GREG_IPI_STRIDE,
119 TSI108_GREG_SPURIOUS,
120 TSI108_GREG_TIMER_FREQ,
121
122 TSI108_TIMER_BASE,
123 TSI108_TIMER_STRIDE,
124 TSI108_TIMER_CURRENT_CNT,
125 TSI108_TIMER_BASE_CNT,
126 TSI108_TIMER_VECTOR_PRI,
127 TSI108_TIMER_DESTINATION,
128
129 TSI108_CPU_BASE,
130 TSI108_CPU_STRIDE,
131 TSI108_CPU_IPI_DISPATCH_0,
132 TSI108_CPU_IPI_DISPATCH_STRIDE,
133 TSI108_CPU_CURRENT_TASK_PRI,
134 TSI108_CPU_WHOAMI,
135 TSI108_CPU_INTACK,
136 TSI108_CPU_EOI,
137 TSI108_CPU_MCACK,
138
139 TSI108_IRQ_BASE,
140 TSI108_IRQ_STRIDE,
141 TSI108_IRQ_VECTOR_PRI,
142 TSI108_VECPRI_VECTOR_MASK,
143 TSI108_VECPRI_POLARITY_POSITIVE,
144 TSI108_VECPRI_POLARITY_NEGATIVE,
145 TSI108_VECPRI_SENSE_LEVEL,
146 TSI108_VECPRI_SENSE_EDGE,
147 TSI108_VECPRI_POLARITY_MASK,
148 TSI108_VECPRI_SENSE_MASK,
149 TSI108_IRQ_DESTINATION
150 },
151};
152
153#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
154
155#else /* CONFIG_MPIC_WEIRD */
156
157#define MPIC_INFO(name) MPIC_##name
158
159#endif /* CONFIG_MPIC_WEIRD */
160
161static inline unsigned int mpic_processor_id(struct mpic *mpic)
162{
163 unsigned int cpu = 0;
164
165 if (!(mpic->flags & MPIC_SECONDARY))
166 cpu = hard_smp_processor_id();
167
168 return cpu;
169}
170
171/*
172 * Register accessor functions
173 */
174
175
176static inline u32 _mpic_read(enum mpic_reg_type type,
177 struct mpic_reg_bank *rb,
178 unsigned int reg)
179{
180 switch(type) {
181#ifdef CONFIG_PPC_DCR
182 case mpic_access_dcr:
183 return dcr_read(rb->dhost, reg);
184#endif
185 case mpic_access_mmio_be:
186 return in_be32(rb->base + (reg >> 2));
187 case mpic_access_mmio_le:
188 default:
189 return in_le32(rb->base + (reg >> 2));
190 }
191}
192
193static inline void _mpic_write(enum mpic_reg_type type,
194 struct mpic_reg_bank *rb,
195 unsigned int reg, u32 value)
196{
197 switch(type) {
198#ifdef CONFIG_PPC_DCR
199 case mpic_access_dcr:
200 dcr_write(rb->dhost, reg, value);
201 break;
202#endif
203 case mpic_access_mmio_be:
204 out_be32(rb->base + (reg >> 2), value);
205 break;
206 case mpic_access_mmio_le:
207 default:
208 out_le32(rb->base + (reg >> 2), value);
209 break;
210 }
211}
212
213static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
214{
215 enum mpic_reg_type type = mpic->reg_type;
216 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
217 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
218
219 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
220 type = mpic_access_mmio_be;
221 return _mpic_read(type, &mpic->gregs, offset);
222}
223
224static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
225{
226 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
227 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
228
229 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
230}
231
232static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
233{
234 return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
235 (tm & 3) * MPIC_INFO(TIMER_STRIDE);
236}
237
238static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
239{
240 unsigned int offset = mpic_tm_offset(mpic, tm) +
241 MPIC_INFO(TIMER_VECTOR_PRI);
242
243 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
244}
245
246static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
247{
248 unsigned int offset = mpic_tm_offset(mpic, tm) +
249 MPIC_INFO(TIMER_VECTOR_PRI);
250
251 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
252}
253
254static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
255{
256 unsigned int cpu = mpic_processor_id(mpic);
257
258 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
259}
260
261static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
262{
263 unsigned int cpu = mpic_processor_id(mpic);
264
265 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
266}
267
268static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
269{
270 unsigned int isu = src_no >> mpic->isu_shift;
271 unsigned int idx = src_no & mpic->isu_mask;
272 unsigned int val;
273
274 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
275 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
276#ifdef CONFIG_MPIC_BROKEN_REGREAD
277 if (reg == 0)
278 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
279 mpic->isu_reg0_shadow[src_no];
280#endif
281 return val;
282}
283
284static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
285 unsigned int reg, u32 value)
286{
287 unsigned int isu = src_no >> mpic->isu_shift;
288 unsigned int idx = src_no & mpic->isu_mask;
289
290 _mpic_write(mpic->reg_type, &mpic->isus[isu],
291 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
292
293#ifdef CONFIG_MPIC_BROKEN_REGREAD
294 if (reg == 0)
295 mpic->isu_reg0_shadow[src_no] =
296 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
297#endif
298}
299
300#define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
301#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
302#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
303#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
304#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
305#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
306#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
307#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
308#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
309#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
310
311
312/*
313 * Low level utility functions
314 */
315
316
317static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
318 struct mpic_reg_bank *rb, unsigned int offset,
319 unsigned int size)
320{
321 rb->base = ioremap(phys_addr + offset, size);
322 BUG_ON(rb->base == NULL);
323}
324
325#ifdef CONFIG_PPC_DCR
326static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
327 unsigned int offset, unsigned int size)
328{
329 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
330 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
331 BUG_ON(!DCR_MAP_OK(rb->dhost));
332}
333
334static inline void mpic_map(struct mpic *mpic,
335 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
336 unsigned int offset, unsigned int size)
337{
338 if (mpic->flags & MPIC_USES_DCR)
339 _mpic_map_dcr(mpic, rb, offset, size);
340 else
341 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
342}
343#else /* CONFIG_PPC_DCR */
344#define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
345#endif /* !CONFIG_PPC_DCR */
346
347
348
349/* Check if we have one of those nice broken MPICs with a flipped endian on
350 * reads from IPI registers
351 */
352static void __init mpic_test_broken_ipi(struct mpic *mpic)
353{
354 u32 r;
355
356 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
357 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
358
359 if (r == swab32(MPIC_VECPRI_MASK)) {
360 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
361 mpic->flags |= MPIC_BROKEN_IPI;
362 }
363}
364
365#ifdef CONFIG_MPIC_U3_HT_IRQS
366
367/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
368 * to force the edge setting on the MPIC and do the ack workaround.
369 */
370static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
371{
372 if (source >= 128 || !mpic->fixups)
373 return 0;
374 return mpic->fixups[source].base != NULL;
375}
376
377
378static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
379{
380 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
381
382 if (fixup->applebase) {
383 unsigned int soff = (fixup->index >> 3) & ~3;
384 unsigned int mask = 1U << (fixup->index & 0x1f);
385 writel(mask, fixup->applebase + soff);
386 } else {
387 raw_spin_lock(&mpic->fixup_lock);
388 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
389 writel(fixup->data, fixup->base + 4);
390 raw_spin_unlock(&mpic->fixup_lock);
391 }
392}
393
394static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
395 bool level)
396{
397 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
398 unsigned long flags;
399 u32 tmp;
400
401 if (fixup->base == NULL)
402 return;
403
404 DBG("startup_ht_interrupt(0x%x) index: %d\n",
405 source, fixup->index);
406 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
407 /* Enable and configure */
408 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
409 tmp = readl(fixup->base + 4);
410 tmp &= ~(0x23U);
411 if (level)
412 tmp |= 0x22;
413 writel(tmp, fixup->base + 4);
414 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
415
416#ifdef CONFIG_PM
417 /* use the lowest bit inverted to the actual HW,
418 * set if this fixup was enabled, clear otherwise */
419 mpic->save_data[source].fixup_data = tmp | 1;
420#endif
421}
422
423static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
424{
425 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
426 unsigned long flags;
427 u32 tmp;
428
429 if (fixup->base == NULL)
430 return;
431
432 DBG("shutdown_ht_interrupt(0x%x)\n", source);
433
434 /* Disable */
435 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
436 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
437 tmp = readl(fixup->base + 4);
438 tmp |= 1;
439 writel(tmp, fixup->base + 4);
440 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
441
442#ifdef CONFIG_PM
443 /* use the lowest bit inverted to the actual HW,
444 * set if this fixup was enabled, clear otherwise */
445 mpic->save_data[source].fixup_data = tmp & ~1;
446#endif
447}
448
449#ifdef CONFIG_PCI_MSI
450static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
451 unsigned int devfn)
452{
453 u8 __iomem *base;
454 u8 pos, flags;
455 u64 addr = 0;
456
457 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
458 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
459 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
460 if (id == PCI_CAP_ID_HT) {
461 id = readb(devbase + pos + 3);
462 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
463 break;
464 }
465 }
466
467 if (pos == 0)
468 return;
469
470 base = devbase + pos;
471
472 flags = readb(base + HT_MSI_FLAGS);
473 if (!(flags & HT_MSI_FLAGS_FIXED)) {
474 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
475 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
476 }
477
478 pr_debug("mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
479 PCI_SLOT(devfn), PCI_FUNC(devfn),
480 str_enabled_disabled(flags & HT_MSI_FLAGS_ENABLE), addr);
481
482 if (!(flags & HT_MSI_FLAGS_ENABLE))
483 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
484}
485#else
486static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
487 unsigned int devfn)
488{
489 return;
490}
491#endif
492
493static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
494 unsigned int devfn, u32 vdid)
495{
496 int i, irq, n;
497 u8 __iomem *base;
498 u32 tmp;
499 u8 pos;
500
501 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
502 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
503 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
504 if (id == PCI_CAP_ID_HT) {
505 id = readb(devbase + pos + 3);
506 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
507 break;
508 }
509 }
510 if (pos == 0)
511 return;
512
513 base = devbase + pos;
514 writeb(0x01, base + 2);
515 n = (readl(base + 4) >> 16) & 0xff;
516
517 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
518 " has %d irqs\n",
519 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
520
521 for (i = 0; i <= n; i++) {
522 writeb(0x10 + 2 * i, base + 2);
523 tmp = readl(base + 4);
524 irq = (tmp >> 16) & 0xff;
525 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
526 /* mask it , will be unmasked later */
527 tmp |= 0x1;
528 writel(tmp, base + 4);
529 mpic->fixups[irq].index = i;
530 mpic->fixups[irq].base = base;
531 /* Apple HT PIC has a non-standard way of doing EOIs */
532 if ((vdid & 0xffff) == 0x106b)
533 mpic->fixups[irq].applebase = devbase + 0x60;
534 else
535 mpic->fixups[irq].applebase = NULL;
536 writeb(0x11 + 2 * i, base + 2);
537 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
538 }
539}
540
541
542static void __init mpic_scan_ht_pics(struct mpic *mpic)
543{
544 unsigned int devfn;
545 u8 __iomem *cfgspace;
546
547 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
548
549 /* Allocate fixups array */
550 mpic->fixups = kzalloc_objs(*mpic->fixups, 128);
551 BUG_ON(mpic->fixups == NULL);
552
553 /* Init spinlock */
554 raw_spin_lock_init(&mpic->fixup_lock);
555
556 /* Map U3 config space. We assume all IO-APICs are on the primary bus
557 * so we only need to map 64kB.
558 */
559 cfgspace = ioremap(0xf2000000, 0x10000);
560 BUG_ON(cfgspace == NULL);
561
562 /* Now we scan all slots. We do a very quick scan, we read the header
563 * type, vendor ID and device ID only, that's plenty enough
564 */
565 for (devfn = 0; devfn < 0x100; devfn++) {
566 u8 __iomem *devbase = cfgspace + (devfn << 8);
567 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
568 u32 l = readl(devbase + PCI_VENDOR_ID);
569 u16 s;
570
571 DBG("devfn %x, l: %x\n", devfn, l);
572
573 /* If no device, skip */
574 if (l == 0xffffffff || l == 0x00000000 ||
575 l == 0x0000ffff || l == 0xffff0000)
576 goto next;
577 /* Check if is supports capability lists */
578 s = readw(devbase + PCI_STATUS);
579 if (!(s & PCI_STATUS_CAP_LIST))
580 goto next;
581
582 mpic_scan_ht_pic(mpic, devbase, devfn, l);
583 mpic_scan_ht_msi(mpic, devbase, devfn);
584
585 next:
586 /* next device, if function 0 */
587 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
588 devfn += 7;
589 }
590}
591
592#else /* CONFIG_MPIC_U3_HT_IRQS */
593
594static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
595{
596 return 0;
597}
598
599static void __init mpic_scan_ht_pics(struct mpic *mpic)
600{
601}
602
603#endif /* CONFIG_MPIC_U3_HT_IRQS */
604
605/* Find an mpic associated with a given linux interrupt */
606static struct mpic *mpic_find(unsigned int irq)
607{
608 if (irq < NR_IRQS_LEGACY)
609 return NULL;
610
611 return irq_get_chip_data(irq);
612}
613
614/* Determine if the linux irq is an IPI */
615static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
616{
617 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
618}
619
620/* Determine if the linux irq is a timer */
621static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
622{
623 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
624}
625
626/* Convert a cpu mask from logical to physical cpu numbers. */
627static inline u32 mpic_physmask(u32 cpumask)
628{
629 int i;
630 u32 mask = 0;
631
632 for (i = 0; i < min(32, NR_CPUS) && cpu_possible(i); ++i, cpumask >>= 1)
633 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
634 return mask;
635}
636
637#ifdef CONFIG_SMP
638/* Get the mpic structure from the IPI number */
639static inline struct mpic * mpic_from_ipi(struct irq_data *d)
640{
641 return irq_data_get_irq_chip_data(d);
642}
643#endif
644
645/* Get the mpic structure from the irq number */
646static inline struct mpic * mpic_from_irq(unsigned int irq)
647{
648 return irq_get_chip_data(irq);
649}
650
651/* Get the mpic structure from the irq data */
652static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
653{
654 return irq_data_get_irq_chip_data(d);
655}
656
657/* Send an EOI */
658static inline void mpic_eoi(struct mpic *mpic)
659{
660 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
661}
662
663/*
664 * Linux descriptor level callbacks
665 */
666
667
668void mpic_unmask_irq(struct irq_data *d)
669{
670 unsigned int loops = 100000;
671 struct mpic *mpic = mpic_from_irq_data(d);
672 unsigned int src = irqd_to_hwirq(d);
673
674 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
675
676 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
677 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
678 ~MPIC_VECPRI_MASK);
679 /* make sure mask gets to controller before we return to user */
680 do {
681 if (!loops--) {
682 printk(KERN_ERR "%s: timeout on hwirq %u\n",
683 __func__, src);
684 break;
685 }
686 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
687}
688
689void mpic_mask_irq(struct irq_data *d)
690{
691 unsigned int loops = 100000;
692 struct mpic *mpic = mpic_from_irq_data(d);
693 unsigned int src = irqd_to_hwirq(d);
694
695 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
696
697 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
698 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
699 MPIC_VECPRI_MASK);
700
701 /* make sure mask gets to controller before we return to user */
702 do {
703 if (!loops--) {
704 printk(KERN_ERR "%s: timeout on hwirq %u\n",
705 __func__, src);
706 break;
707 }
708 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
709}
710
711void mpic_end_irq(struct irq_data *d)
712{
713 struct mpic *mpic = mpic_from_irq_data(d);
714
715#ifdef DEBUG_IRQ
716 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
717#endif
718 /* We always EOI on end_irq() even for edge interrupts since that
719 * should only lower the priority, the MPIC should have properly
720 * latched another edge interrupt coming in anyway
721 */
722
723 mpic_eoi(mpic);
724}
725
726#ifdef CONFIG_MPIC_U3_HT_IRQS
727
728static void mpic_unmask_ht_irq(struct irq_data *d)
729{
730 struct mpic *mpic = mpic_from_irq_data(d);
731 unsigned int src = irqd_to_hwirq(d);
732
733 mpic_unmask_irq(d);
734
735 if (irqd_is_level_type(d))
736 mpic_ht_end_irq(mpic, src);
737}
738
739static unsigned int mpic_startup_ht_irq(struct irq_data *d)
740{
741 struct mpic *mpic = mpic_from_irq_data(d);
742 unsigned int src = irqd_to_hwirq(d);
743
744 mpic_unmask_irq(d);
745 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
746
747 return 0;
748}
749
750static void mpic_shutdown_ht_irq(struct irq_data *d)
751{
752 struct mpic *mpic = mpic_from_irq_data(d);
753 unsigned int src = irqd_to_hwirq(d);
754
755 mpic_shutdown_ht_interrupt(mpic, src);
756 mpic_mask_irq(d);
757}
758
759static void mpic_end_ht_irq(struct irq_data *d)
760{
761 struct mpic *mpic = mpic_from_irq_data(d);
762 unsigned int src = irqd_to_hwirq(d);
763
764#ifdef DEBUG_IRQ
765 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
766#endif
767 /* We always EOI on end_irq() even for edge interrupts since that
768 * should only lower the priority, the MPIC should have properly
769 * latched another edge interrupt coming in anyway
770 */
771
772 if (irqd_is_level_type(d))
773 mpic_ht_end_irq(mpic, src);
774 mpic_eoi(mpic);
775}
776#endif /* !CONFIG_MPIC_U3_HT_IRQS */
777
778#ifdef CONFIG_SMP
779
780static void mpic_unmask_ipi(struct irq_data *d)
781{
782 struct mpic *mpic = mpic_from_ipi(d);
783 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
784
785 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
786 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
787}
788
789static void mpic_mask_ipi(struct irq_data *d)
790{
791 /* NEVER disable an IPI... that's just plain wrong! */
792}
793
794static void mpic_end_ipi(struct irq_data *d)
795{
796 struct mpic *mpic = mpic_from_ipi(d);
797
798 /*
799 * IPIs are marked IRQ_PER_CPU. This has the side effect of
800 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
801 * applying to them. We EOI them late to avoid re-entering.
802 */
803 mpic_eoi(mpic);
804}
805
806#endif /* CONFIG_SMP */
807
808static void mpic_unmask_tm(struct irq_data *d)
809{
810 struct mpic *mpic = mpic_from_irq_data(d);
811 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
812
813 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
814 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
815 mpic_tm_read(src);
816}
817
818static void mpic_mask_tm(struct irq_data *d)
819{
820 struct mpic *mpic = mpic_from_irq_data(d);
821 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
822
823 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
824 mpic_tm_read(src);
825}
826
827int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
828 bool force)
829{
830 struct mpic *mpic = mpic_from_irq_data(d);
831 unsigned int src = irqd_to_hwirq(d);
832
833 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
834 int cpuid = irq_choose_cpu(cpumask);
835
836 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
837 } else {
838 u32 mask = cpumask_bits(cpumask)[0];
839
840 mask &= cpumask_bits(cpu_online_mask)[0];
841
842 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
843 mpic_physmask(mask));
844 }
845
846 return IRQ_SET_MASK_OK;
847}
848
849static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
850{
851 /* Now convert sense value */
852 switch(type & IRQ_TYPE_SENSE_MASK) {
853 case IRQ_TYPE_EDGE_RISING:
854 return MPIC_INFO(VECPRI_SENSE_EDGE) |
855 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
856 case IRQ_TYPE_EDGE_FALLING:
857 case IRQ_TYPE_EDGE_BOTH:
858 return MPIC_INFO(VECPRI_SENSE_EDGE) |
859 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
860 case IRQ_TYPE_LEVEL_HIGH:
861 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
862 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
863 case IRQ_TYPE_LEVEL_LOW:
864 default:
865 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
866 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
867 }
868}
869
870int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
871{
872 struct mpic *mpic = mpic_from_irq_data(d);
873 unsigned int src = irqd_to_hwirq(d);
874 unsigned int vecpri, vold, vnew;
875
876 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
877 mpic, d->irq, src, flow_type);
878
879 if (src >= mpic->num_sources)
880 return -EINVAL;
881
882 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
883
884 /* We don't support "none" type */
885 if (flow_type == IRQ_TYPE_NONE)
886 flow_type = IRQ_TYPE_DEFAULT;
887
888 /* Default: read HW settings */
889 if (flow_type == IRQ_TYPE_DEFAULT) {
890 int vold_ps;
891
892 vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
893 MPIC_INFO(VECPRI_SENSE_MASK));
894
895 if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
896 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
897 flow_type = IRQ_TYPE_EDGE_RISING;
898 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
899 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
900 flow_type = IRQ_TYPE_EDGE_FALLING;
901 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
902 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
903 flow_type = IRQ_TYPE_LEVEL_HIGH;
904 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
905 MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
906 flow_type = IRQ_TYPE_LEVEL_LOW;
907 else
908 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
909 }
910
911 /* Apply to irq desc */
912 irqd_set_trigger_type(d, flow_type);
913
914 /* Apply to HW */
915 if (mpic_is_ht_interrupt(mpic, src))
916 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
917 MPIC_VECPRI_SENSE_EDGE;
918 else
919 vecpri = mpic_type_to_vecpri(mpic, flow_type);
920
921 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
922 MPIC_INFO(VECPRI_SENSE_MASK));
923 vnew |= vecpri;
924 if (vold != vnew)
925 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
926
927 return IRQ_SET_MASK_OK_NOCOPY;
928}
929
930void mpic_set_vector(unsigned int virq, unsigned int vector)
931{
932 struct mpic *mpic = mpic_from_irq(virq);
933 unsigned int src = virq_to_hw(virq);
934 unsigned int vecpri;
935
936 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
937 mpic, virq, src, vector);
938
939 if (src >= mpic->num_sources)
940 return;
941
942 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
943 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
944 vecpri |= vector;
945 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
946}
947
948static void mpic_set_destination(unsigned int virq, unsigned int cpuid)
949{
950 struct mpic *mpic = mpic_from_irq(virq);
951 unsigned int src = virq_to_hw(virq);
952
953 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
954 mpic, virq, src, cpuid);
955
956 if (src >= mpic->num_sources)
957 return;
958
959 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
960}
961
962static struct irq_chip mpic_irq_chip = {
963 .irq_mask = mpic_mask_irq,
964 .irq_unmask = mpic_unmask_irq,
965 .irq_eoi = mpic_end_irq,
966 .irq_set_type = mpic_set_irq_type,
967};
968
969#ifdef CONFIG_SMP
970static const struct irq_chip mpic_ipi_chip = {
971 .irq_mask = mpic_mask_ipi,
972 .irq_unmask = mpic_unmask_ipi,
973 .irq_eoi = mpic_end_ipi,
974};
975#endif /* CONFIG_SMP */
976
977static struct irq_chip mpic_tm_chip = {
978 .irq_mask = mpic_mask_tm,
979 .irq_unmask = mpic_unmask_tm,
980 .irq_eoi = mpic_end_irq,
981};
982
983#ifdef CONFIG_MPIC_U3_HT_IRQS
984static const struct irq_chip mpic_irq_ht_chip = {
985 .irq_startup = mpic_startup_ht_irq,
986 .irq_shutdown = mpic_shutdown_ht_irq,
987 .irq_mask = mpic_mask_irq,
988 .irq_unmask = mpic_unmask_ht_irq,
989 .irq_eoi = mpic_end_ht_irq,
990 .irq_set_type = mpic_set_irq_type,
991};
992#endif /* CONFIG_MPIC_U3_HT_IRQS */
993
994
995static int mpic_host_match(struct irq_domain *h, struct device_node *node,
996 enum irq_domain_bus_token bus_token)
997{
998 /* Exact match, unless mpic node is NULL */
999 struct device_node *of_node = irq_domain_get_of_node(h);
1000 return of_node == NULL || of_node == node;
1001}
1002
1003static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1004 irq_hw_number_t hw)
1005{
1006 struct mpic *mpic = h->host_data;
1007 struct irq_chip *chip;
1008
1009 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1010
1011 if (hw == mpic->spurious_vec)
1012 return -EINVAL;
1013 if (mpic->protected && test_bit(hw, mpic->protected)) {
1014 pr_warn("mpic: Mapping of source 0x%x failed, source protected by firmware !\n",
1015 (unsigned int)hw);
1016 return -EPERM;
1017 }
1018
1019#ifdef CONFIG_SMP
1020 else if (hw >= mpic->ipi_vecs[0]) {
1021 WARN_ON(mpic->flags & MPIC_SECONDARY);
1022
1023 DBG("mpic: mapping as IPI\n");
1024 irq_set_chip_data(virq, mpic);
1025 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1026 handle_percpu_irq);
1027 return 0;
1028 }
1029#endif /* CONFIG_SMP */
1030
1031 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1032 WARN_ON(mpic->flags & MPIC_SECONDARY);
1033
1034 DBG("mpic: mapping as timer\n");
1035 irq_set_chip_data(virq, mpic);
1036 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1037 handle_fasteoi_irq);
1038 return 0;
1039 }
1040
1041 if (mpic_map_error_int(mpic, virq, hw))
1042 return 0;
1043
1044 if (hw >= mpic->num_sources) {
1045 pr_warn("mpic: Mapping of source 0x%x failed, source out of range !\n",
1046 (unsigned int)hw);
1047 return -EINVAL;
1048 }
1049
1050 mpic_msi_reserve_hwirq(mpic, hw);
1051
1052 /* Default chip */
1053 chip = &mpic->hc_irq;
1054
1055#ifdef CONFIG_MPIC_U3_HT_IRQS
1056 /* Check for HT interrupts, override vecpri */
1057 if (mpic_is_ht_interrupt(mpic, hw))
1058 chip = &mpic->hc_ht_irq;
1059#endif /* CONFIG_MPIC_U3_HT_IRQS */
1060
1061 DBG("mpic: mapping to irq chip @%p\n", chip);
1062
1063 irq_set_chip_data(virq, mpic);
1064 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1065
1066 /* Set default irq type */
1067 irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1068
1069 /* If the MPIC was reset, then all vectors have already been
1070 * initialized. Otherwise, a per source lazy initialization
1071 * is done here.
1072 */
1073 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1074 int cpu;
1075
1076 preempt_disable();
1077 cpu = mpic_processor_id(mpic);
1078 preempt_enable();
1079
1080 mpic_set_vector(virq, hw);
1081 mpic_set_destination(virq, cpu);
1082 mpic_irq_set_priority(virq, 8);
1083 }
1084
1085 return 0;
1086}
1087
1088static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1089 const u32 *intspec, unsigned int intsize,
1090 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1091
1092{
1093 struct mpic *mpic = h->host_data;
1094 static unsigned char map_mpic_senses[4] = {
1095 IRQ_TYPE_EDGE_RISING,
1096 IRQ_TYPE_LEVEL_LOW,
1097 IRQ_TYPE_LEVEL_HIGH,
1098 IRQ_TYPE_EDGE_FALLING,
1099 };
1100
1101 *out_hwirq = intspec[0];
1102 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1103 /*
1104 * Freescale MPIC with extended intspec:
1105 * First two cells are as usual. Third specifies
1106 * an "interrupt type". Fourth is type-specific data.
1107 *
1108 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1109 */
1110 switch (intspec[2]) {
1111 case 0:
1112 break;
1113 case 1:
1114 if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1115 break;
1116
1117 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1118 return -EINVAL;
1119
1120 *out_hwirq = mpic->err_int_vecs[intspec[3]];
1121
1122 break;
1123 case 2:
1124 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1125 return -EINVAL;
1126
1127 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1128 break;
1129 case 3:
1130 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1131 return -EINVAL;
1132
1133 *out_hwirq = mpic->timer_vecs[intspec[0]];
1134 break;
1135 default:
1136 pr_debug("%s: unknown irq type %u\n",
1137 __func__, intspec[2]);
1138 return -EINVAL;
1139 }
1140
1141 *out_flags = map_mpic_senses[intspec[1] & 3];
1142 } else if (intsize > 1) {
1143 u32 mask = 0x3;
1144
1145 /* Apple invented a new race of encoding on machines with
1146 * an HT APIC. They encode, among others, the index within
1147 * the HT APIC. We don't care about it here since thankfully,
1148 * it appears that they have the APIC already properly
1149 * configured, and thus our current fixup code that reads the
1150 * APIC config works fine. However, we still need to mask out
1151 * bits in the specifier to make sure we only get bit 0 which
1152 * is the level/edge bit (the only sense bit exposed by Apple),
1153 * as their bit 1 means something else.
1154 */
1155 if (machine_is(powermac))
1156 mask = 0x1;
1157 *out_flags = map_mpic_senses[intspec[1] & mask];
1158 } else
1159 *out_flags = IRQ_TYPE_NONE;
1160
1161 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1162 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1163
1164 return 0;
1165}
1166
1167/* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1168static void mpic_cascade(struct irq_desc *desc)
1169{
1170 struct irq_chip *chip = irq_desc_get_chip(desc);
1171 struct mpic *mpic = irq_desc_get_handler_data(desc);
1172 unsigned int virq;
1173
1174 BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1175
1176 virq = mpic_get_one_irq(mpic);
1177 if (virq)
1178 generic_handle_irq(virq);
1179
1180 chip->irq_eoi(&desc->irq_data);
1181}
1182
1183static const struct irq_domain_ops mpic_host_ops = {
1184 .match = mpic_host_match,
1185 .map = mpic_host_map,
1186 .xlate = mpic_host_xlate,
1187};
1188
1189static u32 fsl_mpic_get_version(struct mpic *mpic)
1190{
1191 u32 brr1;
1192
1193 if (!(mpic->flags & MPIC_FSL))
1194 return 0;
1195
1196 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1197 MPIC_FSL_BRR1);
1198
1199 return brr1 & MPIC_FSL_BRR1_VER;
1200}
1201
1202/*
1203 * Exported functions
1204 */
1205
1206u32 fsl_mpic_primary_get_version(void)
1207{
1208 struct mpic *mpic = mpic_primary;
1209
1210 if (mpic)
1211 return fsl_mpic_get_version(mpic);
1212
1213 return 0;
1214}
1215
1216struct mpic * __init mpic_alloc(struct device_node *node,
1217 phys_addr_t phys_addr,
1218 unsigned int flags,
1219 unsigned int isu_size,
1220 unsigned int irq_count,
1221 const char *name)
1222{
1223 int i, psize, intvec_top;
1224 struct mpic *mpic;
1225 u32 greg_feature;
1226 const char *vers;
1227 const u32 *psrc;
1228 u32 last_irq;
1229 u32 fsl_version = 0;
1230
1231 /* Default MPIC search parameters */
1232 static const struct of_device_id __initconst mpic_device_id[] = {
1233 { .type = "open-pic", },
1234 { .compatible = "open-pic", },
1235 {},
1236 };
1237
1238 /*
1239 * If we were not passed a device-tree node, then perform the default
1240 * search for standardized a standardized OpenPIC.
1241 */
1242 if (node) {
1243 node = of_node_get(node);
1244 } else {
1245 node = of_find_matching_node(NULL, mpic_device_id);
1246 if (!node)
1247 return NULL;
1248 }
1249
1250 /* Pick the physical address from the device tree if unspecified */
1251 if (!phys_addr) {
1252 /* Check if it is DCR-based */
1253 if (of_property_read_bool(node, "dcr-reg")) {
1254 flags |= MPIC_USES_DCR;
1255 } else {
1256 struct resource r;
1257 if (of_address_to_resource(node, 0, &r))
1258 goto err_of_node_put;
1259 phys_addr = r.start;
1260 }
1261 }
1262
1263 /* Read extra device-tree properties into the flags variable */
1264 if (of_property_read_bool(node, "big-endian"))
1265 flags |= MPIC_BIG_ENDIAN;
1266 if (of_property_read_bool(node, "pic-no-reset"))
1267 flags |= MPIC_NO_RESET;
1268 if (of_property_read_bool(node, "single-cpu-affinity"))
1269 flags |= MPIC_SINGLE_DEST_CPU;
1270 if (of_device_is_compatible(node, "fsl,mpic")) {
1271 flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1272 mpic_irq_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1273 mpic_tm_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
1274 }
1275
1276 mpic = kzalloc_obj(struct mpic);
1277 if (mpic == NULL)
1278 goto err_of_node_put;
1279
1280 mpic->name = name;
1281 mpic->node = node;
1282 mpic->paddr = phys_addr;
1283 mpic->flags = flags;
1284
1285 mpic->hc_irq = mpic_irq_chip;
1286 mpic->hc_irq.name = name;
1287 if (!(mpic->flags & MPIC_SECONDARY))
1288 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1289#ifdef CONFIG_MPIC_U3_HT_IRQS
1290 mpic->hc_ht_irq = mpic_irq_ht_chip;
1291 mpic->hc_ht_irq.name = name;
1292 if (!(mpic->flags & MPIC_SECONDARY))
1293 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1294#endif /* CONFIG_MPIC_U3_HT_IRQS */
1295
1296#ifdef CONFIG_SMP
1297 mpic->hc_ipi = mpic_ipi_chip;
1298 mpic->hc_ipi.name = name;
1299#endif /* CONFIG_SMP */
1300
1301 mpic->hc_tm = mpic_tm_chip;
1302 mpic->hc_tm.name = name;
1303
1304 mpic->num_sources = 0; /* so far */
1305
1306 if (mpic->flags & MPIC_LARGE_VECTORS)
1307 intvec_top = 2047;
1308 else
1309 intvec_top = 255;
1310
1311 mpic->timer_vecs[0] = intvec_top - 12;
1312 mpic->timer_vecs[1] = intvec_top - 11;
1313 mpic->timer_vecs[2] = intvec_top - 10;
1314 mpic->timer_vecs[3] = intvec_top - 9;
1315 mpic->timer_vecs[4] = intvec_top - 8;
1316 mpic->timer_vecs[5] = intvec_top - 7;
1317 mpic->timer_vecs[6] = intvec_top - 6;
1318 mpic->timer_vecs[7] = intvec_top - 5;
1319 mpic->ipi_vecs[0] = intvec_top - 4;
1320 mpic->ipi_vecs[1] = intvec_top - 3;
1321 mpic->ipi_vecs[2] = intvec_top - 2;
1322 mpic->ipi_vecs[3] = intvec_top - 1;
1323 mpic->spurious_vec = intvec_top;
1324
1325 /* Look for protected sources */
1326 psrc = of_get_property(mpic->node, "protected-sources", &psize);
1327 if (psrc) {
1328 /* Allocate a bitmap with one bit per interrupt */
1329 mpic->protected = bitmap_zalloc(intvec_top + 1, GFP_KERNEL);
1330 BUG_ON(mpic->protected == NULL);
1331 for (i = 0; i < psize/sizeof(u32); i++) {
1332 if (psrc[i] > intvec_top)
1333 continue;
1334 __set_bit(psrc[i], mpic->protected);
1335 }
1336 }
1337
1338#ifdef CONFIG_MPIC_WEIRD
1339 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1340#endif
1341
1342 /* default register type */
1343 if (mpic->flags & MPIC_BIG_ENDIAN)
1344 mpic->reg_type = mpic_access_mmio_be;
1345 else
1346 mpic->reg_type = mpic_access_mmio_le;
1347
1348 /*
1349 * An MPIC with a "dcr-reg" property must be accessed that way, but
1350 * only if the kernel includes DCR support.
1351 */
1352#ifdef CONFIG_PPC_DCR
1353 if (mpic->flags & MPIC_USES_DCR)
1354 mpic->reg_type = mpic_access_dcr;
1355#else
1356 BUG_ON(mpic->flags & MPIC_USES_DCR);
1357#endif
1358
1359 /* Map the global registers */
1360 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1361 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1362
1363 if (mpic->flags & MPIC_FSL) {
1364 int ret;
1365
1366 /*
1367 * Yes, Freescale really did put global registers in the
1368 * magic per-cpu area -- and they don't even show up in the
1369 * non-magic per-cpu copies that this driver normally uses.
1370 */
1371 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1372 MPIC_CPU_THISBASE, 0x1000);
1373
1374 fsl_version = fsl_mpic_get_version(mpic);
1375
1376 /* Error interrupt mask register (EIMR) is required for
1377 * handling individual device error interrupts. EIMR
1378 * was added in MPIC version 4.1.
1379 *
1380 * Over here we reserve vector number space for error
1381 * interrupt vectors. This space is stolen from the
1382 * global vector number space, as in case of ipis
1383 * and timer interrupts.
1384 *
1385 * Available vector space = intvec_top - 13, where 13
1386 * is the number of vectors which have been consumed by
1387 * ipis, timer interrupts and spurious.
1388 */
1389 if (fsl_version >= 0x401) {
1390 ret = mpic_setup_error_int(mpic, intvec_top - 13);
1391 if (ret)
1392 return NULL;
1393 }
1394
1395 }
1396
1397 /*
1398 * EPR is only available starting with v4.0. To support
1399 * platforms that don't know the MPIC version at compile-time,
1400 * such as qemu-e500, turn off coreint if this MPIC doesn't
1401 * support it. Note that we never enable it if it wasn't
1402 * requested in the first place.
1403 *
1404 * This is done outside the MPIC_FSL check, so that we
1405 * also disable coreint if the MPIC node doesn't have
1406 * an "fsl,mpic" compatible at all. This will be the case
1407 * with device trees generated by older versions of QEMU.
1408 * fsl_version will be zero if MPIC_FSL is not set.
1409 */
1410 if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT))
1411 ppc_md.get_irq = mpic_get_irq;
1412
1413 /* Reset */
1414
1415 /* When using a device-node, reset requests are only honored if the MPIC
1416 * is allowed to reset.
1417 */
1418 if (!(mpic->flags & MPIC_NO_RESET)) {
1419 printk(KERN_DEBUG "mpic: Resetting\n");
1420 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1421 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1422 | MPIC_GREG_GCONF_RESET);
1423 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1424 & MPIC_GREG_GCONF_RESET)
1425 mb();
1426 }
1427
1428 /* CoreInt */
1429 if (mpic->flags & MPIC_ENABLE_COREINT)
1430 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1431 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1432 | MPIC_GREG_GCONF_COREINT);
1433
1434 if (mpic->flags & MPIC_ENABLE_MCK)
1435 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1436 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1437 | MPIC_GREG_GCONF_MCK);
1438
1439 /*
1440 * The MPIC driver will crash if there are more cores than we
1441 * can initialize, so we may as well catch that problem here.
1442 */
1443 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1444
1445 /* Map the per-CPU registers */
1446 for_each_possible_cpu(i) {
1447 unsigned int cpu = get_hard_smp_processor_id(i);
1448
1449 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1450 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1451 0x1000);
1452 }
1453
1454 /*
1455 * Read feature register. For non-ISU MPICs, num sources as well. On
1456 * ISU MPICs, sources are counted as ISUs are added
1457 */
1458 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1459
1460 /*
1461 * By default, the last source number comes from the MPIC, but the
1462 * device-tree and board support code can override it on buggy hw.
1463 * If we get passed an isu_size (multi-isu MPIC) then we use that
1464 * as a default instead of the value read from the HW.
1465 */
1466 last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1467 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1468 if (isu_size)
1469 last_irq = isu_size * MPIC_MAX_ISU - 1;
1470 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1471 if (irq_count)
1472 last_irq = irq_count - 1;
1473
1474 /* Initialize main ISU if none provided */
1475 if (!isu_size) {
1476 isu_size = last_irq + 1;
1477 mpic->num_sources = isu_size;
1478 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1479 MPIC_INFO(IRQ_BASE),
1480 MPIC_INFO(IRQ_STRIDE) * isu_size);
1481 }
1482
1483 mpic->isu_size = isu_size;
1484 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1485 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1486
1487 mpic->irqhost = irq_domain_create_linear(of_fwnode_handle(mpic->node),
1488 intvec_top,
1489 &mpic_host_ops, mpic);
1490
1491 /*
1492 * FIXME: The code leaks the MPIC object and mappings here; this
1493 * is very unlikely to fail but it ought to be fixed anyways.
1494 */
1495 if (mpic->irqhost == NULL)
1496 return NULL;
1497
1498 /* Display version */
1499 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1500 case 1:
1501 vers = "1.0";
1502 break;
1503 case 2:
1504 vers = "1.2";
1505 break;
1506 case 3:
1507 vers = "1.3";
1508 break;
1509 default:
1510 vers = "<unknown>";
1511 break;
1512 }
1513 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1514 " max %d CPUs\n",
1515 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1516 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1517 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1518
1519 mpic->next = mpics;
1520 mpics = mpic;
1521
1522 if (!(mpic->flags & MPIC_SECONDARY)) {
1523 mpic_primary = mpic;
1524 irq_set_default_domain(mpic->irqhost);
1525 }
1526
1527 return mpic;
1528
1529err_of_node_put:
1530 of_node_put(node);
1531 return NULL;
1532}
1533
1534void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1535 phys_addr_t paddr)
1536{
1537 unsigned int isu_first = isu_num * mpic->isu_size;
1538
1539 BUG_ON(isu_num >= MPIC_MAX_ISU);
1540
1541 mpic_map(mpic,
1542 paddr, &mpic->isus[isu_num], 0,
1543 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1544
1545 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1546 mpic->num_sources = isu_first + mpic->isu_size;
1547}
1548
1549void __init mpic_init(struct mpic *mpic)
1550{
1551 int i, cpu;
1552 int num_timers = 4;
1553
1554 BUG_ON(mpic->num_sources == 0);
1555
1556 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1557
1558 /* Set current processor priority to max */
1559 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1560
1561 if (mpic->flags & MPIC_FSL) {
1562 u32 version = fsl_mpic_get_version(mpic);
1563
1564 /*
1565 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1566 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
1567 * I don't know about the status of intermediate versions (or
1568 * whether they even exist).
1569 */
1570 if (version >= 0x0301)
1571 num_timers = 8;
1572 }
1573
1574 /* Initialize timers to our reserved vectors and mask them for now */
1575 for (i = 0; i < num_timers; i++) {
1576 unsigned int offset = mpic_tm_offset(mpic, i);
1577
1578 mpic_write(mpic->tmregs,
1579 offset + MPIC_INFO(TIMER_DESTINATION),
1580 1 << hard_smp_processor_id());
1581 mpic_write(mpic->tmregs,
1582 offset + MPIC_INFO(TIMER_VECTOR_PRI),
1583 MPIC_VECPRI_MASK |
1584 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1585 (mpic->timer_vecs[0] + i));
1586 }
1587
1588 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1589 mpic_test_broken_ipi(mpic);
1590 for (i = 0; i < 4; i++) {
1591 mpic_ipi_write(i,
1592 MPIC_VECPRI_MASK |
1593 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1594 (mpic->ipi_vecs[0] + i));
1595 }
1596
1597 /* Do the HT PIC fixups on U3 broken mpic */
1598 DBG("MPIC flags: %x\n", mpic->flags);
1599 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1600 mpic_scan_ht_pics(mpic);
1601 mpic_u3msi_init(mpic);
1602 }
1603
1604 mpic_pasemi_msi_init(mpic);
1605
1606 cpu = mpic_processor_id(mpic);
1607
1608 if (!(mpic->flags & MPIC_NO_RESET)) {
1609 for (i = 0; i < mpic->num_sources; i++) {
1610 /* start with vector = source number, and masked */
1611 u32 vecpri = MPIC_VECPRI_MASK | i |
1612 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1613
1614 /* check if protected */
1615 if (mpic->protected && test_bit(i, mpic->protected))
1616 continue;
1617 /* init hw */
1618 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1619 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1620 }
1621 }
1622
1623 /* Init spurious vector */
1624 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1625
1626 /* Disable 8259 passthrough, if supported */
1627 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1628 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1629 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1630 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1631
1632 if (mpic->flags & MPIC_NO_BIAS)
1633 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1634 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1635 | MPIC_GREG_GCONF_NO_BIAS);
1636
1637 /* Set current processor priority to 0 */
1638 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1639
1640#ifdef CONFIG_PM
1641 /* allocate memory to save mpic state */
1642 mpic->save_data = kmalloc_objs(*mpic->save_data, mpic->num_sources);
1643 BUG_ON(mpic->save_data == NULL);
1644#endif
1645
1646 /* Check if this MPIC is chained from a parent interrupt controller */
1647 if (mpic->flags & MPIC_SECONDARY) {
1648 int virq = irq_of_parse_and_map(mpic->node, 0);
1649 if (virq) {
1650 printk(KERN_INFO "%pOF: hooking up to IRQ %d\n",
1651 mpic->node, virq);
1652 irq_set_handler_data(virq, mpic);
1653 irq_set_chained_handler(virq, &mpic_cascade);
1654 }
1655 }
1656
1657 /* FSL mpic error interrupt initialization */
1658 if (mpic->flags & MPIC_FSL_HAS_EIMR)
1659 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1660}
1661
1662void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1663{
1664 struct mpic *mpic = mpic_find(irq);
1665 unsigned int src = virq_to_hw(irq);
1666 unsigned long flags;
1667 u32 reg;
1668
1669 if (!mpic)
1670 return;
1671
1672 raw_spin_lock_irqsave(&mpic_lock, flags);
1673 if (mpic_is_ipi(mpic, src)) {
1674 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1675 ~MPIC_VECPRI_PRIORITY_MASK;
1676 mpic_ipi_write(src - mpic->ipi_vecs[0],
1677 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1678 } else if (mpic_is_tm(mpic, src)) {
1679 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1680 ~MPIC_VECPRI_PRIORITY_MASK;
1681 mpic_tm_write(src - mpic->timer_vecs[0],
1682 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1683 } else {
1684 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1685 & ~MPIC_VECPRI_PRIORITY_MASK;
1686 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1687 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1688 }
1689 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1690}
1691
1692void mpic_setup_this_cpu(void)
1693{
1694#ifdef CONFIG_SMP
1695 struct mpic *mpic = mpic_primary;
1696 unsigned long flags;
1697 u32 msk = 1 << hard_smp_processor_id();
1698 unsigned int i;
1699
1700 BUG_ON(mpic == NULL);
1701
1702 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1703
1704 raw_spin_lock_irqsave(&mpic_lock, flags);
1705
1706 /* let the mpic know we want intrs. default affinity is 0xffffffff
1707 * until changed via /proc. That's how it's done on x86. If we want
1708 * it differently, then we should make sure we also change the default
1709 * values of irq_desc[].affinity in irq.c.
1710 */
1711 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1712 for (i = 0; i < mpic->num_sources ; i++)
1713 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1714 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1715 }
1716
1717 /* Set current processor priority to 0 */
1718 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1719
1720 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1721#endif /* CONFIG_SMP */
1722}
1723
1724int mpic_cpu_get_priority(void)
1725{
1726 struct mpic *mpic = mpic_primary;
1727
1728 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1729}
1730
1731void mpic_cpu_set_priority(int prio)
1732{
1733 struct mpic *mpic = mpic_primary;
1734
1735 prio &= MPIC_CPU_TASKPRI_MASK;
1736 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1737}
1738
1739void mpic_teardown_this_cpu(int secondary)
1740{
1741 struct mpic *mpic = mpic_primary;
1742 unsigned long flags;
1743 u32 msk = 1 << hard_smp_processor_id();
1744 unsigned int i;
1745
1746 BUG_ON(mpic == NULL);
1747
1748 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1749 raw_spin_lock_irqsave(&mpic_lock, flags);
1750
1751 /* let the mpic know we don't want intrs. */
1752 for (i = 0; i < mpic->num_sources ; i++)
1753 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1754 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1755
1756 /* Set current processor priority to max */
1757 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1758 /* We need to EOI the IPI since not all platforms reset the MPIC
1759 * on boot and new interrupts wouldn't get delivered otherwise.
1760 */
1761 mpic_eoi(mpic);
1762
1763 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1764}
1765
1766
1767static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1768{
1769 u32 src;
1770
1771 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1772#ifdef DEBUG_LOW
1773 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1774#endif
1775 if (unlikely(src == mpic->spurious_vec)) {
1776 if (mpic->flags & MPIC_SPV_EOI)
1777 mpic_eoi(mpic);
1778 return 0;
1779 }
1780 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1781 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1782 mpic->name, (int)src);
1783 mpic_eoi(mpic);
1784 return 0;
1785 }
1786
1787 return irq_find_mapping(mpic->irqhost, src);
1788}
1789
1790unsigned int mpic_get_one_irq(struct mpic *mpic)
1791{
1792 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1793}
1794
1795unsigned int mpic_get_irq(void)
1796{
1797 struct mpic *mpic = mpic_primary;
1798
1799 BUG_ON(mpic == NULL);
1800
1801 return mpic_get_one_irq(mpic);
1802}
1803
1804unsigned int mpic_get_coreint_irq(void)
1805{
1806#ifdef CONFIG_BOOKE
1807 struct mpic *mpic = mpic_primary;
1808 u32 src;
1809
1810 BUG_ON(mpic == NULL);
1811
1812 src = mfspr(SPRN_EPR);
1813
1814 if (unlikely(src == mpic->spurious_vec)) {
1815 if (mpic->flags & MPIC_SPV_EOI)
1816 mpic_eoi(mpic);
1817 return 0;
1818 }
1819 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1820 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1821 mpic->name, (int)src);
1822 return 0;
1823 }
1824
1825 return irq_find_mapping(mpic->irqhost, src);
1826#else
1827 return 0;
1828#endif
1829}
1830
1831unsigned int mpic_get_mcirq(void)
1832{
1833 struct mpic *mpic = mpic_primary;
1834
1835 BUG_ON(mpic == NULL);
1836
1837 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1838}
1839
1840#ifdef CONFIG_SMP
1841void __init mpic_request_ipis(void)
1842{
1843 struct mpic *mpic = mpic_primary;
1844 int i;
1845 BUG_ON(mpic == NULL);
1846
1847 printk(KERN_INFO "mpic: requesting IPIs...\n");
1848
1849 for (i = 0; i < 4; i++) {
1850 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1851 mpic->ipi_vecs[0] + i);
1852 if (!vipi) {
1853 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1854 continue;
1855 }
1856 smp_request_message_ipi(vipi, i);
1857 }
1858}
1859
1860void smp_mpic_message_pass(int cpu, int msg)
1861{
1862 struct mpic *mpic = mpic_primary;
1863 u32 physmask;
1864
1865 BUG_ON(mpic == NULL);
1866
1867 /* make sure we're sending something that translates to an IPI */
1868 if ((unsigned int)msg > 3) {
1869 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1870 smp_processor_id(), msg);
1871 return;
1872 }
1873
1874#ifdef DEBUG_IPI
1875 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1876#endif
1877
1878 physmask = 1 << get_hard_smp_processor_id(cpu);
1879
1880 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1881 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1882}
1883
1884void __init smp_mpic_probe(void)
1885{
1886 int nr_cpus;
1887
1888 DBG("smp_mpic_probe()...\n");
1889
1890 nr_cpus = num_possible_cpus();
1891
1892 DBG("nr_cpus: %d\n", nr_cpus);
1893
1894 if (nr_cpus > 1)
1895 mpic_request_ipis();
1896}
1897
1898void smp_mpic_setup_cpu(int cpu)
1899{
1900 mpic_setup_this_cpu();
1901}
1902
1903void mpic_reset_core(int cpu)
1904{
1905 struct mpic *mpic = mpic_primary;
1906 u32 pir;
1907 int cpuid = get_hard_smp_processor_id(cpu);
1908 int i;
1909
1910 /* Set target bit for core reset */
1911 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1912 pir |= (1 << cpuid);
1913 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1914 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1915
1916 /* Restore target bit after reset complete */
1917 pir &= ~(1 << cpuid);
1918 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1919 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1920
1921 /* Perform 15 EOI on each reset core to clear pending interrupts.
1922 * This is required for FSL CoreNet based devices */
1923 if (mpic->flags & MPIC_FSL) {
1924 for (i = 0; i < 15; i++) {
1925 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1926 MPIC_CPU_EOI, 0);
1927 }
1928 }
1929}
1930#endif /* CONFIG_SMP */
1931
1932#ifdef CONFIG_PM
1933static void mpic_suspend_one(struct mpic *mpic)
1934{
1935 int i;
1936
1937 for (i = 0; i < mpic->num_sources; i++) {
1938 mpic->save_data[i].vecprio =
1939 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1940 mpic->save_data[i].dest =
1941 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1942 }
1943}
1944
1945static int mpic_suspend(void *data)
1946{
1947 struct mpic *mpic = mpics;
1948
1949 while (mpic) {
1950 mpic_suspend_one(mpic);
1951 mpic = mpic->next;
1952 }
1953
1954 return 0;
1955}
1956
1957static void mpic_resume_one(struct mpic *mpic)
1958{
1959 int i;
1960
1961 for (i = 0; i < mpic->num_sources; i++) {
1962 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1963 mpic->save_data[i].vecprio);
1964 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1965 mpic->save_data[i].dest);
1966
1967#ifdef CONFIG_MPIC_U3_HT_IRQS
1968 if (mpic->fixups) {
1969 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1970
1971 if (fixup->base) {
1972 /* we use the lowest bit in an inverted meaning */
1973 if ((mpic->save_data[i].fixup_data & 1) == 0)
1974 continue;
1975
1976 /* Enable and configure */
1977 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1978
1979 writel(mpic->save_data[i].fixup_data & ~1,
1980 fixup->base + 4);
1981 }
1982 }
1983#endif
1984 } /* end for loop */
1985}
1986
1987static void mpic_resume(void *data)
1988{
1989 struct mpic *mpic = mpics;
1990
1991 while (mpic) {
1992 mpic_resume_one(mpic);
1993 mpic = mpic->next;
1994 }
1995}
1996
1997static const struct syscore_ops mpic_syscore_ops = {
1998 .resume = mpic_resume,
1999 .suspend = mpic_suspend,
2000};
2001
2002static struct syscore mpic_syscore = {
2003 .ops = &mpic_syscore_ops,
2004};
2005
2006static int mpic_init_sys(void)
2007{
2008 int rc;
2009
2010 register_syscore(&mpic_syscore);
2011 rc = subsys_system_register(&mpic_subsys, NULL);
2012 if (rc) {
2013 unregister_syscore(&mpic_syscore);
2014 pr_err("mpic: Failed to register subsystem!\n");
2015 return rc;
2016 }
2017
2018 return 0;
2019}
2020
2021device_initcall(mpic_init_sys);
2022#endif