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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ICS backend for OPAL managed interrupts.
4 *
5 * Copyright 2011 IBM Corp.
6 */
7
8#undef DEBUG
9
10#include <linux/types.h>
11#include <linux/kernel.h>
12#include <linux/irq.h>
13#include <linux/smp.h>
14#include <linux/interrupt.h>
15#include <linux/init.h>
16#include <linux/cpu.h>
17#include <linux/of.h>
18#include <linux/spinlock.h>
19#include <linux/msi.h>
20
21#include <asm/smp.h>
22#include <asm/machdep.h>
23#include <asm/irq.h>
24#include <asm/errno.h>
25#include <asm/xics.h>
26#include <asm/opal.h>
27#include <asm/firmware.h>
28
29static int ics_opal_mangle_server(int server)
30{
31 /* No link for now */
32 return server << 2;
33}
34
35static int ics_opal_unmangle_server(int server)
36{
37 /* No link for now */
38 return server >> 2;
39}
40
41static void ics_opal_unmask_irq(struct irq_data *d)
42{
43 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
44 int64_t rc;
45 int server;
46
47 pr_devel("ics-hal: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq);
48
49 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
50 return;
51
52 server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
53 server = ics_opal_mangle_server(server);
54
55 rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
56 if (rc != OPAL_SUCCESS)
57 pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
58 " error %lld\n",
59 __func__, d->irq, hw_irq, server, rc);
60}
61
62static unsigned int ics_opal_startup(struct irq_data *d)
63{
64 ics_opal_unmask_irq(d);
65 return 0;
66}
67
68static void ics_opal_mask_real_irq(unsigned int hw_irq)
69{
70 int server = ics_opal_mangle_server(xics_default_server);
71 int64_t rc;
72
73 if (hw_irq == XICS_IPI)
74 return;
75
76 /* Have to set XIVE to 0xff to be able to remove a slot */
77 rc = opal_set_xive(hw_irq, server, 0xff);
78 if (rc != OPAL_SUCCESS)
79 pr_err("%s: opal_set_xive(0xff) irq=%u returned %lld\n",
80 __func__, hw_irq, rc);
81}
82
83static void ics_opal_mask_irq(struct irq_data *d)
84{
85 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
86
87 pr_devel("ics-hal: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
88
89 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
90 return;
91 ics_opal_mask_real_irq(hw_irq);
92}
93
94static int ics_opal_set_affinity(struct irq_data *d,
95 const struct cpumask *cpumask,
96 bool force)
97{
98 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
99 __be16 oserver;
100 int16_t server;
101 int8_t priority;
102 int64_t rc;
103 int wanted_server;
104
105 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
106 return -1;
107
108 rc = opal_get_xive(hw_irq, &oserver, &priority);
109 if (rc != OPAL_SUCCESS) {
110 pr_err("%s: opal_get_xive(irq=%d [hw 0x%x]) error %lld\n",
111 __func__, d->irq, hw_irq, rc);
112 return -1;
113 }
114
115 wanted_server = xics_get_irq_server(d->irq, cpumask, 1);
116 if (wanted_server < 0) {
117 pr_warn("%s: No online cpus in the mask %*pb for irq %d\n",
118 __func__, cpumask_pr_args(cpumask), d->irq);
119 return -1;
120 }
121 server = ics_opal_mangle_server(wanted_server);
122
123 pr_debug("ics-hal: set-affinity irq %d [hw 0x%x] server: 0x%x/0x%x\n",
124 d->irq, hw_irq, wanted_server, server);
125
126 rc = opal_set_xive(hw_irq, server, priority);
127 if (rc != OPAL_SUCCESS) {
128 pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
129 " error %lld\n",
130 __func__, d->irq, hw_irq, server, rc);
131 return -1;
132 }
133 return IRQ_SET_MASK_OK;
134}
135
136static struct irq_chip ics_opal_irq_chip = {
137 .name = "OPAL ICS",
138 .irq_startup = ics_opal_startup,
139 .irq_mask = ics_opal_mask_irq,
140 .irq_unmask = ics_opal_unmask_irq,
141 .irq_eoi = NULL, /* Patched at init time */
142 .irq_set_affinity = ics_opal_set_affinity,
143 .irq_set_type = xics_set_irq_type,
144 .irq_retrigger = xics_retrigger,
145};
146
147static int ics_opal_host_match(struct ics *ics, struct device_node *node)
148{
149 return 1;
150}
151
152static int ics_opal_check(struct ics *ics, unsigned int hw_irq)
153{
154 int64_t rc;
155 __be16 server;
156 int8_t priority;
157
158 if (WARN_ON(hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS))
159 return -EINVAL;
160
161 /* Check if HAL knows about this interrupt */
162 rc = opal_get_xive(hw_irq, &server, &priority);
163 if (rc != OPAL_SUCCESS)
164 return -ENXIO;
165
166 return 0;
167}
168
169static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec)
170{
171 int64_t rc;
172 __be16 server;
173 int8_t priority;
174
175 /* Check if HAL knows about this interrupt */
176 rc = opal_get_xive(vec, &server, &priority);
177 if (rc != OPAL_SUCCESS)
178 return;
179
180 ics_opal_mask_real_irq(vec);
181}
182
183static long ics_opal_get_server(struct ics *ics, unsigned long vec)
184{
185 int64_t rc;
186 __be16 server;
187 int8_t priority;
188
189 /* Check if HAL knows about this interrupt */
190 rc = opal_get_xive(vec, &server, &priority);
191 if (rc != OPAL_SUCCESS)
192 return -1;
193 return ics_opal_unmangle_server(be16_to_cpu(server));
194}
195
196/* Only one global & state struct ics */
197static struct ics ics_hal = {
198 .check = ics_opal_check,
199 .mask_unknown = ics_opal_mask_unknown,
200 .get_server = ics_opal_get_server,
201 .host_match = ics_opal_host_match,
202 .chip = &ics_opal_irq_chip,
203};
204
205int __init ics_opal_init(void)
206{
207 if (!firmware_has_feature(FW_FEATURE_OPAL))
208 return -ENODEV;
209
210 /* We need to patch our irq chip's EOI to point to the
211 * right ICP
212 */
213 ics_opal_irq_chip.irq_eoi = icp_ops->eoi;
214
215 /* Register ourselves */
216 xics_register_ics(&ics_hal);
217
218 pr_info("ICS OPAL backend registered\n");
219
220 return 0;
221}