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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2016,2017 IBM Corporation.
4 */
5
6#define pr_fmt(fmt) "xive: " fmt
7
8#include <linux/types.h>
9#include <linux/threads.h>
10#include <linux/kernel.h>
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/debugfs.h>
14#include <linux/smp.h>
15#include <linux/interrupt.h>
16#include <linux/seq_file.h>
17#include <linux/init.h>
18#include <linux/cpu.h>
19#include <linux/of.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/msi.h>
23#include <linux/vmalloc.h>
24
25#include <asm/io.h>
26#include <asm/smp.h>
27#include <asm/machdep.h>
28#include <asm/irq.h>
29#include <asm/errno.h>
30#include <asm/xive.h>
31#include <asm/xive-regs.h>
32#include <asm/xmon.h>
33
34#include "xive-internal.h"
35
36#undef DEBUG_FLUSH
37#undef DEBUG_ALL
38
39#ifdef DEBUG_ALL
40#define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \
41 smp_processor_id(), ## __VA_ARGS__)
42#else
43#define DBG_VERBOSE(fmt...) do { } while(0)
44#endif
45
46bool __xive_enabled;
47EXPORT_SYMBOL_GPL(__xive_enabled);
48bool xive_cmdline_disabled;
49
50/* We use only one priority for now */
51static u8 xive_irq_priority;
52
53/* TIMA exported to KVM */
54void __iomem *xive_tima;
55EXPORT_SYMBOL_GPL(xive_tima);
56u32 xive_tima_offset;
57
58/* Backend ops */
59static const struct xive_ops *xive_ops;
60
61/* Our global interrupt domain */
62static struct irq_domain *xive_irq_domain;
63
64#ifdef CONFIG_SMP
65/* The IPIs use the same logical irq number when on the same chip */
66static struct xive_ipi_desc {
67 unsigned int irq;
68 char name[16];
69 atomic_t started;
70} *xive_ipis;
71
72/*
73 * Use early_cpu_to_node() for hot-plugged CPUs
74 */
75static unsigned int xive_ipi_cpu_to_irq(unsigned int cpu)
76{
77 if (!xive_ipis)
78 return XIVE_BAD_IRQ;
79 return xive_ipis[early_cpu_to_node(cpu)].irq;
80}
81#endif
82
83/* Xive state for each CPU */
84static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
85
86/* An invalid CPU target */
87#define XIVE_INVALID_TARGET (-1)
88
89/*
90 * Global toggle to switch on/off StoreEOI
91 */
92static bool xive_store_eoi = true;
93
94static bool xive_is_store_eoi(struct xive_irq_data *xd)
95{
96 return xd->flags & XIVE_IRQ_FLAG_STORE_EOI && xive_store_eoi;
97}
98
99/*
100 * Read the next entry in a queue, return its content if it's valid
101 * or 0 if there is no new entry.
102 *
103 * The queue pointer is moved forward unless "just_peek" is set
104 */
105static u32 xive_read_eq(struct xive_q *q, bool just_peek)
106{
107 u32 cur;
108
109 if (!q->qpage)
110 return 0;
111 cur = be32_to_cpup(q->qpage + q->idx);
112
113 /* Check valid bit (31) vs current toggle polarity */
114 if ((cur >> 31) == q->toggle)
115 return 0;
116
117 /* If consuming from the queue ... */
118 if (!just_peek) {
119 /* Next entry */
120 q->idx = (q->idx + 1) & q->msk;
121
122 /* Wrap around: flip valid toggle */
123 if (q->idx == 0)
124 q->toggle ^= 1;
125 }
126 /* Mask out the valid bit (31) */
127 return cur & 0x7fffffff;
128}
129
130/*
131 * Scans all the queue that may have interrupts in them
132 * (based on "pending_prio") in priority order until an
133 * interrupt is found or all the queues are empty.
134 *
135 * Then updates the CPPR (Current Processor Priority
136 * Register) based on the most favored interrupt found
137 * (0xff if none) and return what was found (0 if none).
138 *
139 * If just_peek is set, return the most favored pending
140 * interrupt if any but don't update the queue pointers.
141 *
142 * Note: This function can operate generically on any number
143 * of queues (up to 8). The current implementation of the XIVE
144 * driver only uses a single queue however.
145 *
146 * Note2: This will also "flush" "the pending_count" of a queue
147 * into the "count" when that queue is observed to be empty.
148 * This is used to keep track of the amount of interrupts
149 * targetting a queue. When an interrupt is moved away from
150 * a queue, we only decrement that queue count once the queue
151 * has been observed empty to avoid races.
152 */
153static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)
154{
155 u32 irq = 0;
156 u8 prio = 0;
157
158 /* Find highest pending priority */
159 while (xc->pending_prio != 0) {
160 struct xive_q *q;
161
162 prio = ffs(xc->pending_prio) - 1;
163 DBG_VERBOSE("scan_irq: trying prio %d\n", prio);
164
165 /* Try to fetch */
166 irq = xive_read_eq(&xc->queue[prio], just_peek);
167
168 /* Found something ? That's it */
169 if (irq) {
170 if (just_peek || irq_to_desc(irq))
171 break;
172 /*
173 * We should never get here; if we do then we must
174 * have failed to synchronize the interrupt properly
175 * when shutting it down.
176 */
177 pr_crit("xive: got interrupt %d without descriptor, dropping\n",
178 irq);
179 WARN_ON(1);
180 continue;
181 }
182
183 /* Clear pending bits */
184 xc->pending_prio &= ~(1 << prio);
185
186 /*
187 * Check if the queue count needs adjusting due to
188 * interrupts being moved away. See description of
189 * xive_dec_target_count()
190 */
191 q = &xc->queue[prio];
192 if (atomic_read(&q->pending_count)) {
193 int p = atomic_xchg(&q->pending_count, 0);
194 if (p) {
195 WARN_ON(p > atomic_read(&q->count));
196 atomic_sub(p, &q->count);
197 }
198 }
199 }
200
201 /* If nothing was found, set CPPR to 0xff */
202 if (irq == 0)
203 prio = 0xff;
204
205 /* Update HW CPPR to match if necessary */
206 if (prio != xc->cppr) {
207 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio);
208 xc->cppr = prio;
209 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio);
210 }
211
212 return irq;
213}
214
215/*
216 * This is used to perform the magic loads from an ESB
217 * described in xive-regs.h
218 */
219static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
220{
221 u64 val;
222
223 if (offset == XIVE_ESB_SET_PQ_10 && xive_is_store_eoi(xd))
224 offset |= XIVE_ESB_LD_ST_MO;
225
226 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
227 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
228 else
229 val = in_be64(xd->eoi_mmio + offset);
230
231 return (u8)val;
232}
233
234static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
235{
236 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
237 xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
238 else
239 out_be64(xd->eoi_mmio + offset, data);
240}
241
242#if defined(CONFIG_XMON) || defined(CONFIG_DEBUG_FS)
243static void xive_irq_data_dump(struct xive_irq_data *xd, char *buffer, size_t size)
244{
245 u64 val = xive_esb_read(xd, XIVE_ESB_GET);
246
247 snprintf(buffer, size, "flags=%c%c%c PQ=%c%c 0x%016llx 0x%016llx",
248 xive_is_store_eoi(xd) ? 'S' : ' ',
249 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
250 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
251 val & XIVE_ESB_VAL_P ? 'P' : '-',
252 val & XIVE_ESB_VAL_Q ? 'Q' : '-',
253 xd->trig_page, xd->eoi_page);
254}
255#endif
256
257#ifdef CONFIG_XMON
258static notrace void xive_dump_eq(const char *name, struct xive_q *q)
259{
260 u32 i0, i1, idx;
261
262 if (!q->qpage)
263 return;
264 idx = q->idx;
265 i0 = be32_to_cpup(q->qpage + idx);
266 idx = (idx + 1) & q->msk;
267 i1 = be32_to_cpup(q->qpage + idx);
268 xmon_printf("%s idx=%d T=%d %08x %08x ...", name,
269 q->idx, q->toggle, i0, i1);
270}
271
272notrace void xmon_xive_do_dump(int cpu)
273{
274 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
275
276 xmon_printf("CPU %d:", cpu);
277 if (xc) {
278 xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
279
280#ifdef CONFIG_SMP
281 {
282 char buffer[128];
283
284 xive_irq_data_dump(&xc->ipi_data, buffer, sizeof(buffer));
285 xmon_printf("IPI=0x%08x %s", xc->hw_ipi, buffer);
286 }
287#endif
288 xive_dump_eq("EQ", &xc->queue[xive_irq_priority]);
289 }
290 xmon_printf("\n");
291}
292
293static struct irq_data *xive_get_irq_data(u32 hw_irq)
294{
295 unsigned int irq = irq_find_mapping(xive_irq_domain, hw_irq);
296
297 return irq ? irq_get_irq_data(irq) : NULL;
298}
299
300int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d)
301{
302 int rc;
303 u32 target;
304 u8 prio;
305 u32 lirq;
306
307 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
308 if (rc) {
309 xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
310 return rc;
311 }
312
313 xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
314 hw_irq, target, prio, lirq);
315
316 if (!d)
317 d = xive_get_irq_data(hw_irq);
318
319 if (d) {
320 char buffer[128];
321
322 xive_irq_data_dump(irq_data_get_irq_chip_data(d),
323 buffer, sizeof(buffer));
324 xmon_printf("%s", buffer);
325 }
326
327 xmon_printf("\n");
328 return 0;
329}
330
331void xmon_xive_get_irq_all(void)
332{
333 unsigned int i;
334 struct irq_desc *desc;
335
336 for_each_irq_desc(i, desc) {
337 struct irq_data *d = irq_domain_get_irq_data(xive_irq_domain, i);
338
339 if (d)
340 xmon_xive_get_irq_config(irqd_to_hwirq(d), d);
341 }
342}
343
344#endif /* CONFIG_XMON */
345
346static unsigned int xive_get_irq(void)
347{
348 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
349 u32 irq;
350
351 /*
352 * This can be called either as a result of a HW interrupt or
353 * as a "replay" because EOI decided there was still something
354 * in one of the queues.
355 *
356 * First we perform an ACK cycle in order to update our mask
357 * of pending priorities. This will also have the effect of
358 * updating the CPPR to the most favored pending interrupts.
359 *
360 * In the future, if we have a way to differentiate a first
361 * entry (on HW interrupt) from a replay triggered by EOI,
362 * we could skip this on replays unless we soft-mask tells us
363 * that a new HW interrupt occurred.
364 */
365 xive_ops->update_pending(xc);
366
367 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);
368
369 /* Scan our queue(s) for interrupts */
370 irq = xive_scan_interrupts(xc, false);
371
372 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",
373 irq, xc->pending_prio);
374
375 /* Return pending interrupt if any */
376 if (irq == XIVE_BAD_IRQ)
377 return 0;
378 return irq;
379}
380
381/*
382 * After EOI'ing an interrupt, we need to re-check the queue
383 * to see if another interrupt is pending since multiple
384 * interrupts can coalesce into a single notification to the
385 * CPU.
386 *
387 * If we find that there is indeed more in there, we call
388 * force_external_irq_replay() to make Linux synthesize an
389 * external interrupt on the next call to local_irq_restore().
390 */
391static void xive_do_queue_eoi(struct xive_cpu *xc)
392{
393 if (xive_scan_interrupts(xc, true) != 0) {
394 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);
395 force_external_irq_replay();
396 }
397}
398
399/*
400 * EOI an interrupt at the source. There are several methods
401 * to do this depending on the HW version and source type
402 */
403static void xive_do_source_eoi(struct xive_irq_data *xd)
404{
405 u8 eoi_val;
406
407 xd->stale_p = false;
408
409 /* If the XIVE supports the new "store EOI facility, use it */
410 if (xive_is_store_eoi(xd)) {
411 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
412 return;
413 }
414
415 /*
416 * For LSIs, we use the "EOI cycle" special load rather than
417 * PQ bits, as they are automatically re-triggered in HW when
418 * still pending.
419 */
420 if (xd->flags & XIVE_IRQ_FLAG_LSI) {
421 xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
422 return;
423 }
424
425 /*
426 * Otherwise, we use the special MMIO that does a clear of
427 * both P and Q and returns the old Q. This allows us to then
428 * do a re-trigger if Q was set rather than synthesizing an
429 * interrupt in software
430 */
431 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
432 DBG_VERBOSE("eoi_val=%x\n", eoi_val);
433
434 /* Re-trigger if needed */
435 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
436 out_be64(xd->trig_mmio, 0);
437}
438
439/* irq_chip eoi callback, called with irq descriptor lock held */
440static void xive_irq_eoi(struct irq_data *d)
441{
442 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
443 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
444
445 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",
446 d->irq, irqd_to_hwirq(d), xc->pending_prio);
447
448 /*
449 * EOI the source if it hasn't been disabled and hasn't
450 * been passed-through to a KVM guest
451 */
452 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
453 !(xd->flags & XIVE_IRQ_FLAG_NO_EOI))
454 xive_do_source_eoi(xd);
455 else
456 xd->stale_p = true;
457
458 /*
459 * Clear saved_p to indicate that it's no longer occupying
460 * a queue slot on the target queue
461 */
462 xd->saved_p = false;
463
464 /* Check for more work in the queue */
465 xive_do_queue_eoi(xc);
466}
467
468/*
469 * Helper used to mask and unmask an interrupt source.
470 */
471static void xive_do_source_set_mask(struct xive_irq_data *xd,
472 bool mask)
473{
474 u64 val;
475
476 pr_debug("%s: HW 0x%x %smask\n", __func__, xd->hw_irq, mask ? "" : "un");
477
478 /*
479 * If the interrupt had P set, it may be in a queue.
480 *
481 * We need to make sure we don't re-enable it until it
482 * has been fetched from that queue and EOId. We keep
483 * a copy of that P state and use it to restore the
484 * ESB accordingly on unmask.
485 */
486 if (mask) {
487 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
488 if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P))
489 xd->saved_p = true;
490 xd->stale_p = false;
491 } else if (xd->saved_p) {
492 xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
493 xd->saved_p = false;
494 } else {
495 xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
496 xd->stale_p = false;
497 }
498}
499
500/*
501 * Try to chose "cpu" as a new interrupt target. Increments
502 * the queue accounting for that target if it's not already
503 * full.
504 */
505static bool xive_try_pick_target(int cpu)
506{
507 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
508 struct xive_q *q = &xc->queue[xive_irq_priority];
509 int max;
510
511 /*
512 * Calculate max number of interrupts in that queue.
513 *
514 * We leave a gap of 1 just in case...
515 */
516 max = (q->msk + 1) - 1;
517 return !!atomic_add_unless(&q->count, 1, max);
518}
519
520/*
521 * Un-account an interrupt for a target CPU. We don't directly
522 * decrement q->count since the interrupt might still be present
523 * in the queue.
524 *
525 * Instead increment a separate counter "pending_count" which
526 * will be substracted from "count" later when that CPU observes
527 * the queue to be empty.
528 */
529static void xive_dec_target_count(int cpu)
530{
531 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
532 struct xive_q *q = &xc->queue[xive_irq_priority];
533
534 if (WARN_ON(cpu < 0 || !xc)) {
535 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);
536 return;
537 }
538
539 /*
540 * We increment the "pending count" which will be used
541 * to decrement the target queue count whenever it's next
542 * processed and found empty. This ensure that we don't
543 * decrement while we still have the interrupt there
544 * occupying a slot.
545 */
546 atomic_inc(&q->pending_count);
547}
548
549/* Find a tentative CPU target in a CPU mask */
550static int xive_find_target_in_mask(const struct cpumask *mask,
551 unsigned int fuzz)
552{
553 int cpu, first;
554
555 /* Pick up a starting point CPU in the mask based on fuzz */
556 fuzz %= cpumask_weight(mask);
557 first = cpumask_nth(fuzz, mask);
558 WARN_ON(first >= nr_cpu_ids);
559
560 /*
561 * Now go through the entire mask until we find a valid
562 * target.
563 */
564 for_each_cpu_wrap(cpu, mask, first) {
565 if (cpu_online(cpu) && xive_try_pick_target(cpu))
566 return cpu;
567 }
568
569 WARN_ONCE(1, "target CPU not found in mask: %*pbl\n", cpumask_pr_args(mask));
570 return -1;
571}
572
573/*
574 * Pick a target CPU for an interrupt. This is done at
575 * startup or if the affinity is changed in a way that
576 * invalidates the current target.
577 */
578static int xive_pick_irq_target(struct irq_data *d,
579 const struct cpumask *affinity)
580{
581 static unsigned int fuzz;
582 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
583 cpumask_var_t mask;
584 int cpu = -1;
585
586 /*
587 * If we have chip IDs, first we try to build a mask of
588 * CPUs matching the CPU and find a target in there
589 */
590 if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
591 zalloc_cpumask_var(&mask, GFP_ATOMIC)) {
592 /* Build a mask of matching chip IDs */
593 for_each_cpu_and(cpu, affinity, cpu_online_mask) {
594 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
595 if (xc->chip_id == xd->src_chip)
596 cpumask_set_cpu(cpu, mask);
597 }
598 /* Try to find a target */
599 if (cpumask_empty(mask))
600 cpu = -1;
601 else
602 cpu = xive_find_target_in_mask(mask, fuzz++);
603 free_cpumask_var(mask);
604 if (cpu >= 0)
605 return cpu;
606 fuzz--;
607 }
608
609 /* No chip IDs, fallback to using the affinity mask */
610 return xive_find_target_in_mask(affinity, fuzz++);
611}
612
613static unsigned int xive_irq_startup(struct irq_data *d)
614{
615 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
616 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
617 int target, rc;
618
619 xd->saved_p = false;
620 xd->stale_p = false;
621
622 pr_debug("%s: irq %d [0x%x] data @%p\n", __func__, d->irq, hw_irq, d);
623
624 /* Pick a target */
625 target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d));
626 if (target == XIVE_INVALID_TARGET) {
627 /* Try again breaking affinity */
628 target = xive_pick_irq_target(d, cpu_online_mask);
629 if (target == XIVE_INVALID_TARGET)
630 return -ENXIO;
631 pr_warn("irq %d started with broken affinity\n", d->irq);
632 }
633
634 /* Sanity check */
635 if (WARN_ON(target == XIVE_INVALID_TARGET ||
636 target >= nr_cpu_ids))
637 target = smp_processor_id();
638
639 xd->target = target;
640
641 /*
642 * Configure the logical number to be the Linux IRQ number
643 * and set the target queue
644 */
645 rc = xive_ops->configure_irq(hw_irq,
646 get_hard_smp_processor_id(target),
647 xive_irq_priority, d->irq);
648 if (rc)
649 return rc;
650
651 /* Unmask the ESB */
652 xive_do_source_set_mask(xd, false);
653
654 return 0;
655}
656
657/* called with irq descriptor lock held */
658static void xive_irq_shutdown(struct irq_data *d)
659{
660 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
661 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
662
663 pr_debug("%s: irq %d [0x%x] data @%p\n", __func__, d->irq, hw_irq, d);
664
665 if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
666 return;
667
668 /* Mask the interrupt at the source */
669 xive_do_source_set_mask(xd, true);
670
671 /*
672 * Mask the interrupt in HW in the IVT/EAS and set the number
673 * to be the "bad" IRQ number
674 */
675 xive_ops->configure_irq(hw_irq,
676 get_hard_smp_processor_id(xd->target),
677 0xff, XIVE_BAD_IRQ);
678
679 xive_dec_target_count(xd->target);
680 xd->target = XIVE_INVALID_TARGET;
681}
682
683static void xive_irq_unmask(struct irq_data *d)
684{
685 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
686
687 pr_debug("%s: irq %d data @%p\n", __func__, d->irq, xd);
688
689 xive_do_source_set_mask(xd, false);
690}
691
692static void xive_irq_mask(struct irq_data *d)
693{
694 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
695
696 pr_debug("%s: irq %d data @%p\n", __func__, d->irq, xd);
697
698 xive_do_source_set_mask(xd, true);
699}
700
701static int xive_irq_set_affinity(struct irq_data *d,
702 const struct cpumask *cpumask,
703 bool force)
704{
705 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
706 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
707 u32 target, old_target;
708 int rc = 0;
709
710 pr_debug("%s: irq %d/0x%x\n", __func__, d->irq, hw_irq);
711
712 /* Is this valid ? */
713 if (!cpumask_intersects(cpumask, cpu_online_mask))
714 return -EINVAL;
715
716 /*
717 * If existing target is already in the new mask, and is
718 * online then do nothing.
719 */
720 if (xd->target != XIVE_INVALID_TARGET &&
721 cpu_online(xd->target) &&
722 cpumask_test_cpu(xd->target, cpumask))
723 return IRQ_SET_MASK_OK;
724
725 /* Pick a new target */
726 target = xive_pick_irq_target(d, cpumask);
727
728 /* No target found */
729 if (target == XIVE_INVALID_TARGET)
730 return -ENXIO;
731
732 /* Sanity check */
733 if (WARN_ON(target >= nr_cpu_ids))
734 target = smp_processor_id();
735
736 old_target = xd->target;
737
738 /*
739 * Only configure the irq if it's not currently passed-through to
740 * a KVM guest
741 */
742 if (!irqd_is_forwarded_to_vcpu(d))
743 rc = xive_ops->configure_irq(hw_irq,
744 get_hard_smp_processor_id(target),
745 xive_irq_priority, d->irq);
746 if (rc < 0) {
747 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq);
748 return rc;
749 }
750
751 pr_debug(" target: 0x%x\n", target);
752 xd->target = target;
753
754 /* Give up previous target */
755 if (old_target != XIVE_INVALID_TARGET)
756 xive_dec_target_count(old_target);
757
758 return IRQ_SET_MASK_OK;
759}
760
761static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type)
762{
763 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
764
765 /*
766 * We only support these. This has really no effect other than setting
767 * the corresponding descriptor bits mind you but those will in turn
768 * affect the resend function when re-enabling an edge interrupt.
769 *
770 * Set the default to edge as explained in map().
771 */
772 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
773 flow_type = IRQ_TYPE_EDGE_RISING;
774
775 if (flow_type != IRQ_TYPE_EDGE_RISING &&
776 flow_type != IRQ_TYPE_LEVEL_LOW)
777 return -EINVAL;
778
779 irqd_set_trigger_type(d, flow_type);
780
781 /*
782 * Double check it matches what the FW thinks
783 *
784 * NOTE: We don't know yet if the PAPR interface will provide
785 * the LSI vs MSI information apart from the device-tree so
786 * this check might have to move into an optional backend call
787 * that is specific to the native backend
788 */
789 if ((flow_type == IRQ_TYPE_LEVEL_LOW) !=
790 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
791 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",
792 d->irq, (u32)irqd_to_hwirq(d),
793 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge",
794 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
795 }
796
797 return IRQ_SET_MASK_OK_NOCOPY;
798}
799
800static int xive_irq_retrigger(struct irq_data *d)
801{
802 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
803
804 /* This should be only for MSIs */
805 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
806 return 0;
807
808 /*
809 * To perform a retrigger, we first set the PQ bits to
810 * 11, then perform an EOI.
811 */
812 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
813 xive_do_source_eoi(xd);
814
815 return 1;
816}
817
818/*
819 * Caller holds the irq descriptor lock, so this won't be called
820 * concurrently with xive_get_irqchip_state on the same interrupt.
821 */
822static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
823{
824 struct xive_irq_data *xd = irq_data_get_irq_chip_data(d);
825 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
826 int rc;
827 u8 pq;
828
829 /*
830 * This is called by KVM with state non-NULL for enabling
831 * pass-through or NULL for disabling it
832 */
833 if (state) {
834 irqd_set_forwarded_to_vcpu(d);
835
836 /* Set it to PQ=10 state to prevent further sends */
837 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
838 if (!xd->stale_p) {
839 xd->saved_p = !!(pq & XIVE_ESB_VAL_P);
840 xd->stale_p = !xd->saved_p;
841 }
842
843 /* No target ? nothing to do */
844 if (xd->target == XIVE_INVALID_TARGET) {
845 /*
846 * An untargetted interrupt should have been
847 * also masked at the source
848 */
849 WARN_ON(xd->saved_p);
850
851 return 0;
852 }
853
854 /*
855 * If P was set, adjust state to PQ=11 to indicate
856 * that a resend is needed for the interrupt to reach
857 * the guest. Also remember the value of P.
858 *
859 * This also tells us that it's in flight to a host queue
860 * or has already been fetched but hasn't been EOIed yet
861 * by the host. Thus it's potentially using up a host
862 * queue slot. This is important to know because as long
863 * as this is the case, we must not hard-unmask it when
864 * "returning" that interrupt to the host.
865 *
866 * This saved_p is cleared by the host EOI, when we know
867 * for sure the queue slot is no longer in use.
868 */
869 if (xd->saved_p) {
870 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
871
872 /*
873 * Sync the XIVE source HW to ensure the interrupt
874 * has gone through the EAS before we change its
875 * target to the guest. That should guarantee us
876 * that we *will* eventually get an EOI for it on
877 * the host. Otherwise there would be a small window
878 * for P to be seen here but the interrupt going
879 * to the guest queue.
880 */
881 if (xive_ops->sync_source)
882 xive_ops->sync_source(hw_irq);
883 }
884 } else {
885 irqd_clr_forwarded_to_vcpu(d);
886
887 /* No host target ? hard mask and return */
888 if (xd->target == XIVE_INVALID_TARGET) {
889 xive_do_source_set_mask(xd, true);
890 return 0;
891 }
892
893 /*
894 * Sync the XIVE source HW to ensure the interrupt
895 * has gone through the EAS before we change its
896 * target to the host.
897 */
898 if (xive_ops->sync_source)
899 xive_ops->sync_source(hw_irq);
900
901 /*
902 * By convention we are called with the interrupt in
903 * a PQ=10 or PQ=11 state, ie, it won't fire and will
904 * have latched in Q whether there's a pending HW
905 * interrupt or not.
906 *
907 * First reconfigure the target.
908 */
909 rc = xive_ops->configure_irq(hw_irq,
910 get_hard_smp_processor_id(xd->target),
911 xive_irq_priority, d->irq);
912 if (rc)
913 return rc;
914
915 /*
916 * Then if saved_p is not set, effectively re-enable the
917 * interrupt with an EOI. If it is set, we know there is
918 * still a message in a host queue somewhere that will be
919 * EOId eventually.
920 *
921 * Note: We don't check irqd_irq_disabled(). Effectively,
922 * we *will* let the irq get through even if masked if the
923 * HW is still firing it in order to deal with the whole
924 * saved_p business properly. If the interrupt triggers
925 * while masked, the generic code will re-mask it anyway.
926 */
927 if (!xd->saved_p)
928 xive_do_source_eoi(xd);
929
930 }
931 return 0;
932}
933
934/* Called with irq descriptor lock held. */
935static int xive_get_irqchip_state(struct irq_data *data,
936 enum irqchip_irq_state which, bool *state)
937{
938 struct xive_irq_data *xd = irq_data_get_irq_chip_data(data);
939 u8 pq;
940
941 switch (which) {
942 case IRQCHIP_STATE_ACTIVE:
943 pq = xive_esb_read(xd, XIVE_ESB_GET);
944
945 /*
946 * The esb value being all 1's means we couldn't get
947 * the PQ state of the interrupt through mmio. It may
948 * happen, for example when querying a PHB interrupt
949 * while the PHB is in an error state. We consider the
950 * interrupt to be inactive in that case.
951 */
952 *state = (pq != XIVE_ESB_INVALID) && !xd->stale_p &&
953 (xd->saved_p || (!!(pq & XIVE_ESB_VAL_P) &&
954 !irqd_irq_disabled(data)));
955 return 0;
956 default:
957 return -EINVAL;
958 }
959}
960
961static struct irq_chip xive_irq_chip = {
962 .name = "XIVE-IRQ",
963 .irq_startup = xive_irq_startup,
964 .irq_shutdown = xive_irq_shutdown,
965 .irq_eoi = xive_irq_eoi,
966 .irq_mask = xive_irq_mask,
967 .irq_unmask = xive_irq_unmask,
968 .irq_set_affinity = xive_irq_set_affinity,
969 .irq_set_type = xive_irq_set_type,
970 .irq_retrigger = xive_irq_retrigger,
971 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity,
972 .irq_get_irqchip_state = xive_get_irqchip_state,
973};
974
975bool is_xive_irq(struct irq_chip *chip)
976{
977 return chip == &xive_irq_chip;
978}
979EXPORT_SYMBOL_GPL(is_xive_irq);
980
981void xive_cleanup_irq_data(struct xive_irq_data *xd)
982{
983 pr_debug("%s for HW 0x%x\n", __func__, xd->hw_irq);
984
985 if (xd->eoi_mmio) {
986 iounmap(xd->eoi_mmio);
987 if (xd->eoi_mmio == xd->trig_mmio)
988 xd->trig_mmio = NULL;
989 xd->eoi_mmio = NULL;
990 }
991 if (xd->trig_mmio) {
992 iounmap(xd->trig_mmio);
993 xd->trig_mmio = NULL;
994 }
995}
996EXPORT_SYMBOL_GPL(xive_cleanup_irq_data);
997
998static struct xive_irq_data *xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw)
999{
1000 struct xive_irq_data *xd;
1001 int rc;
1002
1003 xd = kzalloc_obj(struct xive_irq_data);
1004 if (!xd)
1005 return ERR_PTR(-ENOMEM);
1006 rc = xive_ops->populate_irq_data(hw, xd);
1007 if (rc) {
1008 kfree(xd);
1009 return ERR_PTR(rc);
1010 }
1011 xd->target = XIVE_INVALID_TARGET;
1012
1013 /*
1014 * Turn OFF by default the interrupt being mapped. A side
1015 * effect of this check is the mapping the ESB page of the
1016 * interrupt in the Linux address space. This prevents page
1017 * fault issues in the crash handler which masks all
1018 * interrupts.
1019 */
1020 xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
1021
1022 return xd;
1023}
1024
1025static void xive_irq_free_data(struct irq_domain *domain, unsigned int virq)
1026{
1027 struct xive_irq_data *xd;
1028 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
1029
1030 if (!data)
1031 return;
1032
1033 xd = irq_data_get_irq_chip_data(data);
1034 if (!xd)
1035 return;
1036
1037 irq_domain_reset_irq_data(data);
1038 xive_cleanup_irq_data(xd);
1039 kfree(xd);
1040}
1041
1042#ifdef CONFIG_SMP
1043
1044static void xive_cause_ipi(int cpu)
1045{
1046 struct xive_cpu *xc;
1047 struct xive_irq_data *xd;
1048
1049 xc = per_cpu(xive_cpu, cpu);
1050
1051 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",
1052 smp_processor_id(), cpu, xc->hw_ipi);
1053
1054 xd = &xc->ipi_data;
1055 if (WARN_ON(!xd->trig_mmio))
1056 return;
1057 out_be64(xd->trig_mmio, 0);
1058}
1059
1060static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id)
1061{
1062 return smp_ipi_demux();
1063}
1064
1065static void xive_ipi_eoi(struct irq_data *d)
1066{
1067 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1068
1069 /* Handle possible race with unplug and drop stale IPIs */
1070 if (!xc)
1071 return;
1072
1073 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
1074 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
1075
1076 xive_do_source_eoi(&xc->ipi_data);
1077 xive_do_queue_eoi(xc);
1078}
1079
1080static void xive_ipi_do_nothing(struct irq_data *d)
1081{
1082 /*
1083 * Nothing to do, we never mask/unmask IPIs, but the callback
1084 * has to exist for the struct irq_chip.
1085 */
1086}
1087
1088static struct irq_chip xive_ipi_chip = {
1089 .name = "XIVE-IPI",
1090 .irq_eoi = xive_ipi_eoi,
1091 .irq_mask = xive_ipi_do_nothing,
1092 .irq_unmask = xive_ipi_do_nothing,
1093};
1094
1095/*
1096 * IPIs are marked per-cpu. We use separate HW interrupts under the
1097 * hood but associated with the same "linux" interrupt
1098 */
1099struct xive_ipi_alloc_info {
1100 irq_hw_number_t hwirq;
1101};
1102
1103static int xive_ipi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1104 unsigned int nr_irqs, void *arg)
1105{
1106 struct xive_ipi_alloc_info *info = arg;
1107 int i;
1108
1109 for (i = 0; i < nr_irqs; i++) {
1110 irq_domain_set_info(domain, virq + i, info->hwirq + i, &xive_ipi_chip,
1111 domain->host_data, handle_percpu_irq,
1112 NULL, NULL);
1113 }
1114 return 0;
1115}
1116
1117static const struct irq_domain_ops xive_ipi_irq_domain_ops = {
1118 .alloc = xive_ipi_irq_domain_alloc,
1119};
1120
1121static int __init xive_init_ipis(void)
1122{
1123 struct fwnode_handle *fwnode;
1124 struct irq_domain *ipi_domain;
1125 unsigned int node;
1126 int ret = -ENOMEM;
1127
1128 fwnode = irq_domain_alloc_named_fwnode("XIVE-IPI");
1129 if (!fwnode)
1130 goto out;
1131
1132 ipi_domain = irq_domain_create_linear(fwnode, nr_node_ids,
1133 &xive_ipi_irq_domain_ops, NULL);
1134 if (!ipi_domain)
1135 goto out_free_fwnode;
1136
1137 xive_ipis = kzalloc_objs(*xive_ipis, nr_node_ids);
1138 if (!xive_ipis)
1139 goto out_free_domain;
1140
1141 for_each_node(node) {
1142 struct xive_ipi_desc *xid = &xive_ipis[node];
1143 struct xive_ipi_alloc_info info = { node };
1144
1145 /*
1146 * Map one IPI interrupt per node for all cpus of that node.
1147 * Since the HW interrupt number doesn't have any meaning,
1148 * simply use the node number.
1149 */
1150 ret = irq_domain_alloc_irqs(ipi_domain, 1, node, &info);
1151 if (ret < 0)
1152 goto out_free_xive_ipis;
1153 xid->irq = ret;
1154
1155 snprintf(xid->name, sizeof(xid->name), "IPI-%d", node);
1156 }
1157
1158 return ret;
1159
1160out_free_xive_ipis:
1161 kfree(xive_ipis);
1162 xive_ipis = NULL;
1163out_free_domain:
1164 irq_domain_remove(ipi_domain);
1165out_free_fwnode:
1166 irq_domain_free_fwnode(fwnode);
1167out:
1168 return ret;
1169}
1170
1171static int xive_request_ipi(unsigned int cpu)
1172{
1173 struct xive_ipi_desc *xid = &xive_ipis[early_cpu_to_node(cpu)];
1174 int ret;
1175
1176 if (atomic_inc_return(&xid->started) > 1)
1177 return 0;
1178
1179 ret = request_irq(xid->irq, xive_muxed_ipi_action,
1180 IRQF_NO_DEBUG | IRQF_PERCPU | IRQF_NO_THREAD,
1181 xid->name, NULL);
1182
1183 WARN(ret < 0, "Failed to request IPI %d: %d\n", xid->irq, ret);
1184 return ret;
1185}
1186
1187static int xive_setup_cpu_ipi(unsigned int cpu)
1188{
1189 unsigned int xive_ipi_irq = xive_ipi_cpu_to_irq(cpu);
1190 struct xive_cpu *xc;
1191 int rc;
1192
1193 pr_debug("Setting up IPI for CPU %d\n", cpu);
1194
1195 if (xive_ipi_irq == XIVE_BAD_IRQ)
1196 return -EIO;
1197
1198 xc = per_cpu(xive_cpu, cpu);
1199
1200 /* Check if we are already setup */
1201 if (xc->hw_ipi != XIVE_BAD_IRQ)
1202 return 0;
1203
1204 /* Register the IPI */
1205 xive_request_ipi(cpu);
1206
1207 /* Grab an IPI from the backend, this will populate xc->hw_ipi */
1208 if (xive_ops->get_ipi(cpu, xc))
1209 return -EIO;
1210
1211 /*
1212 * Populate the IRQ data in the xive_cpu structure and
1213 * configure the HW / enable the IPIs.
1214 */
1215 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
1216 if (rc) {
1217 pr_err("Failed to populate IPI data on CPU %d\n", cpu);
1218 return -EIO;
1219 }
1220 rc = xive_ops->configure_irq(xc->hw_ipi,
1221 get_hard_smp_processor_id(cpu),
1222 xive_irq_priority, xive_ipi_irq);
1223 if (rc) {
1224 pr_err("Failed to map IPI CPU %d\n", cpu);
1225 return -EIO;
1226 }
1227 pr_debug("CPU %d HW IPI 0x%x, virq %d, trig_mmio=%p\n", cpu,
1228 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);
1229
1230 /* Unmask it */
1231 xive_do_source_set_mask(&xc->ipi_data, false);
1232
1233 return 0;
1234}
1235
1236noinstr static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
1237{
1238 unsigned int xive_ipi_irq = xive_ipi_cpu_to_irq(cpu);
1239
1240 /* Disable the IPI and free the IRQ data */
1241
1242 if (xive_ipi_irq == XIVE_BAD_IRQ)
1243 return;
1244
1245 /* Already cleaned up ? */
1246 if (xc->hw_ipi == XIVE_BAD_IRQ)
1247 return;
1248
1249 /* TODO: clear IPI mapping */
1250
1251 /* Mask the IPI */
1252 xive_do_source_set_mask(&xc->ipi_data, true);
1253
1254 /*
1255 * Note: We don't call xive_cleanup_irq_data() to free
1256 * the mappings as this is called from an IPI on kexec
1257 * which is not a safe environment to call iounmap()
1258 */
1259
1260 /* Deconfigure/mask in the backend */
1261 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
1262 0xff, xive_ipi_irq);
1263
1264 /* Free the IPIs in the backend */
1265 xive_ops->put_ipi(cpu, xc);
1266}
1267
1268int __init xive_smp_probe(void)
1269{
1270 int ret;
1271
1272 /* Register the IPI */
1273 ret = xive_init_ipis();
1274 if (ret < 0)
1275 return ret;
1276
1277 /* Allocate and setup IPI for the boot CPU */
1278 ret = xive_setup_cpu_ipi(smp_processor_id());
1279 if (ret < 0)
1280 return ret;
1281
1282 smp_ops->cause_ipi = xive_cause_ipi;
1283
1284 return 0;
1285}
1286
1287#endif /* CONFIG_SMP */
1288
1289static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
1290 irq_hw_number_t hw)
1291{
1292 struct xive_irq_data *xd;
1293
1294 /*
1295 * Mark interrupts as edge sensitive by default so that resend
1296 * actually works. Will fix that up below if needed.
1297 */
1298 irq_clear_status_flags(virq, IRQ_LEVEL);
1299
1300 xd = xive_irq_alloc_data(virq, hw);
1301 if (IS_ERR(xd))
1302 return PTR_ERR(xd);
1303
1304 irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq);
1305 irq_set_chip_data(virq, xd);
1306
1307 return 0;
1308}
1309
1310static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
1311{
1312 xive_irq_free_data(d, virq);
1313}
1314
1315static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct,
1316 const u32 *intspec, unsigned int intsize,
1317 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1318
1319{
1320 *out_hwirq = intspec[0];
1321
1322 /*
1323 * If intsize is at least 2, we look for the type in the second cell,
1324 * we assume the LSB indicates a level interrupt.
1325 */
1326 if (intsize > 1) {
1327 if (intspec[1] & 1)
1328 *out_flags = IRQ_TYPE_LEVEL_LOW;
1329 else
1330 *out_flags = IRQ_TYPE_EDGE_RISING;
1331 } else
1332 *out_flags = IRQ_TYPE_LEVEL_LOW;
1333
1334 return 0;
1335}
1336
1337static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
1338 enum irq_domain_bus_token bus_token)
1339{
1340 return xive_ops->match(node);
1341}
1342
1343#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1344static const char * const esb_names[] = { "RESET", "OFF", "PENDING", "QUEUED" };
1345
1346static const struct {
1347 u64 mask;
1348 char *name;
1349} xive_irq_flags[] = {
1350 { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
1351 { XIVE_IRQ_FLAG_LSI, "LSI" },
1352 { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
1353 { XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" },
1354};
1355
1356static void xive_irq_domain_debug_show(struct seq_file *m, struct irq_domain *d,
1357 struct irq_data *irqd, int ind)
1358{
1359 struct xive_irq_data *xd;
1360 u64 val;
1361 int i;
1362
1363 /* No IRQ domain level information. To be done */
1364 if (!irqd)
1365 return;
1366
1367 if (!is_xive_irq(irq_data_get_irq_chip(irqd)))
1368 return;
1369
1370 seq_printf(m, "%*sXIVE:\n", ind, "");
1371 ind++;
1372
1373 xd = irq_data_get_irq_chip_data(irqd);
1374 if (!xd) {
1375 seq_printf(m, "%*snot assigned\n", ind, "");
1376 return;
1377 }
1378
1379 val = xive_esb_read(xd, XIVE_ESB_GET);
1380 seq_printf(m, "%*sESB: %s\n", ind, "", esb_names[val & 0x3]);
1381 seq_printf(m, "%*sPstate: %s %s\n", ind, "", xd->stale_p ? "stale" : "",
1382 xd->saved_p ? "saved" : "");
1383 seq_printf(m, "%*sTarget: %d\n", ind, "", xd->target);
1384 seq_printf(m, "%*sChip: %d\n", ind, "", xd->src_chip);
1385 seq_printf(m, "%*sTrigger: 0x%016llx\n", ind, "", xd->trig_page);
1386 seq_printf(m, "%*sEOI: 0x%016llx\n", ind, "", xd->eoi_page);
1387 seq_printf(m, "%*sFlags: 0x%llx\n", ind, "", xd->flags);
1388 for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) {
1389 if (xd->flags & xive_irq_flags[i].mask)
1390 seq_printf(m, "%*s%s\n", ind + 12, "", xive_irq_flags[i].name);
1391 }
1392}
1393#endif
1394
1395#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1396static int xive_irq_domain_translate(struct irq_domain *d,
1397 struct irq_fwspec *fwspec,
1398 unsigned long *hwirq,
1399 unsigned int *type)
1400{
1401 return xive_irq_domain_xlate(d, to_of_node(fwspec->fwnode),
1402 fwspec->param, fwspec->param_count,
1403 hwirq, type);
1404}
1405
1406static int xive_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1407 unsigned int nr_irqs, void *arg)
1408{
1409 struct irq_fwspec *fwspec = arg;
1410 struct xive_irq_data *xd;
1411 irq_hw_number_t hwirq;
1412 unsigned int type = IRQ_TYPE_NONE;
1413 int i, rc;
1414
1415 rc = xive_irq_domain_translate(domain, fwspec, &hwirq, &type);
1416 if (rc)
1417 return rc;
1418
1419 pr_debug("%s %d/0x%lx #%d\n", __func__, virq, hwirq, nr_irqs);
1420
1421 for (i = 0; i < nr_irqs; i++) {
1422 /* TODO: call xive_irq_domain_map() */
1423
1424 /*
1425 * Mark interrupts as edge sensitive by default so that resend
1426 * actually works. Will fix that up below if needed.
1427 */
1428 irq_clear_status_flags(virq, IRQ_LEVEL);
1429
1430 /* allocates and sets handler data */
1431 xd = xive_irq_alloc_data(virq + i, hwirq + i);
1432 if (IS_ERR(xd))
1433 return PTR_ERR(xd);
1434
1435 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, &xive_irq_chip, xd);
1436 irq_set_handler(virq + i, handle_fasteoi_irq);
1437 }
1438
1439 return 0;
1440}
1441
1442static void xive_irq_domain_free(struct irq_domain *domain,
1443 unsigned int virq, unsigned int nr_irqs)
1444{
1445 int i;
1446
1447 pr_debug("%s %d #%d\n", __func__, virq, nr_irqs);
1448
1449 for (i = 0; i < nr_irqs; i++)
1450 xive_irq_free_data(domain, virq + i);
1451}
1452#endif
1453
1454static const struct irq_domain_ops xive_irq_domain_ops = {
1455#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1456 .alloc = xive_irq_domain_alloc,
1457 .free = xive_irq_domain_free,
1458 .translate = xive_irq_domain_translate,
1459#endif
1460 .match = xive_irq_domain_match,
1461 .map = xive_irq_domain_map,
1462 .unmap = xive_irq_domain_unmap,
1463 .xlate = xive_irq_domain_xlate,
1464#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
1465 .debug_show = xive_irq_domain_debug_show,
1466#endif
1467};
1468
1469static void __init xive_init_host(struct device_node *np)
1470{
1471 xive_irq_domain = irq_domain_create_tree(of_fwnode_handle(np), &xive_irq_domain_ops, NULL);
1472 if (WARN_ON(xive_irq_domain == NULL))
1473 return;
1474 irq_set_default_domain(xive_irq_domain);
1475}
1476
1477static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1478{
1479 if (xc->queue[xive_irq_priority].qpage)
1480 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
1481}
1482
1483static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1484{
1485 int rc = 0;
1486
1487 /* We setup 1 queues for now with a 64k page */
1488 if (!xc->queue[xive_irq_priority].qpage)
1489 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
1490
1491 return rc;
1492}
1493
1494static int xive_prepare_cpu(unsigned int cpu)
1495{
1496 struct xive_cpu *xc;
1497
1498 xc = per_cpu(xive_cpu, cpu);
1499 if (!xc) {
1500 xc = kzalloc_node(sizeof(struct xive_cpu),
1501 GFP_KERNEL, cpu_to_node(cpu));
1502 if (!xc)
1503 return -ENOMEM;
1504 xc->hw_ipi = XIVE_BAD_IRQ;
1505 xc->chip_id = XIVE_INVALID_CHIP_ID;
1506 if (xive_ops->prepare_cpu)
1507 xive_ops->prepare_cpu(cpu, xc);
1508
1509 per_cpu(xive_cpu, cpu) = xc;
1510 }
1511
1512 /* Setup EQs if not already */
1513 return xive_setup_cpu_queues(cpu, xc);
1514}
1515
1516static void xive_setup_cpu(void)
1517{
1518 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1519
1520 /* The backend might have additional things to do */
1521 if (xive_ops->setup_cpu)
1522 xive_ops->setup_cpu(smp_processor_id(), xc);
1523
1524 /* Set CPPR to 0xff to enable flow of interrupts */
1525 xc->cppr = 0xff;
1526 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1527}
1528
1529#ifdef CONFIG_SMP
1530void xive_smp_setup_cpu(void)
1531{
1532 pr_debug("SMP setup CPU %d\n", smp_processor_id());
1533
1534 /* This will have already been done on the boot CPU */
1535 if (smp_processor_id() != boot_cpuid)
1536 xive_setup_cpu();
1537
1538}
1539
1540int xive_smp_prepare_cpu(unsigned int cpu)
1541{
1542 int rc;
1543
1544 /* Allocate per-CPU data and queues */
1545 rc = xive_prepare_cpu(cpu);
1546 if (rc)
1547 return rc;
1548
1549 /* Allocate and setup IPI for the new CPU */
1550 return xive_setup_cpu_ipi(cpu);
1551}
1552
1553#ifdef CONFIG_HOTPLUG_CPU
1554static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
1555{
1556 u32 irq;
1557
1558 /* We assume local irqs are disabled */
1559 WARN_ON(!irqs_disabled());
1560
1561 /* Check what's already in the CPU queue */
1562 while ((irq = xive_scan_interrupts(xc, false)) != 0) {
1563 /*
1564 * We need to re-route that interrupt to its new destination.
1565 * First get and lock the descriptor
1566 */
1567 struct irq_desc *desc = irq_to_desc(irq);
1568 struct irq_data *d = irq_desc_get_irq_data(desc);
1569 struct xive_irq_data *xd;
1570
1571 /*
1572 * Ignore anything that isn't a XIVE irq and ignore
1573 * IPIs, so can just be dropped.
1574 */
1575 if (d->domain != xive_irq_domain)
1576 continue;
1577
1578 /*
1579 * The IRQ should have already been re-routed, it's just a
1580 * stale in the old queue, so re-trigger it in order to make
1581 * it reach is new destination.
1582 */
1583#ifdef DEBUG_FLUSH
1584 pr_info("CPU %d: Got irq %d while offline, re-sending...\n",
1585 cpu, irq);
1586#endif
1587 raw_spin_lock(&desc->lock);
1588 xd = irq_desc_get_chip_data(desc);
1589
1590 /*
1591 * Clear saved_p to indicate that it's no longer pending
1592 */
1593 xd->saved_p = false;
1594
1595 /*
1596 * For LSIs, we EOI, this will cause a resend if it's
1597 * still asserted. Otherwise do an MSI retrigger.
1598 */
1599 if (xd->flags & XIVE_IRQ_FLAG_LSI)
1600 xive_do_source_eoi(xd);
1601 else
1602 xive_irq_retrigger(d);
1603
1604 raw_spin_unlock(&desc->lock);
1605 }
1606}
1607
1608void xive_smp_disable_cpu(void)
1609{
1610 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1611 unsigned int cpu = smp_processor_id();
1612
1613 /* Migrate interrupts away from the CPU */
1614 irq_migrate_all_off_this_cpu();
1615
1616 /* Set CPPR to 0 to disable flow of interrupts */
1617 xc->cppr = 0;
1618 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1619
1620 /* Flush everything still in the queue */
1621 xive_flush_cpu_queue(cpu, xc);
1622
1623 /* Re-enable CPPR */
1624 xc->cppr = 0xff;
1625 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1626}
1627
1628void xive_flush_interrupt(void)
1629{
1630 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1631 unsigned int cpu = smp_processor_id();
1632
1633 /* Called if an interrupt occurs while the CPU is hot unplugged */
1634 xive_flush_cpu_queue(cpu, xc);
1635}
1636
1637#endif /* CONFIG_HOTPLUG_CPU */
1638
1639#endif /* CONFIG_SMP */
1640
1641noinstr void xive_teardown_cpu(void)
1642{
1643 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1644 unsigned int cpu = smp_processor_id();
1645
1646 /* Set CPPR to 0 to disable flow of interrupts */
1647 xc->cppr = 0;
1648 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1649
1650 if (xive_ops->teardown_cpu)
1651 xive_ops->teardown_cpu(cpu, xc);
1652
1653#ifdef CONFIG_SMP
1654 /* Get rid of IPI */
1655 xive_cleanup_cpu_ipi(cpu, xc);
1656#endif
1657
1658 /* Disable and free the queues */
1659 xive_cleanup_cpu_queues(cpu, xc);
1660}
1661
1662void xive_shutdown(void)
1663{
1664 xive_ops->shutdown();
1665}
1666
1667bool __init xive_core_init(struct device_node *np, const struct xive_ops *ops,
1668 void __iomem *area, u32 offset, u8 max_prio)
1669{
1670 xive_tima = area;
1671 xive_tima_offset = offset;
1672 xive_ops = ops;
1673 xive_irq_priority = max_prio;
1674
1675 ppc_md.get_irq = xive_get_irq;
1676 __xive_enabled = true;
1677
1678 pr_debug("Initializing host..\n");
1679 xive_init_host(np);
1680
1681 pr_debug("Initializing boot CPU..\n");
1682
1683 /* Allocate per-CPU data and queues */
1684 xive_prepare_cpu(smp_processor_id());
1685
1686 /* Get ready for interrupts */
1687 xive_setup_cpu();
1688
1689 pr_info("Interrupt handling initialized with %s backend\n",
1690 xive_ops->name);
1691 pr_info("Using priority %d for all interrupts\n", max_prio);
1692
1693 return true;
1694}
1695
1696__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift)
1697{
1698 unsigned int alloc_order;
1699 struct page *pages;
1700 __be32 *qpage;
1701
1702 alloc_order = xive_alloc_order(queue_shift);
1703 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
1704 if (!pages)
1705 return ERR_PTR(-ENOMEM);
1706 qpage = (__be32 *)page_address(pages);
1707 memset(qpage, 0, 1 << queue_shift);
1708
1709 return qpage;
1710}
1711
1712static int __init xive_off(char *arg)
1713{
1714 xive_cmdline_disabled = true;
1715 return 1;
1716}
1717__setup("xive=off", xive_off);
1718
1719static int __init xive_store_eoi_cmdline(char *arg)
1720{
1721 if (!arg)
1722 return 1;
1723
1724 if (strncmp(arg, "off", 3) == 0) {
1725 pr_info("StoreEOI disabled on kernel command line\n");
1726 xive_store_eoi = false;
1727 }
1728 return 1;
1729}
1730__setup("xive.store-eoi=", xive_store_eoi_cmdline);
1731
1732#ifdef CONFIG_DEBUG_FS
1733static void xive_debug_show_ipi(struct seq_file *m, int cpu)
1734{
1735 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
1736
1737 seq_printf(m, "CPU %d: ", cpu);
1738 if (xc) {
1739 seq_printf(m, "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
1740
1741#ifdef CONFIG_SMP
1742 {
1743 char buffer[128];
1744
1745 xive_irq_data_dump(&xc->ipi_data, buffer, sizeof(buffer));
1746 seq_printf(m, "IPI=0x%08x %s", xc->hw_ipi, buffer);
1747 }
1748#endif
1749 }
1750 seq_puts(m, "\n");
1751}
1752
1753static void xive_debug_show_irq(struct seq_file *m, struct irq_data *d)
1754{
1755 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1756 int rc;
1757 u32 target;
1758 u8 prio;
1759 u32 lirq;
1760 char buffer[128];
1761
1762 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
1763 if (rc) {
1764 seq_printf(m, "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
1765 return;
1766 }
1767
1768 seq_printf(m, "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
1769 hw_irq, target, prio, lirq);
1770
1771 xive_irq_data_dump(irq_data_get_irq_chip_data(d), buffer, sizeof(buffer));
1772 seq_puts(m, buffer);
1773 seq_puts(m, "\n");
1774}
1775
1776static int xive_irq_debug_show(struct seq_file *m, void *private)
1777{
1778 unsigned int i;
1779 struct irq_desc *desc;
1780
1781 for_each_irq_desc(i, desc) {
1782 struct irq_data *d = irq_domain_get_irq_data(xive_irq_domain, i);
1783
1784 if (d)
1785 xive_debug_show_irq(m, d);
1786 }
1787 return 0;
1788}
1789DEFINE_SHOW_ATTRIBUTE(xive_irq_debug);
1790
1791static int xive_ipi_debug_show(struct seq_file *m, void *private)
1792{
1793 int cpu;
1794
1795 if (xive_ops->debug_show)
1796 xive_ops->debug_show(m, private);
1797
1798 for_each_online_cpu(cpu)
1799 xive_debug_show_ipi(m, cpu);
1800 return 0;
1801}
1802DEFINE_SHOW_ATTRIBUTE(xive_ipi_debug);
1803
1804static void xive_eq_debug_show_one(struct seq_file *m, struct xive_q *q, u8 prio)
1805{
1806 int i;
1807
1808 seq_printf(m, "EQ%d idx=%d T=%d\n", prio, q->idx, q->toggle);
1809 if (q->qpage) {
1810 for (i = 0; i < q->msk + 1; i++) {
1811 if (!(i % 8))
1812 seq_printf(m, "%05d ", i);
1813 seq_printf(m, "%08x%s", be32_to_cpup(q->qpage + i),
1814 (i + 1) % 8 ? " " : "\n");
1815 }
1816 }
1817 seq_puts(m, "\n");
1818}
1819
1820static int xive_eq_debug_show(struct seq_file *m, void *private)
1821{
1822 int cpu = (long)m->private;
1823 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
1824
1825 if (xc)
1826 xive_eq_debug_show_one(m, &xc->queue[xive_irq_priority],
1827 xive_irq_priority);
1828 return 0;
1829}
1830DEFINE_SHOW_ATTRIBUTE(xive_eq_debug);
1831
1832static void xive_core_debugfs_create(void)
1833{
1834 struct dentry *xive_dir;
1835 struct dentry *xive_eq_dir;
1836 long cpu;
1837 char name[16];
1838
1839 xive_dir = debugfs_create_dir("xive", arch_debugfs_dir);
1840 if (IS_ERR(xive_dir))
1841 return;
1842
1843 debugfs_create_file("ipis", 0400, xive_dir,
1844 NULL, &xive_ipi_debug_fops);
1845 debugfs_create_file("interrupts", 0400, xive_dir,
1846 NULL, &xive_irq_debug_fops);
1847 xive_eq_dir = debugfs_create_dir("eqs", xive_dir);
1848 for_each_possible_cpu(cpu) {
1849 snprintf(name, sizeof(name), "cpu%ld", cpu);
1850 debugfs_create_file(name, 0400, xive_eq_dir, (void *)cpu,
1851 &xive_eq_debug_fops);
1852 }
1853 debugfs_create_bool("store-eoi", 0600, xive_dir, &xive_store_eoi);
1854
1855 if (xive_ops->debug_create)
1856 xive_ops->debug_create(xive_dir);
1857}
1858#else
1859static inline void xive_core_debugfs_create(void) { }
1860#endif /* CONFIG_DEBUG_FS */
1861
1862int xive_core_debug_init(void)
1863{
1864 if (xive_enabled() && IS_ENABLED(CONFIG_DEBUG_FS))
1865 xive_core_debugfs_create();
1866
1867 return 0;
1868}