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| 2 | |
| 3 | * Copyright (C) 2015 Regents of the University of California
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| 4 |
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| 5 |
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| 6 | #ifndef _ASM_RISCV_CACHEFLUSH_H
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| 7 | #define _ASM_RISCV_CACHEFLUSH_H
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| 8 |
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| 9 | #include <linux/mm.h>
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| 10 |
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| 11 | static inline void local_flush_icache_all(void)
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| 12 | {
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| 13 | asm volatile ("fence.i" ::: "memory");
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| 14 | }
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| 15 |
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| 16 | static inline void local_flush_icache_range(unsigned long start,
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| 17 | unsigned long end)
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| 18 | {
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| 19 | local_flush_icache_all();
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| 20 | }
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| 21 |
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| 22 | #define PG_dcache_clean PG_arch_1
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| 23 |
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| 24 | static inline void flush_dcache_folio(struct folio *folio)
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| 25 | {
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| 26 | if (test_bit(PG_dcache_clean, &folio->flags.f))
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| 27 | clear_bit(PG_dcache_clean, &folio->flags.f);
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| 28 | }
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| 29 | #define flush_dcache_folio flush_dcache_folio
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| 30 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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| 31 |
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| 32 | static inline void flush_dcache_page(struct page *page)
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| 33 | {
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| 34 | flush_dcache_folio(page_folio(page));
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| 35 | }
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| 36 |
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| 37 | #define flush_icache_user_page(vma, pg, addr, len) \
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| 38 | do { \
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| 39 | if (vma->vm_flags & VM_EXEC) \
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| 40 | flush_icache_mm(vma->vm_mm, 0); \
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| 41 | } while (0)
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| 42 |
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| 43 | #if defined(CONFIG_64BIT) && defined(CONFIG_MMU)
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| 44 |
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| 45 | extern DECLARE_BITMAP(new_valid_map_cpus, NR_CPUS);
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| 46 | extern char _end[];
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| 47 | static inline void mark_new_valid_map(void)
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| 48 | {
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| 49 | |
| 50 | * We don't care if concurrently a cpu resets this value since
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| 51 | * the only place this can happen is in handle_exception() where
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| 52 | * an sfence.vma is emitted.
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| 53 |
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| 54 | bitmap_fill(new_valid_map_cpus, NR_CPUS);
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| 55 | }
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| 56 | #define flush_cache_vmap flush_cache_vmap
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| 57 | static inline void flush_cache_vmap(unsigned long start, unsigned long end)
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| 58 | {
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| 59 | if (is_vmalloc_or_module_addr((void *)start) ||
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| 60 | (start >= VMEMMAP_START && end <= VMEMMAP_END))
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| 61 | mark_new_valid_map();
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| 62 | }
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| 63 | #define flush_cache_vmap_early(start, end) local_flush_tlb_kernel_range(start, end)
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| 64 | #endif
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| 65 |
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| 66 | #ifndef CONFIG_SMP
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| 67 |
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| 68 | #define flush_icache_all() local_flush_icache_all()
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| 69 | #define flush_icache_mm(mm, local) flush_icache_all()
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| 70 |
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| 71 | #else
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| 72 |
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| 73 | void flush_icache_all(void);
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| 74 | void flush_icache_mm(struct mm_struct *mm, bool local);
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| 75 |
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| 76 | #endif
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| 77 |
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| 78 | |
| 79 | * RISC-V doesn't have an instruction to flush parts of the instruction cache,
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| 80 | * so instead we just flush the whole thing.
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| 81 |
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| 82 | #define flush_icache_range flush_icache_range
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| 83 | static inline void flush_icache_range(unsigned long start, unsigned long end)
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| 84 | {
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| 85 | flush_icache_all();
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| 86 | }
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| 87 |
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| 88 | extern unsigned int riscv_cbom_block_size;
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| 89 | extern unsigned int riscv_cboz_block_size;
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| 90 | extern unsigned int riscv_cbop_block_size;
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| 91 | void riscv_init_cbo_blocksizes(void);
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| 92 |
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| 93 | #ifdef CONFIG_RISCV_DMA_NONCOHERENT
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| 94 | void riscv_noncoherent_supported(void);
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| 95 | void __init riscv_set_dma_cache_alignment(void);
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| 96 | #else
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| 97 | static inline void riscv_noncoherent_supported(void) {}
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| 98 | static inline void riscv_set_dma_cache_alignment(void) {}
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| 99 | #endif
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| 100 |
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| 101 | |
| 102 | * Bits in sys_riscv_flush_icache()'s flags argument.
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| 103 |
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| 104 | #define SYS_RISCV_FLUSH_ICACHE_LOCAL 1UL
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| 105 | #define SYS_RISCV_FLUSH_ICACHE_ALL (SYS_RISCV_FLUSH_ICACHE_LOCAL)
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| 106 |
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| 107 | #include <asm-generic/cacheflush.h>
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| 108 |
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| 109 | #endif
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