| 1 |
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| 2 | #ifndef _ASM_RISCV_SYNC_CORE_H
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| 3 | #define _ASM_RISCV_SYNC_CORE_H
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| 4 |
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| 5 | |
| 6 | * RISC-V implements return to user-space through an xRET instruction,
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| 7 | * which is not core serializing.
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| 8 |
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| 9 | static inline void sync_core_before_usermode(void)
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| 10 | {
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| 11 | asm volatile ("fence.i" ::: "memory");
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| 12 | }
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| 13 |
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| 14 | #ifdef CONFIG_SMP
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| 15 | |
| 16 | * Ensure the next switch_mm() on every CPU issues a core serializing
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| 17 | * instruction for the given @mm.
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| 18 |
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| 19 | static inline void prepare_sync_core_cmd(struct mm_struct *mm)
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| 20 | {
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| 21 | cpumask_setall(&mm->context.icache_stale_mask);
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| 22 | }
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| 23 | #else
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| 24 | static inline void prepare_sync_core_cmd(struct mm_struct *mm)
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| 25 | {
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| 26 | }
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| 27 | #endif
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| 28 |
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| 29 | #endif
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