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| 2 | #ifndef __ASM_SH_AUXVEC_H
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| 3 | #define __ASM_SH_AUXVEC_H
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| 4 |
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| 5 | |
| 6 | * Architecture-neutral AT_ values in 0-17, leave some room
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| 7 | * for more of them.
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| 8 |
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| 9 |
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| 10 | |
| 11 | * This entry gives some information about the FPU initialization
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| 12 | * performed by the kernel.
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| 13 |
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| 14 | #define AT_FPUCW 18
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| 15 |
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| 16 | |
| 17 | * The entry point to the vsyscall page gets placed here.
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| 18 |
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| 19 | #define AT_SYSINFO_EHDR 33
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| 20 |
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| 21 | |
| 22 | * More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the
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| 23 | * value is -1, then the cache doesn't exist. Otherwise:
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| 24 | *
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| 25 | * bit 0-3: Cache set-associativity; 0 means fully associative.
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| 26 | * bit 4-7: Log2 of cacheline size.
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| 27 | * bit 8-31: Size of the entire cache >> 8.
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| 28 |
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| 29 | #define AT_L1I_CACHESHAPE 34
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| 30 | #define AT_L1D_CACHESHAPE 35
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| 31 | #define AT_L2_CACHESHAPE 36
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| 32 |
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| 33 | #define AT_VECTOR_SIZE_ARCH 5
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| 34 |
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| 35 | #endif
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