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| 2 | |
| 3 | * timer.h: Definitions for the timer chips on the Sparc.
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| 4 | *
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| 5 | * Copyright (C) 1995 David S. Miller ([email protected])
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| 6 |
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| 7 |
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| 8 |
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| 9 | #ifndef _SPARC_TIMER_H
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| 10 | #define _SPARC_TIMER_H
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| 11 |
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| 12 | #include <linux/clocksource.h>
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| 13 | #include <linux/irqreturn.h>
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| 14 |
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| 15 | #include <asm-generic/percpu.h>
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| 16 |
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| 17 | #include <asm/cpu_type.h>
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| 18 |
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| 19 | #define SBUS_CLOCK_RATE 2000000
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| 20 | #define TIMER_VALUE_SHIFT 9
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| 21 | #define TIMER_VALUE_MASK 0x3fffff
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| 22 | #define TIMER_LIMIT_BIT (1 << 31)
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| 23 |
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| 24 | |
| 25 | * From sun4m manual:
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| 26 | * When a counter reaches the value in the corresponding limit register,
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| 27 | * the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200).
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| 28 | *
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| 29 | * To compensate for this add one to the value.
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| 30 |
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| 31 | static inline unsigned int timer_value(unsigned int value)
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| 32 | {
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| 33 | return (value + 1) << TIMER_VALUE_SHIFT;
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| 34 | }
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| 35 |
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| 36 | extern volatile u32 __iomem *master_l10_counter;
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| 37 |
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| 38 | irqreturn_t notrace timer_interrupt(int dummy, void *dev_id);
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| 39 |
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| 40 | #ifdef CONFIG_SMP
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| 41 | DECLARE_PER_CPU(struct clock_event_device, sparc32_clockevent);
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| 42 | void register_percpu_ce(int cpu);
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| 43 | #endif
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| 44 |
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| 45 | #endif
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