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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_PROCESSOR_H
3#define _ASM_X86_PROCESSOR_H
4
5#include <asm/processor-flags.h>
6
7/* Forward declaration, a strange C thing */
8struct task_struct;
9struct mm_struct;
10struct io_bitmap;
11struct vm86;
12
13#include <asm/ptrace.h>
14#include <asm/segment.h>
15#include <asm/types.h>
16#include <uapi/asm/sigcontext.h>
17#include <asm/current.h>
18#include <asm/cpufeatures.h>
19#include <asm/cpuid/types.h>
20#include <asm/page.h>
21#include <asm/pgtable_types.h>
22#include <asm/percpu.h>
23#include <asm/desc_defs.h>
24#include <asm/nops.h>
25#include <asm/special_insns.h>
26#include <asm/fpu/types.h>
27#include <asm/unwind_hints.h>
28#include <asm/vmxfeatures.h>
29#include <asm/vdso/processor.h>
30#include <asm/shstk.h>
31
32#include <linux/personality.h>
33#include <linux/cache.h>
34#include <linux/threads.h>
35#include <linux/math64.h>
36#include <linux/err.h>
37#include <linux/irqflags.h>
38#include <linux/mem_encrypt.h>
39
40/*
41 * We handle most unaligned accesses in hardware. On the other hand
42 * unaligned DMA can be quite expensive on some Nehalem processors.
43 *
44 * Based on this we disable the IP header alignment in network drivers.
45 */
46#define NET_IP_ALIGN 0
47
48#define HBP_NUM 4
49
50/*
51 * These alignment constraints are for performance in the vSMP case,
52 * but in the task_struct case we must also meet hardware imposed
53 * alignment requirements of the FPU state:
54 */
55#ifdef CONFIG_X86_VSMP
56# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
57# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
58#else
59# define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
60# define ARCH_MIN_MMSTRUCT_ALIGN 0
61#endif
62
63extern u16 __read_mostly tlb_lli_4k;
64extern u16 __read_mostly tlb_lli_2m;
65extern u16 __read_mostly tlb_lli_4m;
66extern u16 __read_mostly tlb_lld_4k;
67extern u16 __read_mostly tlb_lld_2m;
68extern u16 __read_mostly tlb_lld_4m;
69extern u16 __read_mostly tlb_lld_1g;
70
71enum x86_topology_cpu_type {
72 /* X86_CPU_TYPE_ANY */
73 TOPO_CPU_TYPE_ANY = 0,
74 TOPO_CPU_TYPE_PERFORMANCE,
75 TOPO_CPU_TYPE_EFFICIENCY,
76 TOPO_CPU_TYPE_LOW_POWER,
77 TOPO_CPU_TYPE_UNKNOWN,
78};
79
80struct cpuinfo_topology {
81 // Real APIC ID read from the local APIC
82 u32 apicid;
83 // The initial APIC ID provided by CPUID
84 u32 initial_apicid;
85
86 // Physical package ID
87 u32 pkg_id;
88
89 // Physical die ID on AMD, Relative on Intel
90 u32 die_id;
91
92 // Compute unit ID - AMD specific
93 u32 cu_id;
94
95 // Core ID relative to the package
96 u32 core_id;
97
98 // Logical ID mappings
99 u32 logical_pkg_id;
100 u32 logical_die_id;
101 u32 logical_core_id;
102
103 // AMD Node ID and Nodes per Package info
104 u32 amd_node_id;
105
106 // Cache level topology IDs
107 u32 llc_id;
108 u32 l2c_id;
109
110 // Hardware defined CPU-type
111 union {
112 u32 hw_cpu_type;
113 struct {
114 // CPUID.1A.EAX[23-0]
115 u32 intel_native_model_id :24;
116 // CPUID.1A.EAX[31-24]
117 u32 intel_type :8;
118 };
119 struct {
120 // CPUID 0x80000026.EBX
121 u32 amd_num_processors :16,
122 amd_power_eff_ranking :8,
123 amd_native_model_id :4,
124 amd_type :4;
125 };
126 };
127
128 // Linux vendor-agnostic CPU type
129 enum x86_topology_cpu_type cpu_type;
130};
131
132/*
133 * CPU type and hardware bug flags. Kept separately for each CPU.
134 */
135struct cpuinfo_x86 {
136 union {
137 /*
138 * The particular ordering (low-to-high) of (vendor,
139 * family, model) is done in case range of models, like
140 * it is usually done on AMD, need to be compared.
141 */
142 struct {
143 __u8 x86_model;
144 /* CPU family */
145 __u8 x86;
146 /* CPU vendor */
147 __u8 x86_vendor;
148 __u8 x86_reserved;
149 };
150 /* combined vendor, family, model */
151 __u32 x86_vfm;
152 };
153 __u8 x86_stepping;
154 union {
155 // MSR_IA32_PLATFORM_ID[52-50]
156 __u8 intel_platform_id;
157 __u8 amd_unused;
158 };
159#ifdef CONFIG_X86_64
160 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
161 int x86_tlbsize;
162#endif
163#ifdef CONFIG_X86_VMX_FEATURE_NAMES
164 __u32 vmx_capability[NVMXINTS];
165#endif
166 __u8 x86_virt_bits;
167 __u8 x86_phys_bits;
168 /* Max extended CPUID function supported: */
169 __u32 extended_cpuid_level;
170 /* Maximum supported CPUID level, -1=no CPUID: */
171 int cpuid_level;
172 /*
173 * Align to size of unsigned long because the x86_capability array
174 * is passed to bitops which require the alignment. Use unnamed
175 * union to enforce the array is aligned to size of unsigned long.
176 */
177 union {
178 __u32 x86_capability[NCAPINTS + NBUGINTS];
179 unsigned long x86_capability_alignment;
180 };
181 char x86_vendor_id[16];
182 char x86_model_id[64];
183 struct cpuinfo_topology topo;
184 struct cpuid_table cpuid;
185 /* in KB - valid for CPUS which support this call: */
186 unsigned int x86_cache_size;
187 int x86_cache_alignment; /* In bytes */
188 /* Cache QoS architectural values, valid only on the BSP: */
189 int x86_cache_max_rmid; /* max index */
190 int x86_cache_occ_scale; /* scale to bytes */
191 int x86_cache_mbm_width_offset;
192 int x86_power;
193 unsigned long loops_per_jiffy;
194 /* protected processor identification number */
195 u64 ppin;
196 u16 x86_clflush_size;
197 /* number of cores as seen by the OS: */
198 u16 booted_cores;
199 /* Index into per_cpu list: */
200 u16 cpu_index;
201 /* Is SMT active on this core? */
202 bool smt_active;
203 u32 microcode;
204 /* Address space bits used by the cache internally */
205 u8 x86_cache_bits;
206 unsigned initialized : 1;
207} __randomize_layout;
208
209#define X86_VENDOR_INTEL 0
210#define X86_VENDOR_CYRIX 1
211#define X86_VENDOR_AMD 2
212#define X86_VENDOR_UMC 3
213#define X86_VENDOR_CENTAUR 5
214#define X86_VENDOR_TRANSMETA 7
215#define X86_VENDOR_NSC 8
216#define X86_VENDOR_HYGON 9
217#define X86_VENDOR_ZHAOXIN 10
218#define X86_VENDOR_VORTEX 11
219#define X86_VENDOR_NUM 12
220
221#define X86_VENDOR_UNKNOWN 0xff
222
223/*
224 * capabilities of CPUs
225 */
226extern struct cpuinfo_x86 boot_cpu_data;
227extern struct cpuinfo_x86 new_cpu_data;
228
229extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
230extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
231
232DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
233#define cpu_data(cpu) per_cpu(cpu_info, cpu)
234
235extern const struct seq_operations cpuinfo_op;
236
237#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
238
239extern void cpu_detect(struct cpuinfo_x86 *c);
240
241static inline unsigned long long l1tf_pfn_limit(void)
242{
243 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
244}
245
246void init_cpu_devs(void);
247void get_cpu_vendor(struct cpuinfo_x86 *c);
248extern void early_cpu_init(void);
249extern void identify_secondary_cpu(unsigned int cpu);
250extern void print_cpu_info(struct cpuinfo_x86 *);
251void print_cpu_msr(struct cpuinfo_x86 *);
252extern u32 intel_get_platform_id(void);
253
254/*
255 * Friendlier CR3 helpers.
256 */
257static inline unsigned long read_cr3_pa(void)
258{
259 return __read_cr3() & CR3_ADDR_MASK;
260}
261
262static inline unsigned long native_read_cr3_pa(void)
263{
264 return __native_read_cr3() & CR3_ADDR_MASK;
265}
266
267static inline void load_cr3(pgd_t *pgdir)
268{
269 write_cr3(__sme_pa(pgdir));
270}
271
272/*
273 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
274 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
275 * unrelated to the task-switch mechanism:
276 */
277#ifdef CONFIG_X86_32
278/* This is the TSS defined by the hardware. */
279struct x86_hw_tss {
280 unsigned short back_link, __blh;
281 unsigned long sp0;
282 unsigned short ss0, __ss0h;
283 unsigned long sp1;
284
285 /*
286 * We don't use ring 1, so ss1 is a convenient scratch space in
287 * the same cacheline as sp0. We use ss1 to cache the value in
288 * MSR_IA32_SYSENTER_CS. When we context switch
289 * MSR_IA32_SYSENTER_CS, we first check if the new value being
290 * written matches ss1, and, if it's not, then we wrmsr the new
291 * value and update ss1.
292 *
293 * The only reason we context switch MSR_IA32_SYSENTER_CS is
294 * that we set it to zero in vm86 tasks to avoid corrupting the
295 * stack if we were to go through the sysenter path from vm86
296 * mode.
297 */
298 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
299
300 unsigned short __ss1h;
301 unsigned long sp2;
302 unsigned short ss2, __ss2h;
303 unsigned long __cr3;
304 unsigned long ip;
305 unsigned long flags;
306 unsigned long ax;
307 unsigned long cx;
308 unsigned long dx;
309 unsigned long bx;
310 unsigned long sp;
311 unsigned long bp;
312 unsigned long si;
313 unsigned long di;
314 unsigned short es, __esh;
315 unsigned short cs, __csh;
316 unsigned short ss, __ssh;
317 unsigned short ds, __dsh;
318 unsigned short fs, __fsh;
319 unsigned short gs, __gsh;
320 unsigned short ldt, __ldth;
321 unsigned short trace;
322 unsigned short io_bitmap_base;
323
324} __attribute__((packed));
325#else
326struct x86_hw_tss {
327 u32 reserved1;
328 u64 sp0;
329 u64 sp1;
330
331 /*
332 * Since Linux does not use ring 2, the 'sp2' slot is unused by
333 * hardware. entry_SYSCALL_64 uses it as scratch space to stash
334 * the user RSP value.
335 */
336 u64 sp2;
337
338 u64 reserved2;
339 u64 ist[7];
340 u32 reserved3;
341 u32 reserved4;
342 u16 reserved5;
343 u16 io_bitmap_base;
344
345} __attribute__((packed));
346#endif
347
348/*
349 * IO-bitmap sizes:
350 */
351#define IO_BITMAP_BITS 65536
352#define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE)
353#define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long))
354
355#define IO_BITMAP_OFFSET_VALID_MAP \
356 (offsetof(struct tss_struct, io_bitmap.bitmap) - \
357 offsetof(struct tss_struct, x86_tss))
358
359#define IO_BITMAP_OFFSET_VALID_ALL \
360 (offsetof(struct tss_struct, io_bitmap.mapall) - \
361 offsetof(struct tss_struct, x86_tss))
362
363#ifdef CONFIG_X86_IOPL_IOPERM
364/*
365 * sizeof(unsigned long) coming from an extra "long" at the end of the
366 * iobitmap. The limit is inclusive, i.e. the last valid byte.
367 */
368# define __KERNEL_TSS_LIMIT \
369 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
370 sizeof(unsigned long) - 1)
371#else
372# define __KERNEL_TSS_LIMIT \
373 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
374#endif
375
376/* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */
377#define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1)
378
379struct entry_stack {
380 char stack[PAGE_SIZE];
381};
382
383struct entry_stack_page {
384 struct entry_stack stack;
385} __aligned(PAGE_SIZE);
386
387/*
388 * All IO bitmap related data stored in the TSS:
389 */
390struct x86_io_bitmap {
391 /* The sequence number of the last active bitmap. */
392 u64 prev_sequence;
393
394 /*
395 * Store the dirty size of the last io bitmap offender. The next
396 * one will have to do the cleanup as the switch out to a non io
397 * bitmap user will just set x86_tss.io_bitmap_base to a value
398 * outside of the TSS limit. So for sane tasks there is no need to
399 * actually touch the io_bitmap at all.
400 */
401 unsigned int prev_max;
402
403 /*
404 * The extra 1 is there because the CPU will access an
405 * additional byte beyond the end of the IO permission
406 * bitmap. The extra byte must be all 1 bits, and must
407 * be within the limit.
408 */
409 unsigned long bitmap[IO_BITMAP_LONGS + 1];
410
411 /*
412 * Special I/O bitmap to emulate IOPL(3). All bytes zero,
413 * except the additional byte at the end.
414 */
415 unsigned long mapall[IO_BITMAP_LONGS + 1];
416};
417
418struct tss_struct {
419 /*
420 * The fixed hardware portion. This must not cross a page boundary
421 * at risk of violating the SDM's advice and potentially triggering
422 * errata.
423 */
424 struct x86_hw_tss x86_tss;
425
426 struct x86_io_bitmap io_bitmap;
427} __aligned(PAGE_SIZE);
428
429DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
430
431/* Per CPU interrupt stacks */
432struct irq_stack {
433 char stack[IRQ_STACK_SIZE];
434} __aligned(IRQ_STACK_SIZE);
435
436DECLARE_PER_CPU_CACHE_HOT(struct irq_stack *, hardirq_stack_ptr);
437#ifdef CONFIG_X86_64
438DECLARE_PER_CPU_CACHE_HOT(bool, hardirq_stack_inuse);
439#else
440DECLARE_PER_CPU_CACHE_HOT(struct irq_stack *, softirq_stack_ptr);
441#endif
442
443DECLARE_PER_CPU_CACHE_HOT(unsigned long, cpu_current_top_of_stack);
444/* const-qualified alias provided by the linker. */
445DECLARE_PER_CPU_CACHE_HOT(const unsigned long __percpu_seg_override,
446 const_cpu_current_top_of_stack);
447
448#ifdef CONFIG_X86_64
449static inline unsigned long cpu_kernelmode_gs_base(int cpu)
450{
451#ifdef CONFIG_SMP
452 return per_cpu_offset(cpu);
453#else
454 return 0;
455#endif
456}
457
458extern asmlinkage void entry_SYSCALL32_ignore(void);
459
460/* Save actual FS/GS selectors and bases to current->thread */
461void current_save_fsgs(void);
462#endif /* X86_64 */
463
464struct perf_event;
465
466struct thread_struct {
467 /* Cached TLS descriptors: */
468 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
469#ifdef CONFIG_X86_32
470 unsigned long sp0;
471#endif
472 unsigned long sp;
473#ifdef CONFIG_X86_32
474 unsigned long sysenter_cs;
475#else
476 unsigned short es;
477 unsigned short ds;
478 unsigned short fsindex;
479 unsigned short gsindex;
480#endif
481
482#ifdef CONFIG_X86_64
483 unsigned long fsbase;
484 unsigned long gsbase;
485#else
486 /*
487 * XXX: this could presumably be unsigned short. Alternatively,
488 * 32-bit kernels could be taught to use fsindex instead.
489 */
490 unsigned long fs;
491 unsigned long gs;
492#endif
493
494 /* Save middle states of ptrace breakpoints */
495 struct perf_event *ptrace_bps[HBP_NUM];
496 /* Debug status used for traps, single steps, etc... */
497 unsigned long virtual_dr6;
498 /* Keep track of the exact dr7 value set by the user */
499 unsigned long ptrace_dr7;
500 /* Fault info: */
501 unsigned long cr2;
502 unsigned long trap_nr;
503 unsigned long error_code;
504#ifdef CONFIG_VM86
505 /* Virtual 86 mode info */
506 struct vm86 *vm86;
507#endif
508 /* IO permissions: */
509 struct io_bitmap *io_bitmap;
510
511 /*
512 * IOPL. Privilege level dependent I/O permission which is
513 * emulated via the I/O bitmap to prevent user space from disabling
514 * interrupts.
515 */
516 unsigned long iopl_emul;
517
518 unsigned int iopl_warn:1;
519
520 /*
521 * Protection Keys Register for Userspace. Loaded immediately on
522 * context switch. Store it in thread_struct to avoid a lookup in
523 * the tasks's FPU xstate buffer. This value is only valid when a
524 * task is scheduled out. For 'current' the authoritative source of
525 * PKRU is the hardware itself.
526 */
527 u32 pkru;
528
529#ifdef CONFIG_X86_USER_SHADOW_STACK
530 unsigned long features;
531 unsigned long features_locked;
532
533 struct thread_shstk shstk;
534#endif
535};
536
537#ifdef CONFIG_X86_DEBUG_FPU
538extern struct fpu *x86_task_fpu(struct task_struct *task);
539#else
540# define x86_task_fpu(task) ((struct fpu *)((void *)(task) + sizeof(*(task))))
541#endif
542
543extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size);
544
545static inline void arch_thread_struct_whitelist(unsigned long *offset,
546 unsigned long *size)
547{
548 fpu_thread_struct_whitelist(offset, size);
549}
550
551static inline void
552native_load_sp0(unsigned long sp0)
553{
554 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
555}
556
557static __always_inline void native_swapgs(void)
558{
559#ifdef CONFIG_X86_64
560 asm volatile("swapgs" ::: "memory");
561#endif
562}
563
564static __always_inline unsigned long current_top_of_stack(void)
565{
566 /*
567 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
568 * and around vm86 mode and sp0 on x86_64 is special because of the
569 * entry trampoline.
570 */
571 if (IS_ENABLED(CONFIG_USE_X86_SEG_SUPPORT))
572 return this_cpu_read_const(const_cpu_current_top_of_stack);
573
574 return this_cpu_read_stable(cpu_current_top_of_stack);
575}
576
577static __always_inline bool on_thread_stack(void)
578{
579 return (unsigned long)(current_top_of_stack() -
580 current_stack_pointer) < THREAD_SIZE;
581}
582
583#ifdef CONFIG_PARAVIRT_XXL
584#include <asm/paravirt.h>
585#else
586
587static inline void load_sp0(unsigned long sp0)
588{
589 native_load_sp0(sp0);
590}
591
592#endif /* CONFIG_PARAVIRT_XXL */
593
594unsigned long __get_wchan(struct task_struct *p);
595
596extern void select_idle_routine(void);
597extern void amd_e400_c1e_apic_setup(void);
598
599extern unsigned long boot_option_idle_override;
600
601enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
602 IDLE_POLL};
603
604extern void enable_sep_cpu(void);
605
606
607/* Defined in head.S */
608extern struct desc_ptr early_gdt_descr;
609
610extern void switch_gdt_and_percpu_base(int);
611extern void load_direct_gdt(int);
612extern void load_fixmap_gdt(int);
613extern void cpu_init(void);
614extern void cpu_init_exception_handling(bool boot_cpu);
615extern void cpu_init_replace_early_idt(void);
616extern void cr4_init(void);
617
618extern void set_task_blockstep(struct task_struct *task, bool on);
619
620/* Boot loader type from the setup header: */
621extern int bootloader_type;
622extern int bootloader_version;
623
624extern char ignore_fpu_irq;
625
626#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
627#define ARCH_HAS_PREFETCHW
628
629#ifdef CONFIG_X86_32
630# define BASE_PREFETCH ""
631# define ARCH_HAS_PREFETCH
632#else
633# define BASE_PREFETCH "prefetcht0 %1"
634#endif
635
636/*
637 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
638 *
639 * It's not worth to care about 3dnow prefetches for the K6
640 * because they are microcoded there and very slow.
641 */
642static inline void prefetch(const void *x)
643{
644 alternative_input(BASE_PREFETCH, "prefetchnta %1",
645 X86_FEATURE_XMM,
646 "m" (*(const char *)x));
647}
648
649/*
650 * 3dnow prefetch to get an exclusive cache line.
651 * Useful for spinlocks to avoid one state transition in the
652 * cache coherency protocol:
653 */
654static __always_inline void prefetchw(const void *x)
655{
656 alternative_input(BASE_PREFETCH, "prefetchw %1",
657 X86_FEATURE_3DNOWPREFETCH,
658 "m" (*(const char *)x));
659}
660
661#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
662 TOP_OF_KERNEL_STACK_PADDING)
663
664#define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
665
666#define task_pt_regs(task) \
667({ \
668 unsigned long __ptr = (unsigned long)task_stack_page(task); \
669 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
670 ((struct pt_regs *)__ptr) - 1; \
671})
672
673#ifdef CONFIG_X86_32
674#define INIT_THREAD { \
675 .sp0 = TOP_OF_INIT_STACK, \
676 .sysenter_cs = __KERNEL_CS, \
677}
678
679#else
680extern unsigned long __top_init_kernel_stack[];
681
682#define INIT_THREAD { \
683 .sp = (unsigned long)&__top_init_kernel_stack, \
684}
685
686#endif /* CONFIG_X86_64 */
687
688extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
689 unsigned long new_sp);
690
691/*
692 * This decides where the kernel will search for a free chunk of vm
693 * space during mmap's.
694 */
695#define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
696#define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
697
698#define KSTK_EIP(task) (task_pt_regs(task)->ip)
699#define KSTK_ESP(task) (task_pt_regs(task)->sp)
700
701/* Get/set a process' ability to use the timestamp counter instruction */
702#define GET_TSC_CTL(adr) get_tsc_mode((adr))
703#define SET_TSC_CTL(val) set_tsc_mode((val))
704
705extern int get_tsc_mode(unsigned long adr);
706extern int set_tsc_mode(unsigned int val);
707
708DECLARE_PER_CPU(u64, msr_misc_features_shadow);
709
710static inline u32 per_cpu_llc_id(unsigned int cpu)
711{
712 return per_cpu(cpu_info.topo.llc_id, cpu);
713}
714
715static inline u32 per_cpu_l2c_id(unsigned int cpu)
716{
717 return per_cpu(cpu_info.topo.l2c_id, cpu);
718}
719
720static inline u32 per_cpu_core_id(unsigned int cpu)
721{
722 return per_cpu(cpu_info.topo.core_id, cpu);
723}
724
725#ifdef CONFIG_CPU_SUP_AMD
726/*
727 * Issue a DIV 0/1 insn to clear any division data from previous DIV
728 * operations.
729 */
730static __always_inline void amd_clear_divider(void)
731{
732 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0)
733 :: "a" (0), "d" (0), "r" (1));
734}
735
736extern void amd_check_microcode(void);
737#else
738static inline void amd_clear_divider(void) { }
739static inline void amd_check_microcode(void) { }
740#endif
741
742extern unsigned long arch_align_stack(unsigned long sp);
743void free_init_pages(const char *what, unsigned long begin, unsigned long end);
744extern void free_kernel_image_pages(const char *what, void *begin, void *end);
745
746void default_idle(void);
747#ifdef CONFIG_XEN
748bool xen_set_default_idle(void);
749#else
750#define xen_set_default_idle 0
751#endif
752
753void __noreturn stop_this_cpu(void *dummy);
754extern bool x86_hypervisor_present;
755void microcode_check(struct cpuinfo_x86 *prev_info);
756void store_cpu_caps(struct cpuinfo_x86 *info);
757
758DECLARE_PER_CPU(bool, cache_state_incoherent);
759
760enum l1tf_mitigations {
761 L1TF_MITIGATION_OFF,
762 L1TF_MITIGATION_AUTO,
763 L1TF_MITIGATION_FLUSH_NOWARN,
764 L1TF_MITIGATION_FLUSH,
765 L1TF_MITIGATION_FLUSH_NOSMT,
766 L1TF_MITIGATION_FULL,
767 L1TF_MITIGATION_FULL_FORCE
768};
769
770extern enum l1tf_mitigations l1tf_mitigation;
771
772enum mds_mitigations {
773 MDS_MITIGATION_OFF,
774 MDS_MITIGATION_AUTO,
775 MDS_MITIGATION_FULL,
776 MDS_MITIGATION_VMWERV,
777};
778
779extern bool gds_ucode_mitigated(void);
780
781/*
782 * Make previous memory operations globally visible before
783 * a WRMSR.
784 *
785 * MFENCE makes writes visible, but only affects load/store
786 * instructions. WRMSR is unfortunately not a load/store
787 * instruction and is unaffected by MFENCE. The LFENCE ensures
788 * that the WRMSR is not reordered.
789 *
790 * Most WRMSRs are full serializing instructions themselves and
791 * do not require this barrier. This is only required for the
792 * IA32_TSC_DEADLINE and X2APIC MSRs.
793 */
794static inline void weak_wrmsr_fence(void)
795{
796 alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE));
797}
798
799#endif /* _ASM_X86_PROCESSOR_H */